watchdog: sp5100_tco: Add support for recent FCH versions
Starting with Family 16h Models 30h-3Fh and Family 15h Models 60h-6Fh, watchdog address space decoding has changed. The cutover point is already identified in the i2c-piix2 driver, so use the same mechanism. Cc: Zoltán Böszörményi <zboszor@pr.hu> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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@ -16,6 +16,11 @@
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* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
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* AMD Publication 45482 "AMD SB800-Series Southbridges Register
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* Reference Guide"
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* AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
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* for AMD Family 16h Models 00h-0Fh Processors"
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* AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
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* AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
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* for AMD Family 16h Models 30h-3Fh Processors"
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*/
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/*
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@ -40,9 +45,14 @@
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/* internal variables */
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enum tco_reg_layout {
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sp5100, sb800, efch
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};
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struct sp5100_tco {
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struct watchdog_device wdd;
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void __iomem *tcobase;
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enum tco_reg_layout tco_reg_layout;
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};
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/* the watchdog platform device */
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@ -67,10 +77,20 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
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* Some TCO specific functions
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*/
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static bool tco_has_sp5100_reg_layout(struct pci_dev *dev)
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static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
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{
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return dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
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dev->revision < 0x40;
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if (dev->vendor == PCI_VENDOR_ID_ATI &&
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dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
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dev->revision < 0x40) {
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return sp5100;
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} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
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((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
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dev->revision >= 0x41) ||
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(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
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dev->revision >= 0x49))) {
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return efch;
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}
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return sb800;
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}
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static int tco_timer_start(struct watchdog_device *wdd)
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@ -139,9 +159,12 @@ static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
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outb(val, SP5100_IO_PM_DATA_REG);
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}
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static void tco_timer_enable(void)
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static void tco_timer_enable(struct sp5100_tco *tco)
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{
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if (!tco_has_sp5100_reg_layout(sp5100_tco_pci)) {
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u32 val;
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switch (tco->tco_reg_layout) {
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case sb800:
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/* For SB800 or later */
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/* Set the Watchdog timer resolution to 1 sec */
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sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
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@ -151,9 +174,8 @@ static void tco_timer_enable(void)
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sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
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~SB800_PM_WATCHDOG_DISABLE,
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SB800_PCI_WATCHDOG_DECODE_EN);
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} else {
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u32 val;
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break;
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case sp5100:
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/* For SP5100 or SB7x0 */
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/* Enable watchdog decode bit */
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pci_read_config_dword(sp5100_tco_pci,
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@ -170,6 +192,13 @@ static void tco_timer_enable(void)
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sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
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~SP5100_PM_WATCHDOG_DISABLE,
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SP5100_PM_WATCHDOG_SECOND_RES);
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break;
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case efch:
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/* Set the Watchdog timer resolution to 1 sec and enable */
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sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
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~EFCH_PM_WATCHDOG_DISABLE,
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EFCH_PM_DECODEEN_SECOND_RES);
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break;
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}
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}
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@ -189,89 +218,113 @@ static int sp5100_tco_setupdevice(struct device *dev,
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{
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struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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const char *dev_name;
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u8 base_addr;
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u32 val;
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u32 mmio_addr = 0, val;
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int ret;
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/*
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* Determine type of southbridge chipset.
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*/
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if (tco_has_sp5100_reg_layout(sp5100_tco_pci)) {
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dev_name = SP5100_DEVNAME;
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base_addr = SP5100_PM_WATCHDOG_BASE;
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} else {
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dev_name = SB800_DEVNAME;
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base_addr = SB800_PM_WATCHDOG_BASE;
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}
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/* Request the IO ports used by this driver */
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if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
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SP5100_PM_IOPORTS_SIZE, dev_name)) {
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SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
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dev_err(dev, "I/O address 0x%04x already in use\n",
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SP5100_IO_PM_INDEX_REG);
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return -EBUSY;
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}
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/*
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* First, Find the watchdog timer MMIO address from indirect I/O.
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* Low three bits of BASE are reserved.
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* Determine type of southbridge chipset.
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*/
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val = sp5100_tco_read_pm_reg32(base_addr) & 0xfffffff8;
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dev_dbg(dev, "Got 0x%04x from indirect I/O\n", val);
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switch (tco->tco_reg_layout) {
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case sp5100:
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dev_name = SP5100_DEVNAME;
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mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
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0xfffffff8;
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break;
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case sb800:
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dev_name = SB800_DEVNAME;
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mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
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0xfffffff8;
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break;
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case efch:
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dev_name = SB800_DEVNAME;
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val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
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if (val & EFCH_PM_DECODEEN_WDT_TMREN)
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mmio_addr = EFCH_PM_WDT_ADDR;
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break;
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default:
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return -ENODEV;
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}
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/* Check MMIO address conflict */
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if (!devm_request_mem_region(dev, val, SP5100_WDT_MEM_MAP_SIZE,
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if (!mmio_addr ||
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!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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dev_dbg(dev, "MMIO address 0x%04x already in use\n", val);
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/*
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* Secondly, Find the watchdog timer MMIO address
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* from SBResource_MMIO register.
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*/
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if (tco_has_sp5100_reg_layout(sp5100_tco_pci)) {
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if (mmio_addr)
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dev_dbg(dev, "MMIO address 0x%08x already in use\n",
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mmio_addr);
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switch (tco->tco_reg_layout) {
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case sp5100:
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/*
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* Secondly, Find the watchdog timer MMIO address
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* from SBResource_MMIO register.
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*/
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/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
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pci_read_config_dword(sp5100_tco_pci,
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SP5100_SB_RESOURCE_MMIO_BASE,
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&val);
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} else {
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/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
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val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
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}
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/* The SBResource_MMIO is enabled and mapped memory space? */
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if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) !=
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&mmio_addr);
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if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
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SB800_ACPI_MMIO_SEL)) !=
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SB800_ACPI_MMIO_DECODE_EN) {
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dev_notice(dev,
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"failed to find MMIO address, giving up.\n");
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ret = -ENODEV;
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goto unreg_region;
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr &= ~0xFFF;
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mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
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break;
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case sb800:
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/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
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mmio_addr =
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sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
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if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
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SB800_ACPI_MMIO_SEL)) !=
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SB800_ACPI_MMIO_DECODE_EN) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr &= ~0xFFF;
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mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
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break;
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case efch:
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val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
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if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
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ret = -ENODEV;
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goto unreg_region;
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}
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mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
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EFCH_PM_ACPI_MMIO_WDT_OFFSET;
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break;
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}
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/* Clear unnecessary the low twelve bits */
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val &= ~0xFFF;
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/* Add the Watchdog Timer offset to base address. */
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val += SB800_PM_WDT_MMIO_OFFSET;
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/* Check MMIO address conflict */
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if (!devm_request_mem_region(dev, val, SP5100_WDT_MEM_MAP_SIZE,
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dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
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mmio_addr);
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if (!devm_request_mem_region(dev, mmio_addr,
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SP5100_WDT_MEM_MAP_SIZE,
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dev_name)) {
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dev_dbg(dev, "MMIO address 0x%04x already in use\n",
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val);
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dev_dbg(dev, "MMIO address 0x%08x already in use\n",
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mmio_addr);
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ret = -EBUSY;
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goto unreg_region;
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}
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dev_dbg(dev, "Got 0x%04x from SBResource_MMIO register\n", val);
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}
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tco->tcobase = devm_ioremap(dev, val, SP5100_WDT_MEM_MAP_SIZE);
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tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
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if (!tco->tcobase) {
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dev_err(dev, "failed to get tcobase address\n");
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ret = -ENOMEM;
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goto unreg_region;
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}
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dev_info(dev, "Using 0x%04x for watchdog MMIO address\n", val);
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dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
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/* Setup the watchdog timer */
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tco_timer_enable();
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tco_timer_enable(tco);
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val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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if (val & SP5100_WDT_DISABLED) {
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@ -332,6 +385,8 @@ static int sp5100_tco_probe(struct platform_device *pdev)
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if (!tco)
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return -ENOMEM;
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tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
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wdd = &tco->wdd;
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wdd->parent = dev;
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wdd->info = &sp5100_tco_wdt_info;
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@ -62,3 +62,24 @@
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#define SB800_PM_WDT_MMIO_OFFSET 0xB00
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#define SB800_DEVNAME "SB800 TCO"
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/* For recent chips with embedded FCH (rev 40+) */
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#define EFCH_PM_DECODEEN 0x00
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#define EFCH_PM_DECODEEN_WDT_TMREN BIT(7)
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#define EFCH_PM_DECODEEN3 0x00
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#define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)
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#define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2))
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/* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
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#define EFCH_PM_WDT_ADDR 0xfeb00000
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#define EFCH_PM_ISACONTROL 0x04
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#define EFCH_PM_ISACONTROL_MMIOEN BIT(1)
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#define EFCH_PM_ACPI_MMIO_ADDR 0xfed80000
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#define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b00
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