KVM: Add MCE support
The related MSRs are emulated. MCE capability is exported via extension KVM_CAP_MCE and ioctl KVM_X86_GET_MCE_CAP_SUPPORTED. A new vcpu ioctl command KVM_X86_SETUP_MCE is used to setup MCE emulation such as the mcg_cap. MCE is injected via vcpu ioctl command KVM_X86_SET_MCE. Extended machine-check state (MCG_EXT_P) and CMCI are not implemented. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
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890ca9aefa
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@ -17,6 +17,7 @@
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#define __KVM_HAVE_USER_NMI
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_MSIX
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#define __KVM_HAVE_MCE
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/* Architectural interrupt line count. */
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#define KVM_NR_INTERRUPTS 256
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@ -373,6 +373,11 @@ struct kvm_vcpu_arch {
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unsigned long dr6;
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unsigned long dr7;
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unsigned long eff_db[KVM_NR_DB_REGS];
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u64 mcg_cap;
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u64 mcg_status;
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u64 mcg_ctl;
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u64 *mce_banks;
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};
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struct kvm_mem_alias {
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@ -42,6 +42,7 @@
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#include <asm/msr.h>
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#include <asm/desc.h>
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#include <asm/mtrr.h>
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#include <asm/mce.h>
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#define MAX_IO_MSRS 256
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#define CR0_RESERVED_BITS \
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@ -55,6 +56,10 @@
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| X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
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#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
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#define KVM_MAX_MCE_BANKS 32
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#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
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/* EFER defaults:
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* - enable syscall per default because its emulated by KVM
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* - enable LME and LMA per default on 64 bit KVM
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@ -777,24 +782,44 @@ static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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return 0;
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}
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static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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{
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u64 mcg_cap = vcpu->arch.mcg_cap;
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unsigned bank_num = mcg_cap & 0xff;
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switch (msr) {
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case MSR_IA32_MCG_STATUS:
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vcpu->arch.mcg_status = data;
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break;
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case MSR_IA32_MCG_CTL:
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if (!(mcg_cap & MCG_CTL_P))
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return 1;
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if (data != 0 && data != ~(u64)0)
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return -1;
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vcpu->arch.mcg_ctl = data;
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break;
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default:
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if (msr >= MSR_IA32_MC0_CTL &&
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msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
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u32 offset = msr - MSR_IA32_MC0_CTL;
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/* only 0 or all 1s can be written to IA32_MCi_CTL */
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if ((offset & 0x3) == 0 &&
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data != 0 && data != ~(u64)0)
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return -1;
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vcpu->arch.mce_banks[offset] = data;
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break;
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}
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return 1;
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}
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return 0;
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}
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int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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{
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switch (msr) {
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case MSR_EFER:
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set_efer(vcpu, data);
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break;
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case MSR_IA32_MC0_STATUS:
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pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
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__func__, data);
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break;
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case MSR_IA32_MCG_STATUS:
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pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
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__func__, data);
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break;
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case MSR_IA32_MCG_CTL:
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pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
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__func__, data);
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break;
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case MSR_IA32_DEBUGCTLMSR:
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if (!data) {
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/* We support the non-activated case already */
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@ -849,6 +874,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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kvm_request_guest_time_update(vcpu);
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break;
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}
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case MSR_IA32_MCG_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
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return set_msr_mce(vcpu, msr, data);
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default:
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pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
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return 1;
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@ -904,6 +933,41 @@ static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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return 0;
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}
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static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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{
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u64 data;
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u64 mcg_cap = vcpu->arch.mcg_cap;
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unsigned bank_num = mcg_cap & 0xff;
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switch (msr) {
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case MSR_IA32_P5_MC_ADDR:
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case MSR_IA32_P5_MC_TYPE:
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data = 0;
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break;
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case MSR_IA32_MCG_CAP:
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data = vcpu->arch.mcg_cap;
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break;
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case MSR_IA32_MCG_CTL:
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if (!(mcg_cap & MCG_CTL_P))
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return 1;
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data = vcpu->arch.mcg_ctl;
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break;
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case MSR_IA32_MCG_STATUS:
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data = vcpu->arch.mcg_status;
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break;
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default:
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if (msr >= MSR_IA32_MC0_CTL &&
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msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
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u32 offset = msr - MSR_IA32_MC0_CTL;
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data = vcpu->arch.mce_banks[offset];
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break;
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}
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return 1;
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}
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*pdata = data;
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return 0;
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}
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int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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{
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u64 data;
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@ -912,18 +976,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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case 0xc0010010: /* SYSCFG */
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case 0xc0010015: /* HWCR */
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case MSR_IA32_PLATFORM_ID:
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case MSR_IA32_P5_MC_ADDR:
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case MSR_IA32_P5_MC_TYPE:
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case MSR_IA32_MC0_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MCG_CAP:
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case MSR_IA32_MCG_CTL:
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case MSR_IA32_MC0_MISC:
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case MSR_IA32_MC0_MISC+4:
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case MSR_IA32_MC0_MISC+8:
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case MSR_IA32_MC0_MISC+12:
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case MSR_IA32_MC0_MISC+16:
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case MSR_IA32_MC0_MISC+20:
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case MSR_IA32_UCODE_REV:
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case MSR_IA32_EBL_CR_POWERON:
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case MSR_IA32_DEBUGCTLMSR:
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@ -966,6 +1018,13 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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case MSR_KVM_SYSTEM_TIME:
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data = vcpu->arch.time;
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break;
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case MSR_IA32_P5_MC_ADDR:
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case MSR_IA32_P5_MC_TYPE:
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case MSR_IA32_MCG_CAP:
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case MSR_IA32_MCG_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
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return get_msr_mce(vcpu, msr, pdata);
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default:
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pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
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return 1;
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@ -1087,6 +1146,9 @@ int kvm_dev_ioctl_check_extension(long ext)
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case KVM_CAP_IOMMU:
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r = iommu_found();
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break;
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case KVM_CAP_MCE:
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r = KVM_MAX_MCE_BANKS;
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break;
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default:
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r = 0;
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break;
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r = 0;
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break;
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}
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case KVM_X86_GET_MCE_CAP_SUPPORTED: {
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u64 mce_cap;
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mce_cap = KVM_MCE_CAP_SUPPORTED;
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r = -EFAULT;
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if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
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goto out;
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r = 0;
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break;
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}
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default:
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r = -EINVAL;
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}
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return 0;
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}
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static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
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u64 mcg_cap)
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{
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int r;
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unsigned bank_num = mcg_cap & 0xff, bank;
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r = -EINVAL;
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if (!bank_num)
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goto out;
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if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
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goto out;
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r = 0;
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vcpu->arch.mcg_cap = mcg_cap;
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/* Init IA32_MCG_CTL to all 1s */
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if (mcg_cap & MCG_CTL_P)
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vcpu->arch.mcg_ctl = ~(u64)0;
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/* Init IA32_MCi_CTL to all 1s */
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for (bank = 0; bank < bank_num; bank++)
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vcpu->arch.mce_banks[bank*4] = ~(u64)0;
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out:
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return r;
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}
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static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
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struct kvm_x86_mce *mce)
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{
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u64 mcg_cap = vcpu->arch.mcg_cap;
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unsigned bank_num = mcg_cap & 0xff;
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u64 *banks = vcpu->arch.mce_banks;
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if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
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return -EINVAL;
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/*
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* if IA32_MCG_CTL is not all 1s, the uncorrected error
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* reporting is disabled
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*/
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if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
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vcpu->arch.mcg_ctl != ~(u64)0)
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return 0;
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banks += 4 * mce->bank;
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/*
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* if IA32_MCi_CTL is not all 1s, the uncorrected error
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* reporting is disabled for the bank
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*/
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if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
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return 0;
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if (mce->status & MCI_STATUS_UC) {
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if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
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!(vcpu->arch.cr4 & X86_CR4_MCE)) {
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printk(KERN_DEBUG "kvm: set_mce: "
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"injects mce exception while "
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"previous one is in progress!\n");
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set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
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return 0;
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}
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if (banks[1] & MCI_STATUS_VAL)
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mce->status |= MCI_STATUS_OVER;
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banks[2] = mce->addr;
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banks[3] = mce->misc;
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vcpu->arch.mcg_status = mce->mcg_status;
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banks[1] = mce->status;
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kvm_queue_exception(vcpu, MC_VECTOR);
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} else if (!(banks[1] & MCI_STATUS_VAL)
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|| !(banks[1] & MCI_STATUS_UC)) {
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if (banks[1] & MCI_STATUS_VAL)
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mce->status |= MCI_STATUS_OVER;
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banks[2] = mce->addr;
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banks[3] = mce->misc;
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banks[1] = mce->status;
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} else
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banks[1] |= MCI_STATUS_OVER;
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return 0;
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}
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long kvm_arch_vcpu_ioctl(struct file *filp,
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unsigned int ioctl, unsigned long arg)
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{
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kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
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break;
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}
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case KVM_X86_SETUP_MCE: {
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u64 mcg_cap;
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r = -EFAULT;
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if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
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goto out;
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r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
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break;
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}
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case KVM_X86_SET_MCE: {
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struct kvm_x86_mce mce;
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r = -EFAULT;
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if (copy_from_user(&mce, argp, sizeof mce))
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goto out;
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r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
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break;
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}
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default:
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r = -EINVAL;
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}
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@ -4440,6 +4604,14 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
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goto fail_mmu_destroy;
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}
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vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
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GFP_KERNEL);
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if (!vcpu->arch.mce_banks) {
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r = -ENOMEM;
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goto fail_mmu_destroy;
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}
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vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
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return 0;
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fail_mmu_destroy:
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@ -415,6 +415,9 @@ struct kvm_trace_rec {
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#define KVM_CAP_ASSIGN_DEV_IRQ 29
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/* Another bug in KVM_SET_USER_MEMORY_REGION fixed: */
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#define KVM_CAP_JOIN_MEMORY_REGIONS_WORKS 30
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#ifdef __KVM_HAVE_MCE
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#define KVM_CAP_MCE 31
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#endif
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#ifdef KVM_CAP_IRQ_ROUTING
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#endif
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#ifdef KVM_CAP_MCE
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/* x86 MCE */
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struct kvm_x86_mce {
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__u64 status;
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__u64 addr;
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__u64 misc;
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__u64 mcg_status;
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__u8 bank;
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__u8 pad1[7];
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__u64 pad2[3];
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};
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#endif
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/*
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* ioctls for VM fds
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*/
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@ -541,6 +557,10 @@ struct kvm_irq_routing {
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#define KVM_NMI _IO(KVMIO, 0x9a)
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/* Available with KVM_CAP_SET_GUEST_DEBUG */
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#define KVM_SET_GUEST_DEBUG _IOW(KVMIO, 0x9b, struct kvm_guest_debug)
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/* MCE for x86 */
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#define KVM_X86_SETUP_MCE _IOW(KVMIO, 0x9c, __u64)
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#define KVM_X86_GET_MCE_CAP_SUPPORTED _IOR(KVMIO, 0x9d, __u64)
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#define KVM_X86_SET_MCE _IOW(KVMIO, 0x9e, struct kvm_x86_mce)
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/*
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* Deprecated interfaces
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