ARM: SAMSUNG: Add tx_st_done variable
tx_st_done is required for checking the transmission status of SPI channels with different fifo levels Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
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.cfg_gpio = s3c64xx_spi_cfg_gpio,
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.tx_st_done = 21,
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};
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static u64 spi_dmamask = DMA_BIT_MASK(32);
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@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
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.cfg_gpio = s3c64xx_spi_cfg_gpio,
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.tx_st_done = 21,
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};
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struct platform_device s3c64xx_device_spi1 = {
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@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
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.cfg_gpio = s5p6440_spi_cfg_gpio,
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.fifo_lvl_mask = 0x1ff,
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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};
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static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
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.cfg_gpio = s5p6450_spi_cfg_gpio,
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.fifo_lvl_mask = 0x1ff,
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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};
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static u64 spi_dmamask = DMA_BIT_MASK(32);
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@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
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.cfg_gpio = s5p6440_spi_cfg_gpio,
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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};
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static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
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.cfg_gpio = s5p6450_spi_cfg_gpio,
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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};
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struct platform_device s5p64x0_device_spi1 = {
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@ -90,6 +90,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.high_speed = 1,
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.tx_st_done = 21,
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};
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static u64 spi_dmamask = DMA_BIT_MASK(32);
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@ -134,6 +135,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.high_speed = 1,
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.tx_st_done = 21,
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};
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struct platform_device s5pc100_device_spi1 = {
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@ -176,6 +178,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.high_speed = 1,
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.tx_st_done = 21,
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};
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struct platform_device s5pc100_device_spi2 = {
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@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
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.fifo_lvl_mask = 0x1ff,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.tx_st_done = 25,
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};
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static u64 spi_dmamask = DMA_BIT_MASK(32);
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@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 15,
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.high_speed = 1,
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.tx_st_done = 25,
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};
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struct platform_device s5pv210_device_spi1 = {
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@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo {
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* @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
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* @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
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* @high_speed: If the controller supports HIGH_SPEED_EN bit
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* @tx_st_done: Depends on tx fifo_lvl field
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*/
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struct s3c64xx_spi_info {
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int src_clk_nr;
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@ -53,6 +54,7 @@ struct s3c64xx_spi_info {
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int fifo_lvl_mask;
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int rx_lvl_offset;
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int high_speed;
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int tx_st_done;
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};
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/**
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