[POWERPC] Import updated version of ppc disassembly code for xmon
This includes: * version 1.24 of ppc-dis.c * version 1.88 of ppc-opc.c * version 1.23 of ppc.h I can't vouch for the accuracy etc. of these changes, but it brings us into line with binutils - and from a cursory test appears to work fine. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>wifi-calibration
Michael Ellerman
Paul Mackerras
parent
0b8e2e1310
commit
897f112bb4
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@ -1,5 +1,6 @@
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/* ppc-dis.c -- Disassemble PowerPC instructions
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Copyright 1994 Free Software Foundation, Inc.
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Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006
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Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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@ -16,8 +17,9 @@ the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#include <asm/cputable.h>
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#include "nonstdio.h"
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#include "ansidecl.h"
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#include "ppc.h"
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@ -36,6 +38,15 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
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dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
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if (cpu_has_feature(CPU_FTRS_POWER5))
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dialect |= PPC_OPCODE_POWER5;
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if (cpu_has_feature(CPU_FTRS_CELL))
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dialect |= PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
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if (cpu_has_feature(CPU_FTRS_POWER6))
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dialect |= PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
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/* Get the major opcode of the instruction. */
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op = PPC_OP (insn);
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@ -120,7 +131,8 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
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}
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/* Print the operand as directed by the flags. */
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if ((operand->flags & PPC_OPERAND_GPR) != 0)
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if ((operand->flags & PPC_OPERAND_GPR) != 0
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|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
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printf("r%ld", value);
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else if ((operand->flags & PPC_OPERAND_FPR) != 0)
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printf("f%ld", value);
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@ -136,7 +148,7 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
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else
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{
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if (operand->bits == 3)
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printf("cr%d", value);
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printf("cr%ld", value);
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else
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{
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static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
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File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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/* ppc.h -- Header file for PowerPC opcode table
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Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
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Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
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Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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@ -17,7 +17,7 @@ the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef PPC_H
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#define PPC_H
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@ -134,6 +134,18 @@ extern const int powerpc_num_opcodes;
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/* Opcode is supported by machine check APU. */
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#define PPC_OPCODE_RFMCI 0x800000
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/* Opcode is only supported by Power5 architecture. */
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#define PPC_OPCODE_POWER5 0x1000000
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/* Opcode is supported by PowerPC e300 family. */
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#define PPC_OPCODE_E300 0x2000000
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/* Opcode is only supported by Power6 architecture. */
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#define PPC_OPCODE_POWER6 0x4000000
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/* Opcode is only supported by PowerPC Cell family. */
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#define PPC_OPCODE_CELL 0x8000000
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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@ -233,25 +245,28 @@ extern const struct powerpc_operand powerpc_operands[];
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register names with a leading 'r'. */
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#define PPC_OPERAND_GPR (040)
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/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
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#define PPC_OPERAND_GPR_0 (0100)
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/* This operand names a floating point register. The disassembler
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prints these with a leading 'f'. */
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#define PPC_OPERAND_FPR (0100)
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#define PPC_OPERAND_FPR (0200)
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_RELATIVE (0200)
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#define PPC_OPERAND_RELATIVE (0400)
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_ABSOLUTE (0400)
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#define PPC_OPERAND_ABSOLUTE (01000)
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/* This operand is optional, and is zero if omitted. This is used for
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the optional BF and L fields in the comparison instructions. The
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example, in the optional BF field in the comparison instructions. The
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assembler must count the number of operands remaining on the line,
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and the number of operands remaining for the opcode, and decide
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whether this operand is present or not. The disassembler should
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print this operand out only if it is not zero. */
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#define PPC_OPERAND_OPTIONAL (01000)
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#define PPC_OPERAND_OPTIONAL (02000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then for the next operand use this operand value plus
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@ -259,24 +274,24 @@ extern const struct powerpc_operand powerpc_operands[];
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hack is needed because the Power rotate instructions can take
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either 4 or 5 operands. The disassembler should print this operand
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out regardless of the PPC_OPERAND_OPTIONAL field. */
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#define PPC_OPERAND_NEXT (02000)
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#define PPC_OPERAND_NEXT (04000)
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define PPC_OPERAND_NEGATIVE (04000)
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#define PPC_OPERAND_NEGATIVE (010000)
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/* This operand names a vector unit register. The disassembler
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prints these with a leading 'v'. */
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#define PPC_OPERAND_VR (010000)
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#define PPC_OPERAND_VR (020000)
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/* This operand is for the DS field in a DS form instruction. */
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#define PPC_OPERAND_DS (020000)
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#define PPC_OPERAND_DS (040000)
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/* This operand is for the DQ field in a DQ form instruction. */
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#define PPC_OPERAND_DQ (040000)
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#define PPC_OPERAND_DQ (0100000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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with the operands table for simplicity. The macro table is an
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