powerpc/85xx: Add TWR-P1025 board support
TWR-P1025 Overview ----------------- 512Mbyte DDR3 (on board DDR) 64MB Nor Flash eTSEC1: Connected to RGMII PHY AR8035 eTSEC3: Connected to RGMII PHY AR8035 Two USB2.0 Type A One microSD Card slot One mini-PCIe slot One mini-USB TypeB dual UART Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [scottwood@freescale.com: use pr_info rather than KERN_INFO] Signed-off-by: Scott Wood <scottwood@freescale.com>wifi-calibration
Xie Xiaobo
Scott Wood
parent
72c916ae97
commit
8a6be2bdb6
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@ -0,0 +1,13 @@
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* Solomon SSD1289 Framebuffer Driver
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Required properties:
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- compatible: Should be "solomon,ssd1289fb". The only supported bus for
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now is lbc.
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- reg: Should contain address of the controller on the LBC bus. The detail
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was described in Documentation/devicetree/bindings/powerpc/fsl/lbc.txt
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Examples:
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display@2,0 {
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compatible = "solomon,ssd1289fb";
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reg = <0x2 0x0000 0x0004>;
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};
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@ -0,0 +1,95 @@
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/*
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* P1025 TWR Device Tree Source (32-bit address map)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "fsl/p1021si-pre.dtsi"
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/ {
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model = "fsl,P1025";
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compatible = "fsl,TWR-P1025";
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memory {
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device_type = "memory";
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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/* NOR Flash and SSD1289 */
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ranges = <0x0 0x0 0x0 0xec000000 0x04000000
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0x2 0x0 0x0 0xe0000000 0x00020000>;
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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};
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pci0: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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reg = <0 0xffe09000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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qe: qe@ffe80000 {
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ranges = <0x0 0x0 0xffe80000 0x40000>;
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reg = <0 0xffe80000 0 0x480>;
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brg-frequency = <0>;
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bus-frequency = <0>;
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};
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};
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/include/ "p1025twr.dtsi"
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/include/ "fsl/p1021si-post.dtsi"
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@ -0,0 +1,280 @@
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/*
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* P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/{
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aliases {
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ethernet3 = &enet3;
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ethernet4 = &enet4;
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};
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};
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&lbc {
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* This location must not be altered */
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/* 256KB for Vitesse 7385 Switch firmware */
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reg = <0x0 0x00040000>;
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label = "NOR Vitesse-7385 Firmware";
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read-only;
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};
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partition@40000 {
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/* 256KB for DTB Image */
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reg = <0x00040000 0x00040000>;
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label = "NOR DTB Image";
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};
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partition@80000 {
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/* 5.5 MB for Linux Kernel Image */
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reg = <0x00080000 0x00580000>;
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label = "NOR Linux Kernel Image";
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};
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partition@400000 {
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/* 56.75MB for Root file System */
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reg = <0x00600000 0x038c0000>;
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label = "NOR Root File System";
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};
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partition@ec0000 {
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/* This location must not be altered */
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/* 256KB for QE ucode firmware*/
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reg = <0x03ec0000 0x00040000>;
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label = "NOR QE microcode firmware";
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read-only;
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};
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partition@f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x03f00000 0x00100000>;
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label = "NOR U-Boot Image";
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read-only;
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};
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};
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/* CS2 for Display */
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display@2,0 {
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compatible = "solomon,ssd1289fb";
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reg = <0x2 0x0000 0x0004>;
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};
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};
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&soc {
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usb@22000 {
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phy_type = "ulpi";
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};
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mdio@24000 {
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phy0: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1 0 0>;
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reg = <0x2>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25000 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26000 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet0: ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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par_io@e0100 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xe0100 0x60>;
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ranges = <0x0 0xe0100 0x60>;
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device_type = "par_io";
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num-ports = <3>;
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
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0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
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0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
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0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
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0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
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0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
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0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
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0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
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0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
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0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
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0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
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0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
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0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
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0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
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0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
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0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
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0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
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0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
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0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
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0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
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0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
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0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
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0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
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};
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pio3: ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
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0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
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0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
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0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
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0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
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};
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pio4: ucc_pin@04 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
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0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
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0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
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0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
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0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
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};
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};
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};
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&qe {
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enet3: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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rx-clock-name = "clk12";
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tx-clock-name = "clk9";
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pio-handle = <&pio1>;
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phy-handle = <&qe_phy0>;
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phy-connection-type = "mii";
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};
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mdio@2120 {
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qe_phy0: ethernet-phy@18 {
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interrupt-parent = <&mpic>;
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interrupts = <4 1 0 0>;
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reg = <0x18>;
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device_type = "ethernet-phy";
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};
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qe_phy1: ethernet-phy@19 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1 0 0>;
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reg = <0x19>;
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device_type = "ethernet-phy";
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};
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tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet4: ucc@2400 {
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device_type = "network";
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compatible = "ucc_geth";
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rx-clock-name = "none";
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tx-clock-name = "clk13";
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pio-handle = <&pio2>;
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phy-handle = <&qe_phy1>;
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phy-connection-type = "rmii";
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};
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serial2: ucc@2600 {
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device_type = "serial";
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compatible = "ucc_uart";
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port-number = <0>;
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rx-clock-name = "brg6";
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tx-clock-name = "brg6";
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pio-handle = <&pio3>;
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};
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serial3: ucc@2200 {
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device_type = "serial";
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compatible = "ucc_uart";
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port-number = <1>;
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rx-clock-name = "brg2";
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tx-clock-name = "brg2";
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pio-handle = <&pio4>;
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};
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};
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@ -123,6 +123,12 @@ config P1023_RDS
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help
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This option enables support for the P1023 RDS and RDB boards
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config TWR_P102x
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bool "Freescale TWR-P102x"
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select DEFAULT_UIMAGE
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help
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This option enables support for the TWR-P1025 board.
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config SOCRATES
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bool "Socrates"
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select DEFAULT_UIMAGE
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@ -18,6 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
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obj-$(CONFIG_P1022_DS) += p1022_ds.o
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obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
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obj-$(CONFIG_P1023_RDS) += p1023_rds.o
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obj-$(CONFIG_TWR_P102x) += twr_p102x.o
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obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
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obj-$(CONFIG_STX_GP3) += stx_gp3.o
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obj-$(CONFIG_TQM85xx) += tqm85xx.o
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@ -0,0 +1,147 @@
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/*
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* Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
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*
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* Author: Michael Johnston <michael.johnston@freescale.com>
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*
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* Description:
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* TWR-P102x Board Setup
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
#include <asm/qe.h>
|
||||
#include <asm/qe_ic.h>
|
||||
#include <asm/fsl_guts.h>
|
||||
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include "smp.h"
|
||||
|
||||
#include "mpc85xx.h"
|
||||
|
||||
static void __init twr_p1025_pic_init(void)
|
||||
{
|
||||
struct mpic *mpic;
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
struct device_node *np;
|
||||
#endif
|
||||
|
||||
mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
|
||||
MPIC_SINGLE_DEST_CPU,
|
||||
0, 256, " OpenPIC ");
|
||||
|
||||
BUG_ON(mpic == NULL);
|
||||
mpic_init(mpic);
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
|
||||
if (np) {
|
||||
qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
|
||||
qe_ic_cascade_high_mpic);
|
||||
of_node_put(np);
|
||||
} else
|
||||
pr_err("Could not find qe-ic node\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ************************************************************************
|
||||
*
|
||||
* Setup the architecture
|
||||
*
|
||||
*/
|
||||
static void __init twr_p1025_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
struct device_node *np;
|
||||
#endif
|
||||
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("twr_p1025_setup_arch()", 0);
|
||||
|
||||
mpc85xx_smp_init();
|
||||
|
||||
fsl_pci_assign_primary();
|
||||
|
||||
#ifdef CONFIG_QUICC_ENGINE
|
||||
mpc85xx_qe_init();
|
||||
|
||||
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
|
||||
if (machine_is(twr_p1025)) {
|
||||
struct ccsr_guts __iomem *guts;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
|
||||
if (np) {
|
||||
guts = of_iomap(np, 0);
|
||||
if (!guts)
|
||||
pr_err("twr_p1025: could not map global utilities register\n");
|
||||
else {
|
||||
/* P1025 has pins muxed for QE and other functions. To
|
||||
* enable QE UEC mode, we need to set bit QE0 for UCC1
|
||||
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
|
||||
* and QE12 for QE MII management signals in PMUXCR
|
||||
* register.
|
||||
* Set QE mux bits in PMUXCR */
|
||||
setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
|
||||
MPC85xx_PMUXCR_QE(3) |
|
||||
MPC85xx_PMUXCR_QE(9) |
|
||||
MPC85xx_PMUXCR_QE(12));
|
||||
iounmap(guts);
|
||||
|
||||
#if defined(CONFIG_SERIAL_QE)
|
||||
/* On P1025TWR board, the UCC7 acted as UART port.
|
||||
* However, The UCC7's CTS pin is low level in default,
|
||||
* it will impact the transmission in full duplex
|
||||
* communication. So disable the Flow control pin PA18.
|
||||
* The UCC7 UART just can use RXD and TXD pins.
|
||||
*/
|
||||
par_io_config_pin(0, 18, 0, 0, 0, 0);
|
||||
#endif
|
||||
/* Drive PB29 to CPLD low - CPLD will then change
|
||||
* muxing from LBC to QE */
|
||||
par_io_config_pin(1, 29, 1, 0, 0, 0);
|
||||
par_io_data_set(1, 29, 0);
|
||||
}
|
||||
of_node_put(np);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_QUICC_ENGINE */
|
||||
|
||||
pr_info("TWR-P1025 board from Freescale Semiconductor\n");
|
||||
}
|
||||
|
||||
machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
|
||||
|
||||
static int __init twr_p1025_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
return of_flat_dt_is_compatible(root, "fsl,TWR-P1025");
|
||||
}
|
||||
|
||||
define_machine(twr_p1025) {
|
||||
.name = "TWR-P1025",
|
||||
.probe = twr_p1025_probe,
|
||||
.setup_arch = twr_p1025_setup_arch,
|
||||
.init_IRQ = twr_p1025_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
.get_irq = mpic_get_irq,
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
};
|
||||
Loading…
Reference in New Issue