video: da8xx-fb rev2: fix disabling of palette completion interrupt
Writing '1' to particular bit of IRQENABLE_CLEAR register disables the corresponding interrupt on revision 2 LCDC. This register was wrongly configured to disable all previous enabled interrupts instead of disabling only palette completion interrupt. Patch fixes it by clearing only palette completion interrupt bit. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
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@ -716,7 +716,6 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
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{
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struct da8xx_fb_par *par = arg;
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u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
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u32 reg_int;
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if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
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lcd_disable_raster();
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@ -733,10 +732,8 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
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lcdc_write(stat, LCD_MASKED_STAT_REG);
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/* Disable PL completion inerrupt */
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reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
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(LCD_V2_PL_INT_ENA);
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lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
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/* Disable PL completion interrupt */
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lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
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/* Setup and start data loading mode */
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lcd_blit(LOAD_DATA, par);
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