From 8b45d639bc6d943dd9b1707cd18cb33a7acf6a28 Mon Sep 17 00:00:00 2001 From: Mirela Rabulea Date: Thu, 14 Jun 2018 17:14:48 +0300 Subject: [PATCH] MLK-18607: arm64: dts: Add dual camera support for imx8mq-evk rev B4 Update ov5640 camera nodes in fsl-imx8mq-evk.dts to match for B4 revision, the two cameras are on separate i2c buses. Create fsl-imx8mq-evk-b3.dts to be used with old B3 revision, here include the B4 dtb, but override the ov5640 camera nodes, to use different i2c addresses on the same i2c bus. Rev B4 tested with HDMI 1920x1080 and fsl-imx8mq-evk.dtb. Rev B3 tested with HDMI 1920x1080 and fsl-imx8mq-evk-b3.dtb. Signed-off-by: Mirela Rabulea Reviewed-by: Robert Chiras , Robby Cai --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-imx8mq-evk-b3.dts | 70 +++++++++++++++++++ .../boot/dts/freescale/fsl-imx8mq-evk.dts | 54 +++++++------- 3 files changed, 98 insertions(+), 27 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 79cf3b07ab12..483ace59d22e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ fsl-imx8mq-ddr4-arm2.dtb \ fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \ fsl-imx8mq-evk.dtb \ + fsl-imx8mq-evk-b3.dtb \ fsl-imx8mq-evk-m4.dtb \ fsl-imx8mq-evk-pcie1-m2.dtb \ fsl-imx8mq-evk-lcdif-adv7535.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts new file mode 100644 index 000000000000..9ad6754790e6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8mq-evk.dts" + +/delete-node/ &ov5640_mipi; +/delete-node/ &ov5640_mipi2; + +&i2c1 { + ov5640_mipi: ov5640_mipi@1c { + compatible = "ovti,ov5640_mipi"; + reg = <0x1c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; + + ov5640_mipi2: ov5640_mipi2@2c { + compatible = "ovti,ov5640_mipi"; + reg = <0x2c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi2_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <1>; + pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi2_ep: endpoint { + remote-endpoint = <&mipi2_sensor_ep>; + }; + }; + }; +}; + +&i2c2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts index a116a44701d4..904989314364 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts @@ -525,35 +525,12 @@ default-role = "sink"; }; - ov5640_mipi: ov5640_mipi@1c { + ov5640_mipi2: ov5640_mipi2@3c { compatible = "ovti,ov5640_mipi"; - reg = <0x1c>; + reg = <0x3c>; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>; - clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; - clock-names = "csi_mclk"; - assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, - <&clk IMX8MQ_CLK_CLKO2_DIV>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; - assigned-clock-rates = <0>, <20000000>; - csi_id = <0>; - pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - mclk = <20000000>; - mclk_source = <0>; - port { - ov5640_mipi1_ep: endpoint { - remote-endpoint = <&mipi1_sensor_ep>; - }; - }; - }; - - ov5640_mipi2: ov5640_mipi2@2c { - compatible = "ovti,ov5640_mipi"; - reg = <0x2c>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi2_pwn>; + pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; clock-names = "csi_mclk"; assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, @@ -576,7 +553,30 @@ clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - status = "disabled"; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1_pwn>; + clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>; + clock-names = "csi_mclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>, + <&clk IMX8MQ_CLK_CLKO2_DIV>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <0>, <20000000>; + csi_id = <0>; + pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + mclk = <20000000>; + mclk_source = <0>; + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; }; &i2c3 {