iommu bitmap instead of iommu pointer in dmar_domain
In order to support assigning multiple devices from different iommus to a domain, iommu bitmap is used to keep all iommus the domain are related to. Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
parent
a2bb8459fe
commit
8c11e798ee
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@ -208,7 +208,7 @@ static inline bool dma_pte_present(struct dma_pte *pte)
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struct dmar_domain {
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int id; /* domain id */
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struct intel_iommu *iommu; /* back pointer to owning iommu */
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unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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@ -362,6 +362,18 @@ void free_iova_mem(struct iova *iova)
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kmem_cache_free(iommu_iova_cache, iova);
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}
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/* in native case, each domain is related to only one iommu */
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static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
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{
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int iommu_id;
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iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
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if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
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return NULL;
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return g_iommus[iommu_id];
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}
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/* Gets context entry for a given bus and devfn */
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static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
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u8 bus, u8 devfn)
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@ -502,6 +514,7 @@ static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
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int level = agaw_to_level(domain->agaw);
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int offset;
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unsigned long flags;
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struct intel_iommu *iommu = domain_get_iommu(domain);
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BUG_ON(!domain->pgd);
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@ -525,7 +538,7 @@ static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
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flags);
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return NULL;
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}
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__iommu_flush_cache(domain->iommu, tmp_page,
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__iommu_flush_cache(iommu, tmp_page,
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PAGE_SIZE);
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dma_set_pte_addr(pte, virt_to_phys(tmp_page));
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/*
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@ -534,7 +547,7 @@ static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
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*/
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dma_set_pte_readable(pte);
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dma_set_pte_writable(pte);
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__iommu_flush_cache(domain->iommu, pte, sizeof(*pte));
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__iommu_flush_cache(iommu, pte, sizeof(*pte));
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}
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parent = phys_to_virt(dma_pte_addr(pte));
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level--;
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@ -571,13 +584,14 @@ static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
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static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
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{
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struct dma_pte *pte = NULL;
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struct intel_iommu *iommu = domain_get_iommu(domain);
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/* get last level pte */
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pte = dma_addr_level_pte(domain, addr, 1);
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if (pte) {
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dma_clear_pte(pte);
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__iommu_flush_cache(domain->iommu, pte, sizeof(*pte));
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__iommu_flush_cache(iommu, pte, sizeof(*pte));
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}
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}
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@ -608,6 +622,7 @@ static void dma_pte_free_pagetable(struct dmar_domain *domain,
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int total = agaw_to_level(domain->agaw);
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int level;
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u64 tmp;
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struct intel_iommu *iommu = domain_get_iommu(domain);
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start &= (((u64)1) << addr_width) - 1;
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end &= (((u64)1) << addr_width) - 1;
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@ -625,7 +640,7 @@ static void dma_pte_free_pagetable(struct dmar_domain *domain,
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free_pgtable_page(
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phys_to_virt(dma_pte_addr(pte)));
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dma_clear_pte(pte);
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__iommu_flush_cache(domain->iommu,
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__iommu_flush_cache(iommu,
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pte, sizeof(*pte));
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}
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tmp += level_size(level);
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@ -1195,7 +1210,8 @@ static struct dmar_domain * iommu_alloc_domain(struct intel_iommu *iommu)
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set_bit(num, iommu->domain_ids);
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domain->id = num;
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domain->iommu = iommu;
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memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
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set_bit(iommu->seq_id, &domain->iommu_bmp);
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domain->flags = 0;
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iommu->domains[num] = domain;
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spin_unlock_irqrestore(&iommu->lock, flags);
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@ -1206,10 +1222,13 @@ static struct dmar_domain * iommu_alloc_domain(struct intel_iommu *iommu)
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static void iommu_free_domain(struct dmar_domain *domain)
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{
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unsigned long flags;
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struct intel_iommu *iommu;
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spin_lock_irqsave(&domain->iommu->lock, flags);
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clear_bit(domain->id, domain->iommu->domain_ids);
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spin_unlock_irqrestore(&domain->iommu->lock, flags);
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iommu = domain_get_iommu(domain);
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spin_lock_irqsave(&iommu->lock, flags);
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clear_bit(domain->id, iommu->domain_ids);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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static struct iova_domain reserved_iova_list;
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@ -1288,7 +1307,7 @@ static int domain_init(struct dmar_domain *domain, int guest_width)
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domain_reserve_special_ranges(domain);
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/* calculate AGAW */
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iommu = domain->iommu;
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iommu = domain_get_iommu(domain);
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if (guest_width > cap_mgaw(iommu->cap))
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guest_width = cap_mgaw(iommu->cap);
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domain->gaw = guest_width;
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@ -1341,7 +1360,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain,
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u8 bus, u8 devfn)
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{
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struct context_entry *context;
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struct intel_iommu *iommu = domain->iommu;
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struct intel_iommu *iommu = domain_get_iommu(domain);
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unsigned long flags;
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pr_debug("Set context mapping for %02x:%02x.%d\n",
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@ -1413,8 +1432,9 @@ static int domain_context_mapped(struct dmar_domain *domain,
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{
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int ret;
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struct pci_dev *tmp, *parent;
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struct intel_iommu *iommu = domain_get_iommu(domain);
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ret = device_context_mapped(domain->iommu,
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ret = device_context_mapped(iommu,
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pdev->bus->number, pdev->devfn);
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if (!ret)
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return ret;
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@ -1425,17 +1445,17 @@ static int domain_context_mapped(struct dmar_domain *domain,
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/* Secondary interface's bus number and devfn 0 */
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parent = pdev->bus->self;
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while (parent != tmp) {
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ret = device_context_mapped(domain->iommu, parent->bus->number,
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ret = device_context_mapped(iommu, parent->bus->number,
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parent->devfn);
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if (!ret)
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return ret;
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parent = parent->bus->self;
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}
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if (tmp->is_pcie)
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return device_context_mapped(domain->iommu,
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return device_context_mapped(iommu,
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tmp->subordinate->number, 0);
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else
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return device_context_mapped(domain->iommu,
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return device_context_mapped(iommu,
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tmp->bus->number, tmp->devfn);
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}
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@ -1447,6 +1467,7 @@ domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
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struct dma_pte *pte;
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int index;
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int addr_width = agaw_to_width(domain->agaw);
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struct intel_iommu *iommu = domain_get_iommu(domain);
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hpa &= (((u64)1) << addr_width) - 1;
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BUG_ON(dma_pte_addr(pte));
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dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
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dma_set_pte_prot(pte, prot);
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__iommu_flush_cache(domain->iommu, pte, sizeof(*pte));
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__iommu_flush_cache(iommu, pte, sizeof(*pte));
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start_pfn++;
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index++;
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}
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@ -1475,10 +1496,12 @@ domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
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static void detach_domain_for_dev(struct dmar_domain *domain, u8 bus, u8 devfn)
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{
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clear_context_table(domain->iommu, bus, devfn);
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domain->iommu->flush.flush_context(domain->iommu, 0, 0, 0,
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struct intel_iommu *iommu = domain_get_iommu(domain);
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clear_context_table(iommu, bus, devfn);
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iommu->flush.flush_context(iommu, 0, 0, 0,
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DMA_CCMD_GLOBAL_INVL, 0);
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domain->iommu->flush.flush_iotlb(domain->iommu, 0, 0, 0,
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iommu->flush.flush_iotlb(iommu, 0, 0, 0,
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DMA_TLB_GLOBAL_FLUSH, 0);
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}
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struct iova *iova;
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int prot = 0;
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int ret;
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struct intel_iommu *iommu;
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BUG_ON(dir == DMA_NONE);
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if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
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if (!domain)
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return 0;
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iommu = domain_get_iommu(domain);
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size = aligned_size((u64)paddr, size);
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iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
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* mappings..
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*/
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if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
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!cap_zlr(domain->iommu->cap))
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!cap_zlr(iommu->cap))
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prot |= DMA_PTE_READ;
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if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
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prot |= DMA_PTE_WRITE;
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goto error;
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/* it's a non-present to present mapping */
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ret = iommu_flush_iotlb_psi(domain->iommu, domain->id,
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ret = iommu_flush_iotlb_psi(iommu, domain->id,
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start_paddr, size >> VTD_PAGE_SHIFT, 1);
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if (ret)
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iommu_flush_write_buffer(domain->iommu);
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iommu_flush_write_buffer(iommu);
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return start_paddr + ((u64)paddr & (~PAGE_MASK));
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@ -2132,12 +2157,14 @@ static void add_unmap(struct dmar_domain *dom, struct iova *iova)
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{
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unsigned long flags;
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int next, iommu_id;
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struct intel_iommu *iommu;
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spin_lock_irqsave(&async_umap_flush_lock, flags);
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if (list_size == HIGH_WATER_MARK)
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flush_unmaps();
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iommu_id = dom->iommu->seq_id;
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iommu = domain_get_iommu(dom);
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iommu_id = iommu->seq_id;
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next = deferred_flush[iommu_id].next;
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deferred_flush[iommu_id].domain[next] = dom;
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@ -2159,12 +2186,15 @@ void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
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struct dmar_domain *domain;
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unsigned long start_addr;
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struct iova *iova;
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struct intel_iommu *iommu;
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if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
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return;
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domain = find_domain(pdev);
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BUG_ON(!domain);
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iommu = domain_get_iommu(domain);
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iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
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if (!iova)
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return;
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@ -2180,9 +2210,9 @@ void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
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/* free page tables */
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dma_pte_free_pagetable(domain, start_addr, start_addr + size);
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if (intel_iommu_strict) {
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if (iommu_flush_iotlb_psi(domain->iommu,
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if (iommu_flush_iotlb_psi(iommu,
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domain->id, start_addr, size >> VTD_PAGE_SHIFT, 0))
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iommu_flush_write_buffer(domain->iommu);
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iommu_flush_write_buffer(iommu);
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/* free iova */
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__free_iova(&domain->iovad, iova);
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} else {
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size_t size = 0;
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void *addr;
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struct scatterlist *sg;
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struct intel_iommu *iommu;
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if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
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return;
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domain = find_domain(pdev);
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BUG_ON(!domain);
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iommu = domain_get_iommu(domain);
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iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
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if (!iova)
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/* free page tables */
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dma_pte_free_pagetable(domain, start_addr, start_addr + size);
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if (iommu_flush_iotlb_psi(domain->iommu, domain->id, start_addr,
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if (iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
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size >> VTD_PAGE_SHIFT, 0))
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iommu_flush_write_buffer(domain->iommu);
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iommu_flush_write_buffer(iommu);
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/* free iova */
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__free_iova(&domain->iovad, iova);
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int ret;
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struct scatterlist *sg;
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unsigned long start_addr;
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struct intel_iommu *iommu;
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BUG_ON(dir == DMA_NONE);
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if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
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if (!domain)
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return 0;
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iommu = domain_get_iommu(domain);
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for_each_sg(sglist, sg, nelems, i) {
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addr = SG_ENT_VIRT_ADDRESS(sg);
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addr = (void *)virt_to_phys(addr);
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@ -2326,7 +2363,7 @@ int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
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* mappings..
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*/
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if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
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!cap_zlr(domain->iommu->cap))
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!cap_zlr(iommu->cap))
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prot |= DMA_PTE_READ;
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if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
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prot |= DMA_PTE_WRITE;
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}
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/* it's a non-present to present mapping */
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if (iommu_flush_iotlb_psi(domain->iommu, domain->id,
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if (iommu_flush_iotlb_psi(iommu, domain->id,
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start_addr, offset >> VTD_PAGE_SHIFT, 1))
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iommu_flush_write_buffer(domain->iommu);
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iommu_flush_write_buffer(iommu);
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return nelems;
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}
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