Merge branch 'gpio/next-mx' into gpio/next
This commit is contained in:
commit
8c31b1635b
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
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||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
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||||
EXTRAVERSION = -rc2
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||||
NAME = Sneaky Weasel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -115,6 +115,8 @@ static struct platform_device *devices[] __initdata = {
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|||
|
||||
static void __init apf9328_init(void)
|
||||
{
|
||||
imx1_soc_init();
|
||||
|
||||
mxc_gpio_setup_multiple_pins(apf9328_pins,
|
||||
ARRAY_SIZE(apf9328_pins),
|
||||
"APF9328");
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||||
|
|
|
@ -490,6 +490,8 @@ static struct platform_device *devices[] __initdata = {
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|||
*/
|
||||
static void __init armadillo5x0_init(void)
|
||||
{
|
||||
imx31_soc_init();
|
||||
|
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mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
|
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ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
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|
|
|
@ -42,6 +42,8 @@ static const unsigned int bug_pins[] __initconst = {
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static void __init bug_board_init(void)
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||||
{
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imx31_soc_init();
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||||
|
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mxc_iomux_setup_multiple_pins(bug_pins,
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ARRAY_SIZE(bug_pins), "uart-4");
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imx31_add_imx_uart4(&uart_pdata);
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|
|
|
@ -250,6 +250,8 @@ __setup("otg_mode=", eukrea_cpuimx27_otg_mode);
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static void __init eukrea_cpuimx27_init(void)
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||||
{
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||||
imx27_soc_init();
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||||
|
||||
mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
|
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ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
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|
|
|
@ -156,6 +156,8 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
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|||
*/
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static void __init eukrea_cpuimx35_init(void)
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{
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imx35_soc_init();
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mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
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ARRAY_SIZE(eukrea_cpuimx35_pads));
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|
|
|
@ -125,6 +125,8 @@ __setup("otg_mode=", eukrea_cpuimx25_otg_mode);
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|||
|
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static void __init eukrea_cpuimx25_init(void)
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{
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imx25_soc_init();
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|
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if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
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ARRAY_SIZE(eukrea_cpuimx25_pads)))
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printk(KERN_ERR "error setting cpuimx25 pads !\n");
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|
|
|
@ -231,6 +231,8 @@ static void __init visstrim_m10_board_init(void)
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|||
{
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int ret;
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|
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imx27_soc_init();
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|
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ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
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ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
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if (ret)
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|
|
|
@ -50,6 +50,8 @@ static const int mx27ipcam_pins[] __initconst = {
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static void __init mx27ipcam_init(void)
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{
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imx27_soc_init();
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|
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mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
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||||
"mx27ipcam");
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|
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|
|
|
@ -59,6 +59,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
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|||
|
||||
static void __init mx27lite_init(void)
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||||
{
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||||
imx27_soc_init();
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|
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mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
|
||||
"imx27lite");
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imx27_add_imx_uart0(&uart_pdata);
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||||
|
|
|
@ -223,6 +223,8 @@ static int kzm_pins[] __initdata = {
|
|||
*/
|
||||
static void __init kzm_board_init(void)
|
||||
{
|
||||
imx31_soc_init();
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||||
|
||||
mxc_iomux_setup_multiple_pins(kzm_pins,
|
||||
ARRAY_SIZE(kzm_pins), "kzm");
|
||||
kzm_init_ext_uart();
|
||||
|
|
|
@ -115,6 +115,8 @@ static struct i2c_board_info mx1ads_i2c_devices[] = {
|
|||
*/
|
||||
static void __init mx1ads_init(void)
|
||||
{
|
||||
imx1_soc_init();
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||||
|
||||
mxc_gpio_setup_multiple_pins(mx1ads_pins,
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||||
ARRAY_SIZE(mx1ads_pins), "mx1ads");
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||||
|
||||
|
|
|
@ -279,6 +279,8 @@ static struct platform_device *platform_devices[] __initdata = {
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|||
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||||
static void __init mx21ads_board_init(void)
|
||||
{
|
||||
imx21_soc_init();
|
||||
|
||||
mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
|
||||
"mx21ads");
|
||||
|
||||
|
|
|
@ -219,6 +219,8 @@ static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
|
|||
|
||||
static void __init mx25pdk_init(void)
|
||||
{
|
||||
imx25_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
|
||||
ARRAY_SIZE(mx25pdk_pads));
|
||||
|
||||
|
|
|
@ -267,6 +267,8 @@ static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
|
|||
|
||||
static void __init mx27pdk_init(void)
|
||||
{
|
||||
imx27_soc_init();
|
||||
|
||||
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
|
||||
"mx27pdk");
|
||||
mx27_3ds_sdhc1_enable_level_translator();
|
||||
|
|
|
@ -288,6 +288,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
|
|||
|
||||
static void __init mx27ads_board_init(void)
|
||||
{
|
||||
imx27_soc_init();
|
||||
|
||||
mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
|
||||
"mx27ads");
|
||||
|
||||
|
|
|
@ -689,6 +689,8 @@ static void __init mx31_3ds_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
imx31_soc_init();
|
||||
|
||||
mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
|
||||
"mx31_3ds");
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||||
|
||||
|
|
|
@ -516,6 +516,8 @@ static void __init mx31ads_init_irq(void)
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|||
|
||||
static void __init mx31ads_init(void)
|
||||
{
|
||||
imx31_soc_init();
|
||||
|
||||
mxc_init_extuart();
|
||||
mxc_init_imx_uart();
|
||||
mxc_init_i2c();
|
||||
|
|
|
@ -243,6 +243,8 @@ core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
|
|||
|
||||
static void __init mx31lilly_board_init(void)
|
||||
{
|
||||
imx31_soc_init();
|
||||
|
||||
switch (mx31lilly_baseboard) {
|
||||
case MX31LILLY_NOBOARD:
|
||||
break;
|
||||
|
|
|
@ -230,6 +230,8 @@ static void __init mx31lite_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
imx31_soc_init();
|
||||
|
||||
switch (mx31lite_baseboard) {
|
||||
case MX31LITE_NOBOARD:
|
||||
break;
|
||||
|
|
|
@ -507,6 +507,8 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
|
|||
*/
|
||||
static void __init mx31moboard_init(void)
|
||||
{
|
||||
imx31_soc_init();
|
||||
|
||||
mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
|
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"moboard");
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||||
|
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|
|
|
@ -179,6 +179,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
|
|||
*/
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static void __init mx35_3ds_init(void)
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{
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imx35_soc_init();
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mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
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imx35_add_fec(NULL);
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|
|
|
@ -233,6 +233,8 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
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static void __init mxt_td60_board_init(void)
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{
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imx27_soc_init();
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mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
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"MXT_TD60");
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|
|
|
@ -357,6 +357,8 @@ static void __init pca100_init(void)
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{
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int ret;
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imx27_soc_init();
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/* SSI unit */
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mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
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MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
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|
|
|
@ -576,6 +576,8 @@ static void __init pcm037_init(void)
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{
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int ret;
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|
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imx31_soc_init();
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mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
|
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mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
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|
|
|
@ -295,6 +295,8 @@ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
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static void __init pcm038_init(void)
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{
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imx27_soc_init();
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mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
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"PCM038");
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|
|
|
@ -356,6 +356,8 @@ static struct esdhc_platform_data sd1_pdata = {
|
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*/
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static void __init pcm043_init(void)
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{
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imx35_soc_init();
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mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
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mxc_audmux_v2_configure_port(3,
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|
|
|
@ -244,6 +244,8 @@ static void __init qong_init_fpga(void)
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*/
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static void __init qong_init(void)
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{
|
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imx31_soc_init();
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|
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mxc_init_imx_uart();
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qong_init_nor_mtd();
|
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qong_init_fpga();
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|
|
|
@ -129,6 +129,8 @@ static struct platform_device *devices[] __initdata = {
|
|||
*/
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static void __init scb9328_init(void)
|
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{
|
||||
imx1_soc_init();
|
||||
|
||||
imx1_add_imx_uart0(&uart_pdata);
|
||||
|
||||
printk(KERN_INFO"Scb9328: Adding devices\n");
|
||||
|
|
|
@ -267,6 +267,8 @@ static struct platform_device *devices[] __initdata = {
|
|||
*/
|
||||
static void __init vpr200_board_init(void)
|
||||
{
|
||||
imx35_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
|
||||
|
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imx35_add_fec(NULL);
|
||||
|
|
|
@ -23,7 +23,6 @@
|
|||
|
||||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/iomux-v1.h>
|
||||
|
||||
|
@ -44,15 +43,15 @@ void __init imx1_init_early(void)
|
|||
MX1_NUM_GPIO_PORT);
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx1_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
|
||||
};
|
||||
|
||||
void __init mx1_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx1_gpio_ports, ARRAY_SIZE(imx1_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx1_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX1_GPIO1_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTA, 0);
|
||||
mxc_register_gpio(1, MX1_GPIO2_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTB, 0);
|
||||
mxc_register_gpio(2, MX1_GPIO3_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTC, 0);
|
||||
mxc_register_gpio(3, MX1_GPIO4_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTD, 0);
|
||||
}
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
#include <mach/common.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/iomux-v1.h>
|
||||
|
||||
|
@ -70,17 +69,17 @@ void __init imx21_init_early(void)
|
|||
MX21_NUM_GPIO_PORT);
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx21_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
|
||||
DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
|
||||
DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
|
||||
DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
|
||||
DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
|
||||
DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
|
||||
};
|
||||
|
||||
void __init mx21_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx21_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX21_GPIO1_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio(1, MX21_GPIO2_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio(2, MX21_GPIO3_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio(3, MX21_GPIO4_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio(4, MX21_GPIO5_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio(5, MX21_GPIO6_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
|
||||
}
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/mx25.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
|
@ -57,16 +56,15 @@ void __init imx25_init_early(void)
|
|||
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx25_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
|
||||
};
|
||||
|
||||
void __init mx25_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx25_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
|
||||
mxc_register_gpio(1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
|
||||
mxc_register_gpio(2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
|
||||
mxc_register_gpio(3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
|
||||
}
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
#include <mach/common.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/iomux-v1.h>
|
||||
|
||||
|
@ -70,17 +69,17 @@ void __init imx27_init_early(void)
|
|||
MX27_NUM_GPIO_PORT);
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx27_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
|
||||
DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
|
||||
DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
|
||||
DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
|
||||
DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
|
||||
DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
|
||||
};
|
||||
|
||||
void __init mx27_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx27_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX27_GPIO1_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio(1, MX27_GPIO2_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio(2, MX27_GPIO3_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio(3, MX27_GPIO4_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio(4, MX27_GPIO5_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio(5, MX27_GPIO6_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
|
||||
}
|
||||
|
|
|
@ -26,7 +26,6 @@
|
|||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
static struct map_desc mx31_io_desc[] __initdata = {
|
||||
|
@ -53,14 +52,14 @@ void __init imx31_init_early(void)
|
|||
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx31_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
|
||||
};
|
||||
|
||||
void __init mx31_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx31_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
|
||||
mxc_register_gpio(1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
|
||||
mxc_register_gpio(2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
|
||||
}
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <mach/common.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
static struct map_desc mx35_io_desc[] __initdata = {
|
||||
|
@ -50,14 +49,14 @@ void __init imx35_init_early(void)
|
|||
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx35_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
|
||||
};
|
||||
|
||||
void __init mx35_init_irq(void)
|
||||
{
|
||||
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx35_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
|
||||
mxc_register_gpio(1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
|
||||
mxc_register_gpio(2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
|
||||
}
|
||||
|
|
|
@ -245,6 +245,8 @@ __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
|
|||
*/
|
||||
static void __init eukrea_cpuimx51_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
|
||||
ARRAY_SIZE(eukrea_cpuimx51_pads));
|
||||
|
||||
|
|
|
@ -264,6 +264,8 @@ static struct platform_device *platform_devices[] __initdata = {
|
|||
|
||||
static void __init eukrea_cpuimx51sd_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
|
||||
ARRAY_SIZE(eukrea_cpuimx51sd_pads));
|
||||
|
||||
|
|
|
@ -192,6 +192,8 @@ static const struct imxi2c_platform_data i2c_data __initconst = {
|
|||
*/
|
||||
static void __init mx50_rdp_board_init(void)
|
||||
{
|
||||
imx50_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
|
||||
ARRAY_SIZE(mx50_rdp_pads));
|
||||
|
||||
|
|
|
@ -135,6 +135,8 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
|
|||
*/
|
||||
static void __init mx51_3ds_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
|
||||
ARRAY_SIZE(mx51_3ds_pads));
|
||||
|
||||
|
|
|
@ -340,6 +340,8 @@ static void __init mx51_babbage_init(void)
|
|||
iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
|
||||
MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
|
||||
|
||||
imx51_soc_init();
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ_IMX)
|
||||
get_cpu_op = mx51_get_cpu_op;
|
||||
#endif
|
||||
|
|
|
@ -236,6 +236,8 @@ late_initcall(mx51_efikamx_power_init);
|
|||
|
||||
static void __init mx51_efikamx_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
|
||||
ARRAY_SIZE(mx51efikamx_pads));
|
||||
efika_board_common_init();
|
||||
|
|
|
@ -248,6 +248,8 @@ static void __init mx51_efikasb_board_id(void)
|
|||
|
||||
static void __init efikasb_board_init(void)
|
||||
{
|
||||
imx51_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
|
||||
ARRAY_SIZE(mx51efikasb_pads));
|
||||
efika_board_common_init();
|
||||
|
|
|
@ -117,6 +117,8 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = {
|
|||
|
||||
static void __init mx53_evk_board_init(void)
|
||||
{
|
||||
imx53_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
|
||||
ARRAY_SIZE(mx53_evk_pads));
|
||||
mx53_evk_init_uart();
|
||||
|
|
|
@ -227,6 +227,8 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
|
|||
|
||||
static void __init mx53_loco_board_init(void)
|
||||
{
|
||||
imx53_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
|
||||
ARRAY_SIZE(mx53_loco_pads));
|
||||
imx53_add_imx_uart(0, NULL);
|
||||
|
|
|
@ -113,6 +113,8 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
|
|||
|
||||
static void __init mx53_smd_board_init(void)
|
||||
{
|
||||
imx53_soc_init();
|
||||
|
||||
mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
|
||||
ARRAY_SIZE(mx53_smd_pads));
|
||||
mx53_smd_init_uart();
|
||||
|
|
|
@ -12,7 +12,6 @@
|
|||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/imx-uart.h>
|
||||
#include <mach/irqs.h>
|
||||
|
@ -119,66 +118,3 @@ struct platform_device mxc_usbh2_device = {
|
|||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
static struct mxc_gpio_port mxc_gpio_ports[] = {
|
||||
{
|
||||
.chip.label = "gpio-0",
|
||||
.base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
|
||||
.irq = MX51_MXC_INT_GPIO1_LOW,
|
||||
.irq_high = MX51_MXC_INT_GPIO1_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START
|
||||
},
|
||||
{
|
||||
.chip.label = "gpio-1",
|
||||
.base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
|
||||
.irq = MX51_MXC_INT_GPIO2_LOW,
|
||||
.irq_high = MX51_MXC_INT_GPIO2_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
|
||||
},
|
||||
{
|
||||
.chip.label = "gpio-2",
|
||||
.base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
|
||||
.irq = MX51_MXC_INT_GPIO3_LOW,
|
||||
.irq_high = MX51_MXC_INT_GPIO3_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
|
||||
},
|
||||
{
|
||||
.chip.label = "gpio-3",
|
||||
.base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
|
||||
.irq = MX51_MXC_INT_GPIO4_LOW,
|
||||
.irq_high = MX51_MXC_INT_GPIO4_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
|
||||
},
|
||||
{
|
||||
.chip.label = "gpio-4",
|
||||
.base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR),
|
||||
.irq = MX53_INT_GPIO5_LOW,
|
||||
.irq_high = MX53_INT_GPIO5_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4
|
||||
},
|
||||
{
|
||||
.chip.label = "gpio-5",
|
||||
.base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR),
|
||||
.irq = MX53_INT_GPIO6_LOW,
|
||||
.irq_high = MX53_INT_GPIO6_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5
|
||||
},
|
||||
{
|
||||
.chip.label = "gpio-6",
|
||||
.base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR),
|
||||
.irq = MX53_INT_GPIO7_LOW,
|
||||
.irq_high = MX53_INT_GPIO7_HIGH,
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6
|
||||
},
|
||||
};
|
||||
|
||||
int __init imx51_register_gpios(void)
|
||||
{
|
||||
return mxc_gpio_init(mxc_gpio_ports, 4);
|
||||
}
|
||||
|
||||
int __init imx53_register_gpios(void)
|
||||
{
|
||||
return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
|
||||
}
|
||||
|
||||
|
|
|
@ -26,7 +26,6 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-v3.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
|
@ -56,17 +55,17 @@ void __init imx50_init_early(void)
|
|||
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
|
||||
}
|
||||
|
||||
static struct mxc_gpio_port imx50_gpio_ports[] = {
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
|
||||
};
|
||||
|
||||
void __init mx50_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
|
||||
mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
|
||||
}
|
||||
|
||||
void __init imx50_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio(1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio(2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio(3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
|
||||
mxc_register_gpio(4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
|
||||
mxc_register_gpio(5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
|
||||
}
|
||||
|
|
|
@ -69,8 +69,6 @@ void __init imx53_init_early(void)
|
|||
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
|
||||
}
|
||||
|
||||
int imx51_register_gpios(void);
|
||||
|
||||
void __init mx51_init_irq(void)
|
||||
{
|
||||
unsigned long tzic_addr;
|
||||
|
@ -86,11 +84,8 @@ void __init mx51_init_irq(void)
|
|||
panic("unable to map TZIC interrupt controller\n");
|
||||
|
||||
tzic_init_irq(tzic_virt);
|
||||
imx51_register_gpios();
|
||||
}
|
||||
|
||||
int imx53_register_gpios(void);
|
||||
|
||||
void __init mx53_init_irq(void)
|
||||
{
|
||||
unsigned long tzic_addr;
|
||||
|
@ -103,5 +98,23 @@ void __init mx53_init_irq(void)
|
|||
panic("unable to map TZIC interrupt controller\n");
|
||||
|
||||
tzic_init_irq(tzic_virt);
|
||||
imx53_register_gpios();
|
||||
}
|
||||
|
||||
void __init imx51_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio(1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio(2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio(3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
|
||||
}
|
||||
|
||||
void __init imx53_soc_init(void)
|
||||
{
|
||||
mxc_register_gpio(0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio(1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio(2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio(3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
|
||||
mxc_register_gpio(4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
|
||||
mxc_register_gpio(5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
|
||||
mxc_register_gpio(6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
|
||||
}
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
# Common support
|
||||
obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
|
||||
obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o
|
||||
|
||||
obj-$(CONFIG_MXS_OCOTP) += ocotp.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
|
|
|
@ -88,3 +88,14 @@ int __init mxs_add_amba_device(const struct amba_device *dev)
|
|||
|
||||
return amba_device_register(adev, &iomem_resource);
|
||||
}
|
||||
|
||||
struct device mxs_apbh_bus = {
|
||||
.init_name = "mxs_apbh",
|
||||
.parent = &platform_bus,
|
||||
};
|
||||
|
||||
static int __init mxs_device_init(void)
|
||||
{
|
||||
return device_register(&mxs_apbh_bus);
|
||||
}
|
||||
core_initcall(mxs_device_init);
|
||||
|
|
|
@ -6,4 +6,5 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
|
|||
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
|
||||
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
|
||||
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
|
||||
obj-y += platform-gpio-mxs.o
|
||||
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
|
||||
|
|
53
arch/arm/mach-mxs/devices/platform-gpio-mxs.c
Normal file
53
arch/arm/mach-mxs/devices/platform-gpio-mxs.c
Normal file
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <mach/mx23.h>
|
||||
#include <mach/mx28.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
struct platform_device *__init mxs_add_gpio(
|
||||
int id, resource_size_t iobase, int irq)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = iobase,
|
||||
.end = iobase + SZ_8K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = irq,
|
||||
.end = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
return platform_device_register_resndata(&mxs_apbh_bus,
|
||||
"gpio-mxs", id, res, ARRAY_SIZE(res), NULL, 0);
|
||||
}
|
||||
|
||||
static int __init mxs_add_mxs_gpio(void)
|
||||
{
|
||||
if (cpu_is_mx23()) {
|
||||
mxs_add_gpio(0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
|
||||
mxs_add_gpio(1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
|
||||
mxs_add_gpio(2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
|
||||
}
|
||||
|
||||
if (cpu_is_mx28()) {
|
||||
mxs_add_gpio(0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
|
||||
mxs_add_gpio(1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
|
||||
mxs_add_gpio(2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
|
||||
mxs_add_gpio(3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
|
||||
mxs_add_gpio(4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
postcore_initcall(mxs_add_mxs_gpio);
|
|
@ -1,34 +0,0 @@
|
|||
/*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MXS_GPIO_H__
|
||||
#define __MXS_GPIO_H__
|
||||
|
||||
struct mxs_gpio_port {
|
||||
void __iomem *base;
|
||||
int id;
|
||||
int irq;
|
||||
int irq_high;
|
||||
int virtual_irq_start;
|
||||
struct gpio_chip chip;
|
||||
};
|
||||
|
||||
int mxs_gpio_init(struct mxs_gpio_port*, int);
|
||||
|
||||
#endif /* __MXS_GPIO_H__ */
|
|
@ -11,6 +11,8 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/amba/bus.h>
|
||||
|
||||
extern struct device mxs_apbh_bus;
|
||||
|
||||
struct platform_device *mxs_add_platform_device_dmamask(
|
||||
const char *name, int id,
|
||||
const struct resource *res, unsigned int num_resources,
|
||||
|
|
|
@ -26,7 +26,6 @@
|
|||
#include <mach/iomux-mx28.h>
|
||||
|
||||
#include "devices-mx28.h"
|
||||
#include "gpio.h"
|
||||
|
||||
#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
|
||||
#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
|
||||
|
|
|
@ -41,5 +41,4 @@ void __init mx23_map_io(void)
|
|||
void __init mx23_init_irq(void)
|
||||
{
|
||||
icoll_init_irq();
|
||||
mx23_register_gpios();
|
||||
}
|
||||
|
|
|
@ -41,5 +41,4 @@ void __init mx28_map_io(void)
|
|||
void __init mx28_init_irq(void)
|
||||
{
|
||||
icoll_init_irq();
|
||||
mx28_register_gpios();
|
||||
}
|
||||
|
|
|
@ -249,6 +249,29 @@ static int slot_cn7_get_cd(struct platform_device *pdev)
|
|||
{
|
||||
return !gpio_get_value(GPIO_PORT41);
|
||||
}
|
||||
/* MERAM */
|
||||
static struct sh_mobile_meram_info meram_info = {
|
||||
.addr_mode = SH_MOBILE_MERAM_MODE1,
|
||||
};
|
||||
|
||||
static struct resource meram_resources[] = {
|
||||
[0] = {
|
||||
.name = "MERAM",
|
||||
.start = 0xe8000000,
|
||||
.end = 0xe81fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device meram_device = {
|
||||
.name = "sh_mobile_meram",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(meram_resources),
|
||||
.resource = meram_resources,
|
||||
.dev = {
|
||||
.platform_data = &meram_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* SH_MMCIF */
|
||||
static struct resource sh_mmcif_resources[] = {
|
||||
|
@ -447,13 +470,29 @@ const static struct fb_videomode ap4evb_lcdc_modes[] = {
|
|||
#endif
|
||||
},
|
||||
};
|
||||
static struct sh_mobile_meram_cfg lcd_meram_cfg = {
|
||||
.icb[0] = {
|
||||
.marker_icb = 28,
|
||||
.cache_icb = 24,
|
||||
.meram_offset = 0x0,
|
||||
.meram_size = 0x40,
|
||||
},
|
||||
.icb[1] = {
|
||||
.marker_icb = 29,
|
||||
.cache_icb = 25,
|
||||
.meram_offset = 0x40,
|
||||
.meram_size = 0x40,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mobile_lcdc_info lcdc_info = {
|
||||
.meram_dev = &meram_info,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
.bpp = 16,
|
||||
.lcd_cfg = ap4evb_lcdc_modes,
|
||||
.num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
|
||||
.meram_cfg = &lcd_meram_cfg,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -724,15 +763,31 @@ static struct platform_device fsi_device = {
|
|||
static struct platform_device fsi_ak4643_device = {
|
||||
.name = "sh_fsi2_a_ak4643",
|
||||
};
|
||||
static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
|
||||
.icb[0] = {
|
||||
.marker_icb = 30,
|
||||
.cache_icb = 26,
|
||||
.meram_offset = 0x80,
|
||||
.meram_size = 0x100,
|
||||
},
|
||||
.icb[1] = {
|
||||
.marker_icb = 31,
|
||||
.cache_icb = 27,
|
||||
.meram_offset = 0x180,
|
||||
.meram_size = 0x100,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
|
||||
.clock_source = LCDC_CLK_EXTERNAL,
|
||||
.meram_dev = &meram_info,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
.bpp = 16,
|
||||
.interface_type = RGB24,
|
||||
.clock_divider = 1,
|
||||
.flags = LCDC_FLAGS_DWPOL,
|
||||
.meram_cfg = &hdmi_meram_cfg,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -961,6 +1016,7 @@ static struct platform_device *ap4evb_devices[] __initdata = {
|
|||
&csi2_device,
|
||||
&ceu_device,
|
||||
&ap4evb_camera,
|
||||
&meram_device,
|
||||
};
|
||||
|
||||
static void __init hdmi_init_pm_clock(void)
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <linux/tca6416_keypad.h>
|
||||
|
@ -314,6 +315,30 @@ static struct platform_device smc911x_device = {
|
|||
},
|
||||
};
|
||||
|
||||
/* MERAM */
|
||||
static struct sh_mobile_meram_info mackerel_meram_info = {
|
||||
.addr_mode = SH_MOBILE_MERAM_MODE1,
|
||||
};
|
||||
|
||||
static struct resource meram_resources[] = {
|
||||
[0] = {
|
||||
.name = "MERAM",
|
||||
.start = 0xe8000000,
|
||||
.end = 0xe81fffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device meram_device = {
|
||||
.name = "sh_mobile_meram",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(meram_resources),
|
||||
.resource = meram_resources,
|
||||
.dev = {
|
||||
.platform_data = &mackerel_meram_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* LCDC */
|
||||
static struct fb_videomode mackerel_lcdc_modes[] = {
|
||||
{
|
||||
|
@ -342,7 +367,23 @@ static int mackerel_get_brightness(void *board_data)
|
|||
return gpio_get_value(GPIO_PORT31);
|
||||
}
|
||||
|
||||
static struct sh_mobile_meram_cfg lcd_meram_cfg = {
|
||||
.icb[0] = {
|
||||
.marker_icb = 28,
|
||||
.cache_icb = 24,
|
||||
.meram_offset = 0x0,
|
||||
.meram_size = 0x40,
|
||||
},
|
||||
.icb[1] = {
|
||||
.marker_icb = 29,
|
||||
.cache_icb = 25,
|
||||
.meram_offset = 0x40,
|
||||
.meram_size = 0x40,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_mobile_lcdc_info lcdc_info = {
|
||||
.meram_dev = &mackerel_meram_info,
|
||||
.clock_source = LCDC_CLK_BUS,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
|
@ -362,6 +403,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
|
|||
.name = "sh_mobile_lcdc_bl",
|
||||
.max_brightness = 1,
|
||||
},
|
||||
.meram_cfg = &lcd_meram_cfg,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -388,8 +430,23 @@ static struct platform_device lcdc_device = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
|
||||
.icb[0] = {
|
||||
.marker_icb = 30,
|
||||
.cache_icb = 26,
|
||||
.meram_offset = 0x80,
|
||||
.meram_size = 0x100,
|
||||
},
|
||||
.icb[1] = {
|
||||
.marker_icb = 31,
|
||||
.cache_icb = 27,
|
||||
.meram_offset = 0x180,
|
||||
.meram_size = 0x100,
|
||||
},
|
||||
};
|
||||
/* HDMI */
|
||||
static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
|
||||
.meram_dev = &mackerel_meram_info,
|
||||
.clock_source = LCDC_CLK_EXTERNAL,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
|
@ -397,6 +454,7 @@ static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
|
|||
.interface_type = RGB24,
|
||||
.clock_divider = 1,
|
||||
.flags = LCDC_FLAGS_DWPOL,
|
||||
.meram_cfg = &hdmi_meram_cfg,
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -856,6 +914,17 @@ static int slot_cn7_get_cd(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* SDHI0 */
|
||||
static irqreturn_t mackerel_sdhi0_gpio_cd(int irq, void *arg)
|
||||
{
|
||||
struct device *dev = arg;
|
||||
struct sh_mobile_sdhi_info *info = dev->platform_data;
|
||||
struct tmio_mmc_data *pdata = info->pdata;
|
||||
|
||||
tmio_mmc_cd_wakeup(pdata);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct sh_mobile_sdhi_info sdhi0_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
|
||||
|
@ -1150,6 +1219,7 @@ static struct platform_device *mackerel_devices[] __initdata = {
|
|||
&mackerel_camera,
|
||||
&hdmi_lcdc_device,
|
||||
&hdmi_device,
|
||||
&meram_device,
|
||||
};
|
||||
|
||||
/* Keypad Initialization */
|
||||
|
@ -1238,6 +1308,7 @@ static void __init mackerel_init(void)
|
|||
{
|
||||
u32 srcr4;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
sh7372_pinmux_init();
|
||||
|
||||
|
@ -1343,6 +1414,13 @@ static void __init mackerel_init(void)
|
|||
gpio_request(GPIO_FN_SDHID0_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0, NULL);
|
||||
|
||||
ret = request_irq(evt2irq(0x3340), mackerel_sdhi0_gpio_cd,
|
||||
IRQF_TRIGGER_FALLING, "sdhi0 cd", &sdhi0_device.dev);
|
||||
if (!ret)
|
||||
sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD;
|
||||
else
|
||||
pr_err("Cannot get IRQ #%d: %d\n", evt2irq(0x3340), ret);
|
||||
|
||||
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
|
||||
/* enable SDHI1 */
|
||||
gpio_request(GPIO_FN_SDHICMD1, NULL);
|
||||
|
|
|
@ -509,6 +509,7 @@ enum { MSTP001,
|
|||
MSTP118, MSTP117, MSTP116, MSTP113,
|
||||
MSTP106, MSTP101, MSTP100,
|
||||
MSTP223,
|
||||
MSTP218, MSTP217, MSTP216,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
|
||||
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
|
||||
|
@ -534,6 +535,9 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
|
||||
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
|
||||
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
|
||||
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
|
||||
[MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
|
||||
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
||||
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
|
@ -626,6 +630,9 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
|
||||
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
|
||||
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
|
|
|
@ -24,6 +24,8 @@
|
|||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "board-harmony.h"
|
||||
|
||||
#define PMC_CTRL 0x0
|
||||
#define PMC_CTRL_INTR_LOW (1 << 17)
|
||||
|
||||
|
@ -98,7 +100,7 @@ static struct tps6586x_platform_data tps_platform = {
|
|||
.irq_base = TEGRA_NR_IRQS,
|
||||
.num_subdevs = ARRAY_SIZE(tps_devs),
|
||||
.subdevs = tps_devs,
|
||||
.gpio_base = TEGRA_NR_GPIOS,
|
||||
.gpio_base = HARMONY_GPIO_TPS6586X(0),
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata harmony_regulators[] = {
|
||||
|
|
|
@ -17,7 +17,8 @@
|
|||
#ifndef _MACH_TEGRA_BOARD_HARMONY_H
|
||||
#define _MACH_TEGRA_BOARD_HARMONY_H
|
||||
|
||||
#define HARMONY_GPIO_WM8903(_x_) (TEGRA_NR_GPIOS + (_x_))
|
||||
#define HARMONY_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_))
|
||||
#define HARMONY_GPIO_WM8903(_x_) (HARMONY_GPIO_TPS6586X(4) + (_x_))
|
||||
|
||||
#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5
|
||||
#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#
|
||||
|
||||
# Common support
|
||||
obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o
|
||||
obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
|
||||
|
||||
# MX51 uses the TZIC interrupt controller, older platforms use AVIC
|
||||
obj-$(CONFIG_MXC_TZIC) += tzic.o
|
||||
|
|
|
@ -89,3 +89,14 @@ err:
|
|||
|
||||
return pdev;
|
||||
}
|
||||
|
||||
struct device mxc_aips_bus = {
|
||||
.init_name = "mxc_aips",
|
||||
.parent = &platform_bus,
|
||||
};
|
||||
|
||||
static int __init mxc_device_init(void)
|
||||
{
|
||||
return device_register(&mxc_aips_bus);
|
||||
}
|
||||
core_initcall(mxc_device_init);
|
||||
|
|
|
@ -2,6 +2,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
|
|||
obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
|
||||
obj-y += platform-gpio-mxc.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
|
||||
|
|
32
arch/arm/plat-mxc/devices/platform-gpio-mxc.c
Normal file
32
arch/arm/plat-mxc/devices/platform-gpio-mxc.c
Normal file
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include <mach/devices-common.h>
|
||||
|
||||
struct platform_device *__init mxc_register_gpio(int id,
|
||||
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = iobase,
|
||||
.end = iobase + iosize - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = irq,
|
||||
.end = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = irq_high,
|
||||
.end = irq_high,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
return platform_device_register_resndata(&mxc_aips_bus,
|
||||
"gpio-mxc", id, res, ARRAY_SIZE(res), NULL, 0);
|
||||
}
|
|
@ -43,6 +43,15 @@ extern void mx35_init_irq(void);
|
|||
extern void mx50_init_irq(void);
|
||||
extern void mx51_init_irq(void);
|
||||
extern void mx53_init_irq(void);
|
||||
extern void imx1_soc_init(void);
|
||||
extern void imx21_soc_init(void);
|
||||
extern void imx25_soc_init(void);
|
||||
extern void imx27_soc_init(void);
|
||||
extern void imx31_soc_init(void);
|
||||
extern void imx35_soc_init(void);
|
||||
extern void imx50_soc_init(void);
|
||||
extern void imx51_soc_init(void);
|
||||
extern void imx53_soc_init(void);
|
||||
extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
|
||||
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
|
||||
extern int mx1_clocks_init(unsigned long fref);
|
||||
|
@ -55,7 +64,8 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
|
|||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
|
||||
unsigned long ckih1, unsigned long ckih2);
|
||||
extern int mxc_register_gpios(void);
|
||||
extern struct platform_device *mxc_register_gpio(int id,
|
||||
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
|
||||
extern int mxc_register_device(struct platform_device *pdev, void *data);
|
||||
extern void mxc_set_cpu_type(unsigned int type);
|
||||
extern void mxc_arch_reset_init(void __iomem *);
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
extern struct device mxc_aips_bus;
|
||||
|
||||
struct platform_device *imx_add_platform_device_dmamask(
|
||||
const char *name, int id,
|
||||
const struct resource *res, unsigned int num_resources,
|
||||
|
|
|
@ -36,31 +36,4 @@
|
|||
#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
|
||||
#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
|
||||
|
||||
struct mxc_gpio_port {
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
int irq_high;
|
||||
int virtual_irq_start;
|
||||
struct gpio_chip chip;
|
||||
u32 both_edges;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
|
||||
{ \
|
||||
.chip.label = "gpio-" #_id, \
|
||||
.irq = _irq, \
|
||||
.irq_high = _irq_high, \
|
||||
.base = soc ## _IO_ADDRESS( \
|
||||
soc ## _GPIO ## _hwid ## _BASE_ADDR), \
|
||||
.virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
|
||||
}
|
||||
|
||||
#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
|
||||
DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
|
||||
#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
|
||||
DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
|
||||
|
||||
int mxc_gpio_init(struct mxc_gpio_port*, int);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
ENTRY(_strncpy)
|
||||
CC = R2 == 0;
|
||||
if CC JUMP 4f;
|
||||
if CC JUMP 6f;
|
||||
|
||||
P2 = R2 ; /* size */
|
||||
P0 = R0 ; /* dst*/
|
||||
|
|
|
@ -161,7 +161,7 @@ config ARCH_HAS_CPU_IDLE_WAIT
|
|||
|
||||
config NO_IOPORT
|
||||
def_bool !PCI
|
||||
depends on !SH_CAYMAN && !SH_SH4202_MICRODEV
|
||||
depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN
|
||||
|
||||
config IO_TRAPPED
|
||||
bool
|
||||
|
|
|
@ -359,37 +359,31 @@ static struct soc_camera_link camera_link = {
|
|||
.priv = &camera_info,
|
||||
};
|
||||
|
||||
static void dummy_release(struct device *dev)
|
||||
{
|
||||
}
|
||||
static struct platform_device *camera_device;
|
||||
|
||||
static struct platform_device camera_device = {
|
||||
.name = "soc_camera_platform",
|
||||
.dev = {
|
||||
.platform_data = &camera_info,
|
||||
.release = dummy_release,
|
||||
},
|
||||
};
|
||||
static void ap325rxa_camera_release(struct device *dev)
|
||||
{
|
||||
soc_camera_platform_release(&camera_device);
|
||||
}
|
||||
|
||||
static int ap325rxa_camera_add(struct soc_camera_link *icl,
|
||||
struct device *dev)
|
||||
{
|
||||
if (icl != &camera_link || camera_probe() <= 0)
|
||||
return -ENODEV;
|
||||
int ret = soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
|
||||
ap325rxa_camera_release, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
camera_info.dev = dev;
|
||||
ret = camera_probe();
|
||||
if (ret < 0)
|
||||
soc_camera_platform_del(icl, camera_device, &camera_link);
|
||||
|
||||
return platform_device_register(&camera_device);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ap325rxa_camera_del(struct soc_camera_link *icl)
|
||||
{
|
||||
if (icl != &camera_link)
|
||||
return;
|
||||
|
||||
platform_device_unregister(&camera_device);
|
||||
memset(&camera_device.dev.kobj, 0,
|
||||
sizeof(camera_device.dev.kobj));
|
||||
soc_camera_platform_del(icl, camera_device, &camera_link);
|
||||
}
|
||||
#endif /* CONFIG_I2C */
|
||||
|
||||
|
|
|
@ -885,6 +885,9 @@ static struct platform_device sh_mmcif_device = {
|
|||
},
|
||||
.num_resources = ARRAY_SIZE(sh_mmcif_resources),
|
||||
.resource = sh_mmcif_resources,
|
||||
.archdata = {
|
||||
.hwblk_id = HWBLK_MMC,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <asm/pgtable-2level.h>
|
||||
#endif
|
||||
#include <asm/page.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/addrspace.h>
|
||||
|
|
|
@ -41,7 +41,9 @@
|
|||
|
||||
#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
|
||||
#define kernel_stack_pointer(_regs) ((unsigned long)(_regs)->regs[15])
|
||||
#define GET_USP(regs) ((regs)->regs[15])
|
||||
|
||||
#define GET_FP(regs) ((regs)->regs[14])
|
||||
#define GET_USP(regs) ((regs)->regs[15])
|
||||
|
||||
extern void show_regs(struct pt_regs *);
|
||||
|
||||
|
@ -131,7 +133,7 @@ extern void ptrace_triggered(struct perf_event *bp, int nmi,
|
|||
|
||||
static inline unsigned long profile_pc(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long pc = instruction_pointer(regs);
|
||||
unsigned long pc = regs->pc;
|
||||
|
||||
if (virt_addr_uncached(pc))
|
||||
return CAC_ADDR(pc);
|
||||
|
|
|
@ -9,6 +9,7 @@
|
|||
#include <linux/pagemap.h>
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
#include <linux/swap.h>
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
|
|
@ -236,6 +236,7 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
SHDMA_SLAVE_INVALID,
|
||||
SHDMA_SLAVE_SCIF0_TX,
|
||||
SHDMA_SLAVE_SCIF0_RX,
|
||||
SHDMA_SLAVE_SCIF1_TX,
|
||||
|
|
|
@ -285,6 +285,7 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
SHDMA_SLAVE_INVALID,
|
||||
SHDMA_SLAVE_SCIF0_TX,
|
||||
SHDMA_SLAVE_SCIF0_RX,
|
||||
SHDMA_SLAVE_SCIF1_TX,
|
||||
|
|
|
@ -252,6 +252,7 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
SHDMA_SLAVE_INVALID,
|
||||
SHDMA_SLAVE_SDHI_TX,
|
||||
SHDMA_SLAVE_SDHI_RX,
|
||||
SHDMA_SLAVE_MMCIF_TX,
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/fs.h>
|
||||
#include <linux/ftrace.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/prefetch.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/system.h>
|
||||
|
|
|
@ -82,7 +82,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
|||
void *addr;
|
||||
|
||||
addr = __in_29bit_mode() ?
|
||||
(void *)P1SEGADDR((unsigned long)vaddr) : vaddr;
|
||||
(void *)CAC_ADDR((unsigned long)vaddr) : vaddr;
|
||||
|
||||
switch (direction) {
|
||||
case DMA_FROM_DEVICE: /* invalidate only */
|
||||
|
|
|
@ -21,7 +21,7 @@ static void cfq_dtor(struct io_context *ioc)
|
|||
if (!hlist_empty(&ioc->cic_list)) {
|
||||
struct cfq_io_context *cic;
|
||||
|
||||
cic = list_entry(ioc->cic_list.first, struct cfq_io_context,
|
||||
cic = hlist_entry(ioc->cic_list.first, struct cfq_io_context,
|
||||
cic_list);
|
||||
cic->dtor(ioc);
|
||||
}
|
||||
|
@ -57,7 +57,7 @@ static void cfq_exit(struct io_context *ioc)
|
|||
if (!hlist_empty(&ioc->cic_list)) {
|
||||
struct cfq_io_context *cic;
|
||||
|
||||
cic = list_entry(ioc->cic_list.first, struct cfq_io_context,
|
||||
cic = hlist_entry(ioc->cic_list.first, struct cfq_io_context,
|
||||
cic_list);
|
||||
cic->exit(ioc);
|
||||
}
|
||||
|
|
|
@ -185,7 +185,7 @@ struct cfq_group {
|
|||
int nr_cfqq;
|
||||
|
||||
/*
|
||||
* Per group busy queus average. Useful for workload slice calc. We
|
||||
* Per group busy queues average. Useful for workload slice calc. We
|
||||
* create the array for each prio class but at run time it is used
|
||||
* only for RT and BE class and slot for IDLE class remains unused.
|
||||
* This is primarily done to avoid confusion and a gcc warning.
|
||||
|
@ -369,16 +369,16 @@ CFQ_CFQQ_FNS(wait_busy);
|
|||
#define cfq_log_cfqq(cfqd, cfqq, fmt, args...) \
|
||||
blk_add_trace_msg((cfqd)->queue, "cfq%d%c %s " fmt, (cfqq)->pid, \
|
||||
cfq_cfqq_sync((cfqq)) ? 'S' : 'A', \
|
||||
blkg_path(&(cfqq)->cfqg->blkg), ##args);
|
||||
blkg_path(&(cfqq)->cfqg->blkg), ##args)
|
||||
|
||||
#define cfq_log_cfqg(cfqd, cfqg, fmt, args...) \
|
||||
blk_add_trace_msg((cfqd)->queue, "%s " fmt, \
|
||||
blkg_path(&(cfqg)->blkg), ##args); \
|
||||
blkg_path(&(cfqg)->blkg), ##args) \
|
||||
|
||||
#else
|
||||
#define cfq_log_cfqq(cfqd, cfqq, fmt, args...) \
|
||||
blk_add_trace_msg((cfqd)->queue, "cfq%d " fmt, (cfqq)->pid, ##args)
|
||||
#define cfq_log_cfqg(cfqd, cfqg, fmt, args...) do {} while (0);
|
||||
#define cfq_log_cfqg(cfqd, cfqg, fmt, args...) do {} while (0)
|
||||
#endif
|
||||
#define cfq_log(cfqd, fmt, args...) \
|
||||
blk_add_trace_msg((cfqd)->queue, "cfq " fmt, ##args)
|
||||
|
@ -3786,9 +3786,6 @@ new_queue:
|
|||
return 0;
|
||||
|
||||
queue_fail:
|
||||
if (cic)
|
||||
put_io_context(cic->ioc);
|
||||
|
||||
cfq_schedule_dispatch(cfqd);
|
||||
spin_unlock_irqrestore(q->queue_lock, flags);
|
||||
cfq_log(cfqd, "set_request fail");
|
||||
|
|
|
@ -192,7 +192,8 @@ static int sock_xmit(struct nbd_device *lo, int send, void *buf, int size,
|
|||
if (lo->xmit_timeout)
|
||||
del_timer_sync(&ti);
|
||||
} else
|
||||
result = kernel_recvmsg(sock, &msg, &iov, 1, size, 0);
|
||||
result = kernel_recvmsg(sock, &msg, &iov, 1, size,
|
||||
msg.msg_flags);
|
||||
|
||||
if (signal_pending(current)) {
|
||||
siginfo_t info;
|
||||
|
@ -753,9 +754,26 @@ static int __init nbd_init(void)
|
|||
return -ENOMEM;
|
||||
|
||||
part_shift = 0;
|
||||
if (max_part > 0)
|
||||
if (max_part > 0) {
|
||||
part_shift = fls(max_part);
|
||||
|
||||
/*
|
||||
* Adjust max_part according to part_shift as it is exported
|
||||
* to user space so that user can know the max number of
|
||||
* partition kernel should be able to manage.
|
||||
*
|
||||
* Note that -1 is required because partition 0 is reserved
|
||||
* for the whole disk.
|
||||
*/
|
||||
max_part = (1UL << part_shift) - 1;
|
||||
}
|
||||
|
||||
if ((1UL << part_shift) > DISK_MAX_PARTS)
|
||||
return -EINVAL;
|
||||
|
||||
if (nbds_max > 1UL << (MINORBITS - part_shift))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < nbds_max; i++) {
|
||||
struct gendisk *disk = alloc_disk(1 << part_shift);
|
||||
if (!disk)
|
||||
|
|
|
@ -809,11 +809,13 @@ static int __init xen_blkif_init(void)
|
|||
failed_init:
|
||||
kfree(blkbk->pending_reqs);
|
||||
kfree(blkbk->pending_grant_handles);
|
||||
for (i = 0; i < mmap_pages; i++) {
|
||||
if (blkbk->pending_pages[i])
|
||||
__free_page(blkbk->pending_pages[i]);
|
||||
if (blkbk->pending_pages) {
|
||||
for (i = 0; i < mmap_pages; i++) {
|
||||
if (blkbk->pending_pages[i])
|
||||
__free_page(blkbk->pending_pages[i]);
|
||||
}
|
||||
kfree(blkbk->pending_pages);
|
||||
}
|
||||
kfree(blkbk->pending_pages);
|
||||
kfree(blkbk);
|
||||
blkbk = NULL;
|
||||
return rc;
|
||||
|
|
|
@ -357,14 +357,13 @@ static int xen_vbd_create(struct xen_blkif *blkif, blkif_vdev_t handle,
|
|||
}
|
||||
|
||||
vbd->bdev = bdev;
|
||||
vbd->size = vbd_sz(vbd);
|
||||
|
||||
if (vbd->bdev->bd_disk == NULL) {
|
||||
DPRINTK("xen_vbd_create: device %08x doesn't exist.\n",
|
||||
vbd->pdevice);
|
||||
xen_vbd_free(vbd);
|
||||
return -ENOENT;
|
||||
}
|
||||
vbd->size = vbd_sz(vbd);
|
||||
|
||||
if (vbd->bdev->bd_disk->flags & GENHD_FL_CD || cdrom)
|
||||
vbd->type |= VDISK_CDROM;
|
||||
|
|
|
@ -355,29 +355,24 @@ static void hci_uart_tty_wakeup(struct tty_struct *tty)
|
|||
* flags pointer to flags for data
|
||||
* count count of received data in bytes
|
||||
*
|
||||
* Return Value: Number of bytes received
|
||||
* Return Value: None
|
||||
*/
|
||||
static unsigned int hci_uart_tty_receive(struct tty_struct *tty,
|
||||
const u8 *data, char *flags, int count)
|
||||
static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *flags, int count)
|
||||
{
|
||||
struct hci_uart *hu = (void *)tty->disc_data;
|
||||
int received;
|
||||
|
||||
if (!hu || tty != hu->tty)
|
||||
return -ENODEV;
|
||||
return;
|
||||
|
||||
if (!test_bit(HCI_UART_PROTO_SET, &hu->flags))
|
||||
return -EINVAL;
|
||||
return;
|
||||
|
||||
spin_lock(&hu->rx_lock);
|
||||
received = hu->proto->recv(hu, (void *) data, count);
|
||||
if (received > 0)
|
||||
hu->hdev->stat.byte_rx += received;
|
||||
hu->proto->recv(hu, (void *) data, count);
|
||||
hu->hdev->stat.byte_rx += count;
|
||||
spin_unlock(&hu->rx_lock);
|
||||
|
||||
tty_unthrottle(tty);
|
||||
|
||||
return received;
|
||||
}
|
||||
|
||||
static int hci_uart_register_dev(struct hci_uart *hu)
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
@ -153,12 +152,10 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
|
|||
{
|
||||
int ret;
|
||||
|
||||
/* wake up device and enable clock */
|
||||
pm_runtime_get_sync(&p->pdev->dev);
|
||||
/* enable clock */
|
||||
ret = clk_enable(p->clk);
|
||||
if (ret) {
|
||||
dev_err(&p->pdev->dev, "cannot enable clock\n");
|
||||
pm_runtime_put_sync(&p->pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -190,9 +187,8 @@ static void sh_cmt_disable(struct sh_cmt_priv *p)
|
|||
/* disable interrupts in CMT block */
|
||||
sh_cmt_write(p, CMCSR, 0);
|
||||
|
||||
/* stop clock and mark device as idle */
|
||||
/* stop clock */
|
||||
clk_disable(p->clk);
|
||||
pm_runtime_put_sync(&p->pdev->dev);
|
||||
}
|
||||
|
||||
/* private flags */
|
||||
|
@ -664,7 +660,6 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
|
|||
|
||||
if (p) {
|
||||
dev_info(&pdev->dev, "kept as earlytimer\n");
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -679,9 +674,6 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
|
|||
kfree(p);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
}
|
||||
|
||||
if (!is_early_platform_device(pdev))
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -25,7 +25,6 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
@ -110,12 +109,10 @@ static int sh_tmu_enable(struct sh_tmu_priv *p)
|
|||
{
|
||||
int ret;
|
||||
|
||||
/* wake up device and enable clock */
|
||||
pm_runtime_get_sync(&p->pdev->dev);
|
||||
/* enable clock */
|
||||
ret = clk_enable(p->clk);
|
||||
if (ret) {
|
||||
dev_err(&p->pdev->dev, "cannot enable clock\n");
|
||||
pm_runtime_put_sync(&p->pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -144,9 +141,8 @@ static void sh_tmu_disable(struct sh_tmu_priv *p)
|
|||
/* disable interrupts in TMU block */
|
||||
sh_tmu_write(p, TCR, 0x0000);
|
||||
|
||||
/* stop clock and mark device as idle */
|
||||
/* stop clock */
|
||||
clk_disable(p->clk);
|
||||
pm_runtime_put_sync(&p->pdev->dev);
|
||||
}
|
||||
|
||||
static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
|
||||
|
@ -415,7 +411,6 @@ static int __devinit sh_tmu_probe(struct platform_device *pdev)
|
|||
|
||||
if (p) {
|
||||
dev_info(&pdev->dev, "kept as earlytimer\n");
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -430,9 +425,6 @@ static int __devinit sh_tmu_probe(struct platform_device *pdev)
|
|||
kfree(p);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
}
|
||||
|
||||
if (!is_early_platform_device(pdev))
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -343,7 +343,7 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
|
|||
|
||||
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
||||
dmae_set_chcr(sh_chan, cfg->chcr);
|
||||
} else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
|
||||
} else {
|
||||
dmae_init(sh_chan);
|
||||
}
|
||||
|
||||
|
@ -1144,6 +1144,8 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
|
|||
/* platform data */
|
||||
shdev->pdata = pdata;
|
||||
|
||||
platform_set_drvdata(pdev, shdev);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
|
@ -1256,7 +1258,6 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
|
|||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, shdev);
|
||||
dma_async_device_register(&shdev->common);
|
||||
|
||||
return err;
|
||||
|
@ -1278,6 +1279,8 @@ rst_err:
|
|||
|
||||
if (dmars)
|
||||
iounmap(shdev->dmars);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
emapdmars:
|
||||
iounmap(shdev->chan_reg);
|
||||
synchronize_rcu();
|
||||
|
@ -1316,6 +1319,8 @@ static int __exit sh_dmae_remove(struct platform_device *pdev)
|
|||
iounmap(shdev->dmars);
|
||||
iounmap(shdev->chan_reg);
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
synchronize_rcu();
|
||||
kfree(shdev);
|
||||
|
||||
|
|
|
@ -94,6 +94,15 @@ config GPIO_EXYNOS4
|
|||
def_bool y
|
||||
depends on CPU_EXYNOS4210
|
||||
|
||||
config GPIO_MXS
|
||||
def_bool y
|
||||
depends on ARCH_MXS
|
||||
|
||||
config GPIO_MXC
|
||||
def_bool y
|
||||
depends on ARCH_MXC
|
||||
select GPIO_BASIC_MMIO_CORE
|
||||
|
||||
config GPIO_PLAT_SAMSUNG
|
||||
def_bool y
|
||||
depends on SAMSUNG_GPIOLIB_4BIT
|
||||
|
|
|
@ -10,6 +10,8 @@ obj-$(CONFIG_GPIO_BASIC_MMIO_CORE) += basic_mmio_gpio.o
|
|||
obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o
|
||||
obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
|
||||
obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o
|
||||
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
|
||||
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
|
||||
obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
|
||||
obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o
|
||||
obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o
|
||||
|
|
|
@ -24,11 +24,28 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/basic_mmio_gpio.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm-generic/bug.h>
|
||||
|
||||
static struct mxc_gpio_port *mxc_gpio_ports;
|
||||
static int gpio_table_size;
|
||||
struct mxc_gpio_port {
|
||||
struct list_head node;
|
||||
void __iomem *base;
|
||||
int irq;
|
||||
int irq_high;
|
||||
int virtual_irq_start;
|
||||
struct bgpio_chip bgc;
|
||||
u32 both_edges;
|
||||
};
|
||||
|
||||
/*
|
||||
* MX2 has one interrupt *for all* gpio ports. The list is used
|
||||
* to save the references to all ports, so that mx2_gpio_irq_handler
|
||||
* can walk through all interrupt status registers.
|
||||
*/
|
||||
static LIST_HEAD(mxc_gpio_ports);
|
||||
|
||||
#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
|
||||
|
||||
|
@ -50,7 +67,7 @@ static int gpio_table_size;
|
|||
|
||||
static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
|
||||
{
|
||||
__raw_writel(1 << index, port->base + GPIO_ISR);
|
||||
writel(1 << index, port->base + GPIO_ISR);
|
||||
}
|
||||
|
||||
static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
|
||||
|
@ -58,35 +75,36 @@ static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
|
|||
{
|
||||
u32 l;
|
||||
|
||||
l = __raw_readl(port->base + GPIO_IMR);
|
||||
l = readl(port->base + GPIO_IMR);
|
||||
l = (l & (~(1 << index))) | (!!enable << index);
|
||||
__raw_writel(l, port->base + GPIO_IMR);
|
||||
writel(l, port->base + GPIO_IMR);
|
||||
}
|
||||
|
||||
static void gpio_ack_irq(struct irq_data *d)
|
||||
{
|
||||
struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
_clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
|
||||
_clear_gpio_irqstatus(port, gpio & 0x1f);
|
||||
}
|
||||
|
||||
static void gpio_mask_irq(struct irq_data *d)
|
||||
{
|
||||
struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
|
||||
_set_gpio_irqenable(port, gpio & 0x1f, 0);
|
||||
}
|
||||
|
||||
static void gpio_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
|
||||
_set_gpio_irqenable(port, gpio & 0x1f, 1);
|
||||
}
|
||||
|
||||
static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
|
||||
|
||||
static int gpio_set_irq_type(struct irq_data *d, u32 type)
|
||||
{
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
|
||||
struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 bit, val;
|
||||
int edge;
|
||||
void __iomem *reg = port->base;
|
||||
|
@ -100,7 +118,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
|
|||
edge = GPIO_INT_FALL_EDGE;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
val = mxc_gpio_get(&port->chip, gpio & 31);
|
||||
val = gpio_get_value(gpio & 31);
|
||||
if (val) {
|
||||
edge = GPIO_INT_LOW_LEV;
|
||||
pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
|
||||
|
@ -122,8 +140,8 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type)
|
|||
|
||||
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
|
||||
bit = gpio & 0xf;
|
||||
val = __raw_readl(reg) & ~(0x3 << (bit << 1));
|
||||
__raw_writel(val | (edge << (bit << 1)), reg);
|
||||
val = readl(reg) & ~(0x3 << (bit << 1));
|
||||
writel(val | (edge << (bit << 1)), reg);
|
||||
_clear_gpio_irqstatus(port, gpio & 0x1f);
|
||||
|
||||
return 0;
|
||||
|
@ -137,7 +155,7 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
|
|||
|
||||
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
|
||||
bit = gpio & 0xf;
|
||||
val = __raw_readl(reg);
|
||||
val = readl(reg);
|
||||
edge = (val >> (bit << 1)) & 3;
|
||||
val &= ~(0x3 << (bit << 1));
|
||||
if (edge == GPIO_INT_HIGH_LEV) {
|
||||
|
@ -151,7 +169,7 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
|
|||
gpio, edge);
|
||||
return;
|
||||
}
|
||||
__raw_writel(val | (edge << (bit << 1)), reg);
|
||||
writel(val | (edge << (bit << 1)), reg);
|
||||
}
|
||||
|
||||
/* handle 32 interrupts in one status register */
|
||||
|
@ -177,8 +195,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
|
|||
u32 irq_stat;
|
||||
struct mxc_gpio_port *port = irq_get_handler_data(irq);
|
||||
|
||||
irq_stat = __raw_readl(port->base + GPIO_ISR) &
|
||||
__raw_readl(port->base + GPIO_IMR);
|
||||
irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
|
||||
|
||||
mxc_gpio_irq_handler(port, irq_stat);
|
||||
}
|
||||
|
@ -186,19 +203,18 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
|
|||
/* MX2 has one interrupt *for all* gpio ports */
|
||||
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
|
||||
{
|
||||
int i;
|
||||
u32 irq_msk, irq_stat;
|
||||
struct mxc_gpio_port *port = irq_get_handler_data(irq);
|
||||
struct mxc_gpio_port *port;
|
||||
|
||||
/* walk through all interrupt status registers */
|
||||
for (i = 0; i < gpio_table_size; i++) {
|
||||
irq_msk = __raw_readl(port[i].base + GPIO_IMR);
|
||||
list_for_each_entry(port, &mxc_gpio_ports, node) {
|
||||
irq_msk = readl(port->base + GPIO_IMR);
|
||||
if (!irq_msk)
|
||||
continue;
|
||||
|
||||
irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
|
||||
irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
|
||||
if (irq_stat)
|
||||
mxc_gpio_irq_handler(&port[i], irq_stat);
|
||||
mxc_gpio_irq_handler(port, irq_stat);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -215,7 +231,7 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
|
|||
{
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
u32 gpio_idx = gpio & 0x1F;
|
||||
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
|
||||
struct mxc_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
|
||||
if (enable) {
|
||||
if (port->irq_high && (gpio_idx >= 16))
|
||||
|
@ -241,121 +257,123 @@ static struct irq_chip gpio_irq_chip = {
|
|||
.irq_set_wake = gpio_set_wake_irq,
|
||||
};
|
||||
|
||||
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
|
||||
int dir)
|
||||
{
|
||||
struct mxc_gpio_port *port =
|
||||
container_of(chip, struct mxc_gpio_port, chip);
|
||||
u32 l;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
l = __raw_readl(port->base + GPIO_GDIR);
|
||||
if (dir)
|
||||
l |= 1 << offset;
|
||||
else
|
||||
l &= ~(1 << offset);
|
||||
__raw_writel(l, port->base + GPIO_GDIR);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
struct mxc_gpio_port *port =
|
||||
container_of(chip, struct mxc_gpio_port, chip);
|
||||
void __iomem *reg = port->base + GPIO_DR;
|
||||
u32 l;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
|
||||
__raw_writel(l, reg);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
}
|
||||
|
||||
static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct mxc_gpio_port *port =
|
||||
container_of(chip, struct mxc_gpio_port, chip);
|
||||
|
||||
return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
|
||||
}
|
||||
|
||||
static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
_set_gpio_direction(chip, offset, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxc_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int value)
|
||||
{
|
||||
mxc_gpio_set(chip, offset, value);
|
||||
_set_gpio_direction(chip, offset, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This lock class tells lockdep that GPIO irqs are in a different
|
||||
* category than their parents, so it won't report false recursion.
|
||||
*/
|
||||
static struct lock_class_key gpio_lock_class;
|
||||
|
||||
int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
|
||||
static int __devinit mxc_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
int i, j;
|
||||
struct mxc_gpio_port *port;
|
||||
struct resource *iores;
|
||||
int err, i;
|
||||
|
||||
/* save for local usage */
|
||||
mxc_gpio_ports = port;
|
||||
gpio_table_size = cnt;
|
||||
port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
printk(KERN_INFO "MXC GPIO hardware\n");
|
||||
port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32;
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
/* disable the interrupt and clear the status */
|
||||
__raw_writel(0, port[i].base + GPIO_IMR);
|
||||
__raw_writel(~0, port[i].base + GPIO_ISR);
|
||||
for (j = port[i].virtual_irq_start;
|
||||
j < port[i].virtual_irq_start + 32; j++) {
|
||||
irq_set_lockdep_class(j, &gpio_lock_class);
|
||||
irq_set_chip_and_handler(j, &gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(j, IRQF_VALID);
|
||||
}
|
||||
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!iores) {
|
||||
err = -ENODEV;
|
||||
goto out_kfree;
|
||||
}
|
||||
|
||||
/* register gpio chip */
|
||||
port[i].chip.direction_input = mxc_gpio_direction_input;
|
||||
port[i].chip.direction_output = mxc_gpio_direction_output;
|
||||
port[i].chip.get = mxc_gpio_get;
|
||||
port[i].chip.set = mxc_gpio_set;
|
||||
port[i].chip.base = i * 32;
|
||||
port[i].chip.ngpio = 32;
|
||||
if (!request_mem_region(iores->start, resource_size(iores),
|
||||
pdev->name)) {
|
||||
err = -EBUSY;
|
||||
goto out_kfree;
|
||||
}
|
||||
|
||||
spin_lock_init(&port[i].lock);
|
||||
port->base = ioremap(iores->start, resource_size(iores));
|
||||
if (!port->base) {
|
||||
err = -ENOMEM;
|
||||
goto out_release_mem;
|
||||
}
|
||||
|
||||
/* its a serious configuration bug when it fails */
|
||||
BUG_ON( gpiochip_add(&port[i].chip) < 0 );
|
||||
port->irq_high = platform_get_irq(pdev, 1);
|
||||
port->irq = platform_get_irq(pdev, 0);
|
||||
if (port->irq < 0) {
|
||||
err = -EINVAL;
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
|
||||
/* setup one handler for each entry */
|
||||
irq_set_chained_handler(port[i].irq,
|
||||
mx3_gpio_irq_handler);
|
||||
irq_set_handler_data(port[i].irq, &port[i]);
|
||||
if (port[i].irq_high) {
|
||||
/* setup handler for GPIO 16 to 31 */
|
||||
irq_set_chained_handler(port[i].irq_high,
|
||||
mx3_gpio_irq_handler);
|
||||
irq_set_handler_data(port[i].irq_high,
|
||||
&port[i]);
|
||||
}
|
||||
}
|
||||
/* disable the interrupt and clear the status */
|
||||
writel(0, port->base + GPIO_IMR);
|
||||
writel(~0, port->base + GPIO_ISR);
|
||||
|
||||
for (i = port->virtual_irq_start;
|
||||
i < port->virtual_irq_start + 32; i++) {
|
||||
irq_set_lockdep_class(i, &gpio_lock_class);
|
||||
irq_set_chip_and_handler(i, &gpio_irq_chip, handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
irq_set_chip_data(i, port);
|
||||
}
|
||||
|
||||
if (cpu_is_mx2()) {
|
||||
/* setup one handler for all GPIO interrupts */
|
||||
irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
|
||||
irq_set_handler_data(port[0].irq, port);
|
||||
if (pdev->id == 0)
|
||||
irq_set_chained_handler(port->irq,
|
||||
mx2_gpio_irq_handler);
|
||||
} else {
|
||||
/* setup one handler for each entry */
|
||||
irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
|
||||
irq_set_handler_data(port->irq, port);
|
||||
if (port->irq_high > 0) {
|
||||
/* setup handler for GPIO 16 to 31 */
|
||||
irq_set_chained_handler(port->irq_high,
|
||||
mx3_gpio_irq_handler);
|
||||
irq_set_handler_data(port->irq_high, port);
|
||||
}
|
||||
}
|
||||
|
||||
err = bgpio_init(&port->bgc, &pdev->dev, 4,
|
||||
port->base + GPIO_PSR,
|
||||
port->base + GPIO_DR, NULL,
|
||||
port->base + GPIO_GDIR, NULL, false);
|
||||
if (err)
|
||||
goto out_iounmap;
|
||||
|
||||
port->bgc.gc.base = pdev->id * 32;
|
||||
|
||||
err = gpiochip_add(&port->bgc.gc);
|
||||
if (err)
|
||||
goto out_bgpio_remove;
|
||||
|
||||
list_add_tail(&port->node, &mxc_gpio_ports);
|
||||
|
||||
return 0;
|
||||
|
||||
out_bgpio_remove:
|
||||
bgpio_remove(&port->bgc);
|
||||
out_iounmap:
|
||||
iounmap(port->base);
|
||||
out_release_mem:
|
||||
release_mem_region(iores->start, resource_size(iores));
|
||||
out_kfree:
|
||||
kfree(port);
|
||||
dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct platform_driver mxc_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "gpio-mxc",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = mxc_gpio_probe,
|
||||
};
|
||||
|
||||
static int __init gpio_mxc_init(void)
|
||||
{
|
||||
return platform_driver_register(&mxc_gpio_driver);
|
||||
}
|
||||
postcore_initcall(gpio_mxc_init);
|
||||
|
||||
MODULE_AUTHOR("Freescale Semiconductor, "
|
||||
"Daniel Mack <danielncaiaq.de>, "
|
||||
"Juergen Beisert <kernel@pengutronix.de>");
|
||||
MODULE_DESCRIPTION("Freescale MXC GPIO");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -25,14 +25,12 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <mach/mx23.h>
|
||||
#include <mach/mx28.h>
|
||||
#include <asm-generic/bug.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <mach/mxs.h>
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
static struct mxs_gpio_port *mxs_gpio_ports;
|
||||
static int gpio_table_size;
|
||||
#define MXS_SET 0x4
|
||||
#define MXS_CLR 0x8
|
||||
|
||||
#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
|
||||
#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
|
||||
|
@ -50,40 +48,55 @@ static int gpio_table_size;
|
|||
#define GPIO_INT_LEV_MASK (1 << 0)
|
||||
#define GPIO_INT_POL_MASK (1 << 1)
|
||||
|
||||
struct mxs_gpio_port {
|
||||
void __iomem *base;
|
||||
int id;
|
||||
int irq;
|
||||
int irq_high;
|
||||
int virtual_irq_start;
|
||||
struct gpio_chip chip;
|
||||
};
|
||||
|
||||
/* Note: This driver assumes 32 GPIOs are handled in one register */
|
||||
|
||||
static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
|
||||
{
|
||||
__mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
|
||||
writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
|
||||
}
|
||||
|
||||
static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
|
||||
int enable)
|
||||
{
|
||||
if (enable) {
|
||||
__mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
|
||||
__mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
|
||||
writel(1 << index,
|
||||
port->base + PINCTRL_IRQEN(port->id) + MXS_SET);
|
||||
writel(1 << index,
|
||||
port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET);
|
||||
} else {
|
||||
__mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
|
||||
writel(1 << index,
|
||||
port->base + PINCTRL_IRQEN(port->id) + MXS_CLR);
|
||||
}
|
||||
}
|
||||
|
||||
static void mxs_gpio_ack_irq(struct irq_data *d)
|
||||
{
|
||||
struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
|
||||
clear_gpio_irqstatus(port, gpio & 0x1f);
|
||||
}
|
||||
|
||||
static void mxs_gpio_mask_irq(struct irq_data *d)
|
||||
{
|
||||
struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
|
||||
set_gpio_irqenable(port, gpio & 0x1f, 0);
|
||||
}
|
||||
|
||||
static void mxs_gpio_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
|
||||
set_gpio_irqenable(port, gpio & 0x1f, 1);
|
||||
}
|
||||
|
||||
static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
|
||||
|
@ -92,7 +105,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
|
|||
{
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
u32 pin_mask = 1 << (gpio & 31);
|
||||
struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
|
||||
struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
void __iomem *pin_addr;
|
||||
int edge;
|
||||
|
||||
|
@ -116,16 +129,16 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
|
|||
/* set level or edge */
|
||||
pin_addr = port->base + PINCTRL_IRQLEV(port->id);
|
||||
if (edge & GPIO_INT_LEV_MASK)
|
||||
__mxs_setl(pin_mask, pin_addr);
|
||||
writel(pin_mask, pin_addr + MXS_SET);
|
||||
else
|
||||
__mxs_clrl(pin_mask, pin_addr);
|
||||
writel(pin_mask, pin_addr + MXS_CLR);
|
||||
|
||||
/* set polarity */
|
||||
pin_addr = port->base + PINCTRL_IRQPOL(port->id);
|
||||
if (edge & GPIO_INT_POL_MASK)
|
||||
__mxs_setl(pin_mask, pin_addr);
|
||||
writel(pin_mask, pin_addr + MXS_SET);
|
||||
else
|
||||
__mxs_clrl(pin_mask, pin_addr);
|
||||
writel(pin_mask, pin_addr + MXS_CLR);
|
||||
|
||||
clear_gpio_irqstatus(port, gpio & 0x1f);
|
||||
|
||||
|
@ -136,13 +149,13 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
|
|||
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 irq_stat;
|
||||
struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
|
||||
struct mxs_gpio_port *port = irq_get_handler_data(irq);
|
||||
u32 gpio_irq_no_base = port->virtual_irq_start;
|
||||
|
||||
desc->irq_data.chip->irq_ack(&desc->irq_data);
|
||||
|
||||
irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
|
||||
__raw_readl(port->base + PINCTRL_IRQEN(port->id));
|
||||
irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
|
||||
readl(port->base + PINCTRL_IRQEN(port->id));
|
||||
|
||||
while (irq_stat != 0) {
|
||||
int irqoffset = fls(irq_stat) - 1;
|
||||
|
@ -164,7 +177,7 @@ static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
|
|||
{
|
||||
u32 gpio = irq_to_gpio(d->irq);
|
||||
u32 gpio_idx = gpio & 0x1f;
|
||||
struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
|
||||
struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
|
||||
|
||||
if (enable) {
|
||||
if (port->irq_high && (gpio_idx >= 16))
|
||||
|
@ -198,9 +211,9 @@ static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
|
|||
void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
|
||||
|
||||
if (dir)
|
||||
__mxs_setl(1 << offset, pin_addr);
|
||||
writel(1 << offset, pin_addr + MXS_SET);
|
||||
else
|
||||
__mxs_clrl(1 << offset, pin_addr);
|
||||
writel(1 << offset, pin_addr + MXS_CLR);
|
||||
}
|
||||
|
||||
static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
|
@ -208,7 +221,7 @@ static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|||
struct mxs_gpio_port *port =
|
||||
container_of(chip, struct mxs_gpio_port, chip);
|
||||
|
||||
return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
|
||||
return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
|
||||
}
|
||||
|
||||
static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
|
@ -218,9 +231,9 @@ static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|||
void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
|
||||
|
||||
if (value)
|
||||
__mxs_setl(1 << offset, pin_addr);
|
||||
writel(1 << offset, pin_addr + MXS_SET);
|
||||
else
|
||||
__mxs_clrl(1 << offset, pin_addr);
|
||||
writel(1 << offset, pin_addr + MXS_CLR);
|
||||
}
|
||||
|
||||
static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
|
@ -245,87 +258,113 @@ static int mxs_gpio_direction_output(struct gpio_chip *chip,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
|
||||
static int __devinit mxs_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
int i, j;
|
||||
static void __iomem *base;
|
||||
struct mxs_gpio_port *port;
|
||||
struct resource *iores = NULL;
|
||||
int err, i;
|
||||
|
||||
/* save for local usage */
|
||||
mxs_gpio_ports = port;
|
||||
gpio_table_size = cnt;
|
||||
port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
pr_info("MXS GPIO hardware\n");
|
||||
port->id = pdev->id;
|
||||
port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
/* disable the interrupt and clear the status */
|
||||
__raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
|
||||
__raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
|
||||
|
||||
/* clear address has to be used to clear IRQSTAT bits */
|
||||
__mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
|
||||
|
||||
for (j = port[i].virtual_irq_start;
|
||||
j < port[i].virtual_irq_start + 32; j++) {
|
||||
irq_set_chip_and_handler(j, &gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(j, IRQF_VALID);
|
||||
/*
|
||||
* map memory region only once, as all the gpio ports
|
||||
* share the same one
|
||||
*/
|
||||
if (!base) {
|
||||
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!iores) {
|
||||
err = -ENODEV;
|
||||
goto out_kfree;
|
||||
}
|
||||
|
||||
/* setup one handler for each entry */
|
||||
irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
|
||||
irq_set_handler_data(port[i].irq, &port[i]);
|
||||
if (!request_mem_region(iores->start, resource_size(iores),
|
||||
pdev->name)) {
|
||||
err = -EBUSY;
|
||||
goto out_kfree;
|
||||
}
|
||||
|
||||
/* register gpio chip */
|
||||
port[i].chip.direction_input = mxs_gpio_direction_input;
|
||||
port[i].chip.direction_output = mxs_gpio_direction_output;
|
||||
port[i].chip.get = mxs_gpio_get;
|
||||
port[i].chip.set = mxs_gpio_set;
|
||||
port[i].chip.to_irq = mxs_gpio_to_irq;
|
||||
port[i].chip.base = i * 32;
|
||||
port[i].chip.ngpio = 32;
|
||||
|
||||
/* its a serious configuration bug when it fails */
|
||||
BUG_ON(gpiochip_add(&port[i].chip) < 0);
|
||||
base = ioremap(iores->start, resource_size(iores));
|
||||
if (!base) {
|
||||
err = -ENOMEM;
|
||||
goto out_release_mem;
|
||||
}
|
||||
}
|
||||
port->base = base;
|
||||
|
||||
port->irq = platform_get_irq(pdev, 0);
|
||||
if (port->irq < 0) {
|
||||
err = -EINVAL;
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
/* disable the interrupt and clear the status */
|
||||
writel(0, port->base + PINCTRL_PIN2IRQ(port->id));
|
||||
writel(0, port->base + PINCTRL_IRQEN(port->id));
|
||||
|
||||
/* clear address has to be used to clear IRQSTAT bits */
|
||||
writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
|
||||
|
||||
for (i = port->virtual_irq_start;
|
||||
i < port->virtual_irq_start + 32; i++) {
|
||||
irq_set_chip_and_handler(i, &gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID);
|
||||
irq_set_chip_data(i, port);
|
||||
}
|
||||
|
||||
/* setup one handler for each entry */
|
||||
irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
|
||||
irq_set_handler_data(port->irq, port);
|
||||
|
||||
/* register gpio chip */
|
||||
port->chip.direction_input = mxs_gpio_direction_input;
|
||||
port->chip.direction_output = mxs_gpio_direction_output;
|
||||
port->chip.get = mxs_gpio_get;
|
||||
port->chip.set = mxs_gpio_set;
|
||||
port->chip.to_irq = mxs_gpio_to_irq;
|
||||
port->chip.base = port->id * 32;
|
||||
port->chip.ngpio = 32;
|
||||
|
||||
err = gpiochip_add(&port->chip);
|
||||
if (err)
|
||||
goto out_iounmap;
|
||||
|
||||
return 0;
|
||||
|
||||
out_iounmap:
|
||||
if (iores)
|
||||
iounmap(port->base);
|
||||
out_release_mem:
|
||||
if (iores)
|
||||
release_mem_region(iores->start, resource_size(iores));
|
||||
out_kfree:
|
||||
kfree(port);
|
||||
dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
|
||||
#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
|
||||
|
||||
#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \
|
||||
{ \
|
||||
.chip.label = "gpio-" #_id, \
|
||||
.id = _id, \
|
||||
.irq = _irq, \
|
||||
.base = _base, \
|
||||
.virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX23
|
||||
static struct mxs_gpio_port mx23_gpio_ports[] = {
|
||||
DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
|
||||
DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
|
||||
DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
|
||||
static struct platform_driver mxs_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "gpio-mxs",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = mxs_gpio_probe,
|
||||
};
|
||||
|
||||
int __init mx23_register_gpios(void)
|
||||
static int __init mxs_gpio_init(void)
|
||||
{
|
||||
return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
|
||||
return platform_driver_register(&mxs_gpio_driver);
|
||||
}
|
||||
#endif
|
||||
postcore_initcall(mxs_gpio_init);
|
||||
|
||||
#ifdef CONFIG_SOC_IMX28
|
||||
static struct mxs_gpio_port mx28_gpio_ports[] = {
|
||||
DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
|
||||
DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
|
||||
DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
|
||||
DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
|
||||
DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
|
||||
};
|
||||
|
||||
int __init mx28_register_gpios(void)
|
||||
{
|
||||
return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
|
||||
}
|
||||
#endif
|
||||
MODULE_AUTHOR("Freescale Semiconductor, "
|
||||
"Daniel Mack <danielncaiaq.de>, "
|
||||
"Juergen Beisert <kernel@pengutronix.de>");
|
||||
MODULE_DESCRIPTION("Freescale MXS GPIO");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -296,7 +296,7 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
|||
* If the TjMax is not plausible, an assumption
|
||||
* will be used
|
||||
*/
|
||||
if (val > 80 && val < 120) {
|
||||
if (val) {
|
||||
dev_info(dev, "TjMax is %d C.\n", val);
|
||||
return val * 1000;
|
||||
}
|
||||
|
@ -304,24 +304,9 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
|||
|
||||
/*
|
||||
* An assumption is made for early CPUs and unreadable MSR.
|
||||
* NOTE: the given value may not be correct.
|
||||
* NOTE: the calculated value may not be correct.
|
||||
*/
|
||||
|
||||
switch (c->x86_model) {
|
||||
case 0xe:
|
||||
case 0xf:
|
||||
case 0x16:
|
||||
case 0x1a:
|
||||
dev_warn(dev, "TjMax is assumed as 100 C!\n");
|
||||
return 100000;
|
||||
case 0x17:
|
||||
case 0x1c: /* Atom CPUs */
|
||||
return adjust_tjmax(c, id, dev);
|
||||
default:
|
||||
dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
|
||||
" using default TjMax of 100C.\n", c->x86_model);
|
||||
return 100000;
|
||||
}
|
||||
return adjust_tjmax(c, id, dev);
|
||||
}
|
||||
|
||||
static void __devinit get_ucode_rev_on_cpu(void *edx)
|
||||
|
@ -341,7 +326,7 @@ static int get_pkg_tjmax(unsigned int cpu, struct device *dev)
|
|||
err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
|
||||
if (!err) {
|
||||
val = (eax >> 16) & 0xff;
|
||||
if (val > 80 && val < 120)
|
||||
if (val)
|
||||
return val * 1000;
|
||||
}
|
||||
dev_warn(dev, "Unable to read Pkg-TjMax from CPU:%u\n", cpu);
|
||||
|
|
|
@ -136,15 +136,29 @@ static int max6642_detect(struct i2c_client *client,
|
|||
if (man_id != 0x4D)
|
||||
return -ENODEV;
|
||||
|
||||
/* sanity check */
|
||||
if (i2c_smbus_read_byte_data(client, 0x04) != 0x4D
|
||||
|| i2c_smbus_read_byte_data(client, 0x06) != 0x4D
|
||||
|| i2c_smbus_read_byte_data(client, 0xff) != 0x4D)
|
||||
return -ENODEV;
|
||||
|
||||
/*
|
||||
* We read the config and status register, the 4 lower bits in the
|
||||
* config register should be zero and bit 5, 3, 1 and 0 should be
|
||||
* zero in the status register.
|
||||
*/
|
||||
reg_config = i2c_smbus_read_byte_data(client, MAX6642_REG_R_CONFIG);
|
||||
if ((reg_config & 0x0f) != 0x00)
|
||||
return -ENODEV;
|
||||
|
||||
/* in between, another round of sanity checks */
|
||||
if (i2c_smbus_read_byte_data(client, 0x04) != reg_config
|
||||
|| i2c_smbus_read_byte_data(client, 0x06) != reg_config
|
||||
|| i2c_smbus_read_byte_data(client, 0xff) != reg_config)
|
||||
return -ENODEV;
|
||||
|
||||
reg_status = i2c_smbus_read_byte_data(client, MAX6642_REG_R_STATUS);
|
||||
if (((reg_config & 0x0f) != 0x00) ||
|
||||
((reg_status & 0x2b) != 0x00))
|
||||
if ((reg_status & 0x2b) != 0x00)
|
||||
return -ENODEV;
|
||||
|
||||
strlcpy(info->type, "max6642", I2C_NAME_SIZE);
|
||||
|
@ -246,7 +260,7 @@ static SENSOR_DEVICE_ATTR_2(temp1_max, S_IWUSR | S_IRUGO, show_temp_max,
|
|||
set_temp_max, 0, MAX6642_REG_W_LOCAL_HIGH);
|
||||
static SENSOR_DEVICE_ATTR_2(temp2_max, S_IWUSR | S_IRUGO, show_temp_max,
|
||||
set_temp_max, 1, MAX6642_REG_W_REMOTE_HIGH);
|
||||
static SENSOR_DEVICE_ATTR(temp_fault, S_IRUGO, show_alarm, NULL, 2);
|
||||
static SENSOR_DEVICE_ATTR(temp2_fault, S_IRUGO, show_alarm, NULL, 2);
|
||||
static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL, 6);
|
||||
static SENSOR_DEVICE_ATTR(temp2_max_alarm, S_IRUGO, show_alarm, NULL, 4);
|
||||
|
||||
|
@ -256,7 +270,7 @@ static struct attribute *max6642_attributes[] = {
|
|||
&sensor_dev_attr_temp1_max.dev_attr.attr,
|
||||
&sensor_dev_attr_temp2_max.dev_attr.attr,
|
||||
|
||||
&sensor_dev_attr_temp_fault.dev_attr.attr,
|
||||
&sensor_dev_attr_temp2_fault.dev_attr.attr,
|
||||
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
|
||||
&sensor_dev_attr_temp2_max_alarm.dev_attr.attr,
|
||||
NULL
|
||||
|
|
|
@ -120,21 +120,17 @@ static void serport_ldisc_close(struct tty_struct *tty)
|
|||
* 'interrupt' routine.
|
||||
*/
|
||||
|
||||
static unsigned int serport_ldisc_receive(struct tty_struct *tty,
|
||||
const unsigned char *cp, char *fp, int count)
|
||||
static void serport_ldisc_receive(struct tty_struct *tty, const unsigned char *cp, char *fp, int count)
|
||||
{
|
||||
struct serport *serport = (struct serport*) tty->disc_data;
|
||||
unsigned long flags;
|
||||
unsigned int ch_flags;
|
||||
int ret = 0;
|
||||
int i;
|
||||
|
||||
spin_lock_irqsave(&serport->lock, flags);
|
||||
|
||||
if (!test_bit(SERPORT_ACTIVE, &serport->flags)) {
|
||||
ret = -EINVAL;
|
||||
if (!test_bit(SERPORT_ACTIVE, &serport->flags))
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
switch (fp[i]) {
|
||||
|
@ -156,8 +152,6 @@ static unsigned int serport_ldisc_receive(struct tty_struct *tty,
|
|||
|
||||
out:
|
||||
spin_unlock_irqrestore(&serport->lock, flags);
|
||||
|
||||
return ret == 0 ? count : ret;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -674,7 +674,7 @@ gigaset_tty_ioctl(struct tty_struct *tty, struct file *file,
|
|||
* cflags buffer containing error flags for received characters (ignored)
|
||||
* count number of received characters
|
||||
*/
|
||||
static unsigned int
|
||||
static void
|
||||
gigaset_tty_receive(struct tty_struct *tty, const unsigned char *buf,
|
||||
char *cflags, int count)
|
||||
{
|
||||
|
@ -683,12 +683,12 @@ gigaset_tty_receive(struct tty_struct *tty, const unsigned char *buf,
|
|||
struct inbuf_t *inbuf;
|
||||
|
||||
if (!cs)
|
||||
return -ENODEV;
|
||||
return;
|
||||
inbuf = cs->inbuf;
|
||||
if (!inbuf) {
|
||||
dev_err(cs->dev, "%s: no inbuf\n", __func__);
|
||||
cs_put(cs);
|
||||
return -EINVAL;
|
||||
return;
|
||||
}
|
||||
|
||||
tail = inbuf->tail;
|
||||
|
@ -725,8 +725,6 @@ gigaset_tty_receive(struct tty_struct *tty, const unsigned char *buf,
|
|||
gig_dbg(DEBUG_INTR, "%s-->BH", __func__);
|
||||
gigaset_schedule_event(cs);
|
||||
cs_put(cs);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -747,8 +747,8 @@ static void st_tty_close(struct tty_struct *tty)
|
|||
pr_debug("%s: done ", __func__);
|
||||
}
|
||||
|
||||
static unsigned int st_tty_receive(struct tty_struct *tty,
|
||||
const unsigned char *data, char *tty_flags, int count)
|
||||
static void st_tty_receive(struct tty_struct *tty, const unsigned char *data,
|
||||
char *tty_flags, int count)
|
||||
{
|
||||
#ifdef VERBOSE
|
||||
print_hex_dump(KERN_DEBUG, ">in>", DUMP_PREFIX_NONE,
|
||||
|
@ -761,8 +761,6 @@ static unsigned int st_tty_receive(struct tty_struct *tty,
|
|||
*/
|
||||
st_recv(tty->disc_data, data, count);
|
||||
pr_debug("done %s", __func__);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/* wake-up function called in from the TTY layer
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue