openrisc: head: refactor out tlb flush into it's own function
This brings it inline with the other setup oprations done like the cache enables _ic_enable and _dc_enable. Also, this is going to make it easier to initialize additional cpu's when smp is introduced. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: Added commit body] Signed-off-by: Stafford Horne <shorne@gmail.com>
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@ -522,22 +522,8 @@ enable_dc:
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l.nop
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flush_tlb:
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/*
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* I N V A L I D A T E T L B e n t r i e s
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*/
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LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
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LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
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l.addi r7,r0,128 /* Maximum number of sets */
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1:
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l.mtspr r5,r0,0x0
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l.mtspr r6,r0,0x0
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l.addi r5,r5,1
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l.addi r6,r6,1
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l.sfeq r7,r0
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l.bnf 1b
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l.addi r7,r7,-1
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l.jal _flush_tlb
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l.nop
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/* The MMU needs to be enabled before or32_early_setup is called */
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@ -629,6 +615,26 @@ jump_start_kernel:
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l.jr r30
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l.nop
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_flush_tlb:
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/*
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* I N V A L I D A T E T L B e n t r i e s
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*/
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LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
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LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
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l.addi r7,r0,128 /* Maximum number of sets */
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1:
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l.mtspr r5,r0,0x0
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l.mtspr r6,r0,0x0
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l.addi r5,r5,1
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l.addi r6,r6,1
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l.sfeq r7,r0
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l.bnf 1b
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l.addi r7,r7,-1
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l.jr r9
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l.nop
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/* ========================================[ cache ]=== */
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/* aligment here so we don't change memory offsets with
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