[SPARC64]: Kill pci_controller->base_address_update().
Implemented but never actually used. Signed-off-by: David S. Miller <davem@davemloft.net>
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0bae5f81b6
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8d3aee9375
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@ -894,50 +894,6 @@ static void psycho_register_error_handlers(struct pci_controller_info *p)
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}
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/* PSYCHO boot time probing and initialization. */
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static void psycho_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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struct resource *res, *root;
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u32 reg;
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int where, size, is_64bit;
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res = &pdev->resource[resource];
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if (resource < 6) {
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where = PCI_BASE_ADDRESS_0 + (resource * 4);
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} else if (resource == PCI_ROM_RESOURCE) {
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where = pdev->rom_base_reg;
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} else {
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/* Somebody might have asked allocation of a non-standard resource */
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return;
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}
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is_64bit = 0;
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if (res->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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else {
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root = &pbm->mem_space;
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if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
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== PCI_BASE_ADDRESS_MEM_TYPE_64)
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is_64bit = 1;
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}
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size = res->end - res->start;
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pci_read_config_dword(pdev, where, ®);
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reg = ((reg & size) |
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(((u32)(res->start - root->start)) & ~size));
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if (resource == PCI_ROM_RESOURCE) {
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reg |= PCI_ROM_ADDRESS_ENABLE;
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res->flags |= IORESOURCE_ROM_ENABLE;
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}
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pci_write_config_dword(pdev, where, reg);
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/* This knows that the upper 32-bits of the address
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* must be zero. Our PCI common layer enforces this.
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*/
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if (is_64bit)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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static void pbm_config_busmastering(struct pci_pbm_info *pbm)
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{
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u8 *addr;
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@ -1209,7 +1165,6 @@ void psycho_init(struct device_node *dp, char *model_name)
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p->index = pci_num_controllers++;
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p->pbms_same_domain = 0;
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p->scan_bus = psycho_scan_bus;
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p->base_address_update = psycho_base_address_update;
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p->pci_ops = &psycho_ops;
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prop = of_find_property(dp, "reg", NULL);
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@ -862,51 +862,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
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sabre_write(base + SABRE_PCICTRL, tmp);
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}
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static void sabre_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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struct resource *res;
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unsigned long base;
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u32 reg;
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int where, size, is_64bit;
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res = &pdev->resource[resource];
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if (resource < 6) {
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where = PCI_BASE_ADDRESS_0 + (resource * 4);
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} else if (resource == PCI_ROM_RESOURCE) {
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where = pdev->rom_base_reg;
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} else {
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/* Somebody might have asked allocation of a non-standard resource */
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return;
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}
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is_64bit = 0;
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if (res->flags & IORESOURCE_IO)
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base = pbm->controller_regs + SABRE_IOSPACE;
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else {
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base = pbm->controller_regs + SABRE_MEMSPACE;
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if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
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== PCI_BASE_ADDRESS_MEM_TYPE_64)
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is_64bit = 1;
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}
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size = res->end - res->start;
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pci_read_config_dword(pdev, where, ®);
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reg = ((reg & size) |
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(((u32)(res->start - base)) & ~size));
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if (resource == PCI_ROM_RESOURCE) {
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reg |= PCI_ROM_ADDRESS_ENABLE;
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res->flags |= IORESOURCE_ROM_ENABLE;
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}
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pci_write_config_dword(pdev, where, reg);
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/* This knows that the upper 32-bits of the address
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* must be zero. Our PCI common layer enforces this.
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*/
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if (is_64bit)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
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{
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struct pci_dev *pdev;
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@ -1099,7 +1054,6 @@ void sabre_init(struct device_node *dp, char *model_name)
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p->index = pci_num_controllers++;
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p->pbms_same_domain = 1;
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p->scan_bus = sabre_scan_bus;
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p->base_address_update = sabre_base_address_update;
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p->pci_ops = &sabre_ops;
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/*
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@ -1251,50 +1251,6 @@ static void schizo_scan_bus(struct pci_controller_info *p)
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schizo_register_error_handlers(p);
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}
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static void schizo_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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struct resource *res, *root;
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u32 reg;
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int where, size, is_64bit;
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res = &pdev->resource[resource];
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if (resource < 6) {
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where = PCI_BASE_ADDRESS_0 + (resource * 4);
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} else if (resource == PCI_ROM_RESOURCE) {
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where = pdev->rom_base_reg;
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} else {
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/* Somebody might have asked allocation of a non-standard resource */
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return;
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}
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is_64bit = 0;
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if (res->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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else {
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root = &pbm->mem_space;
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if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
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== PCI_BASE_ADDRESS_MEM_TYPE_64)
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is_64bit = 1;
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}
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size = res->end - res->start;
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pci_read_config_dword(pdev, where, ®);
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reg = ((reg & size) |
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(((u32)(res->start - root->start)) & ~size));
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if (resource == PCI_ROM_RESOURCE) {
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reg |= PCI_ROM_ADDRESS_ENABLE;
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res->flags |= IORESOURCE_ROM_ENABLE;
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}
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pci_write_config_dword(pdev, where, reg);
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/* This knows that the upper 32-bits of the address
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* must be zero. Our PCI common layer enforces this.
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*/
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if (is_64bit)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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#define SCHIZO_STRBUF_CONTROL (0x02800UL)
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#define SCHIZO_STRBUF_FLUSH (0x02808UL)
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#define SCHIZO_STRBUF_FSYNC (0x02810UL)
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@ -1661,7 +1617,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ
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p->index = pci_num_controllers++;
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p->scan_bus = schizo_scan_bus;
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p->base_address_update = schizo_base_address_update;
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p->pci_ops = &schizo_ops;
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/* Like PSYCHO we have a 2GB aligned area for memory space. */
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@ -698,51 +698,6 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p)
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/* XXX register error interrupt handlers XXX */
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}
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static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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struct resource *res, *root;
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u32 reg;
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int where, size, is_64bit;
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res = &pdev->resource[resource];
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if (resource < 6) {
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where = PCI_BASE_ADDRESS_0 + (resource * 4);
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} else if (resource == PCI_ROM_RESOURCE) {
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where = pdev->rom_base_reg;
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} else {
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/* Somebody might have asked allocation of a non-standard resource */
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return;
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}
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/* XXX 64-bit MEM handling is not %100 correct... XXX */
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is_64bit = 0;
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if (res->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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else {
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root = &pbm->mem_space;
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if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
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== PCI_BASE_ADDRESS_MEM_TYPE_64)
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is_64bit = 1;
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}
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size = res->end - res->start;
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pci_read_config_dword(pdev, where, ®);
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reg = ((reg & size) |
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(((u32)(res->start - root->start)) & ~size));
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if (resource == PCI_ROM_RESOURCE) {
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reg |= PCI_ROM_ADDRESS_ENABLE;
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res->flags |= IORESOURCE_ROM_ENABLE;
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}
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pci_write_config_dword(pdev, where, reg);
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/* This knows that the upper 32-bits of the address
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* must be zero. Our PCI common layer enforces this.
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*/
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if (is_64bit)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
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struct pci_iommu *iommu)
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{
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@ -1378,7 +1333,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
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p->pbms_same_domain = 0;
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p->scan_bus = pci_sun4v_scan_bus;
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p->base_address_update = pci_sun4v_base_address_update;
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#ifdef CONFIG_PCI_MSI
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p->setup_msi_irq = pci_sun4v_setup_msi_irq;
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p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
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@ -224,7 +224,6 @@ struct pci_controller_info {
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/* Operations which are controller specific. */
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void (*scan_bus)(struct pci_controller_info *);
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void (*base_address_update)(struct pci_dev *, int);
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#ifdef CONFIG_PCI_MSI
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int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
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