From 766644d2df254934d656a0a0628b636212c24f9e Mon Sep 17 00:00:00 2001 From: Thomas Abraham Date: Sun, 25 Mar 2012 20:32:49 +0530 Subject: [PATCH 1/2] of/irq: add empty irq_of_parse_and_map() for non-dt builds Add a empty irq_of_parse_and_map() function that returns 0 for non-dt builds and avoid having #ifdef CONFIG_OF around all calls to irq_of_parse_and_map(). In addition to that, the irq_of_parse_and_map() function declaration is made available only if CONFIG_OF_IRQ is defined, which is the same config option that makes the irq_of_parse_and_map() function definition available. While at it, fix a typo as well. Changes since v1: - Moved irq_of_parse_and_map() function declaration under CONFIG_OF_IRQ. - Fix a minor typo in comments. Suggested-by: Grant Likely Signed-off-by: Thomas Abraham Acked-by: Rob Herring [grant.likely: fix bug causing SPARC to break] Signed-off-by: Grant Likely --- include/linux/of_irq.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index d229ad3edee0..1717cd935e1c 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -11,7 +11,7 @@ struct of_irq; #include /* - * irq_of_parse_and_map() is used ba all OF enabled platforms; but SPARC + * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC * implements it differently. However, the prototype is the same for all, * so declare it here regardless of the CONFIG_OF_IRQ setting. */ @@ -76,5 +76,13 @@ extern struct device_node *of_irq_find_parent(struct device_node *child); extern void of_irq_init(const struct of_device_id *matches); #endif /* CONFIG_OF_IRQ */ -#endif /* CONFIG_OF */ + +#else /* !CONFIG_OF */ +static inline unsigned int irq_of_parse_and_map(struct device_node *dev, + int index) +{ + return 0; +} +#endif /* !CONFIG_OF */ + #endif /* __OF_IRQ_H */ From 0a68214b76ca858c46b73d2e9792671f0ac0b7e2 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Wed, 9 May 2012 18:57:57 +0100 Subject: [PATCH 2/2] ARM: DT: Add binding for GIC virtualization extentions (VGIC) The GICv2 can have virtualization extension support, consisting of an additional set of registers and interrupts. Add the necessary binding to the GIC DT documentation. Signed-off-by: Marc Zyngier Acked-by: David Vrabel Signed-off-by: Grant Likely --- Documentation/devicetree/bindings/arm/gic.txt | 35 +++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index 9b4b82a721b6..62eb8df1e08d 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -11,7 +11,9 @@ have PPIs or SGIs. Main node required properties: - compatible : should be one of: + "arm,cortex-a15-gic" "arm,cortex-a9-gic" + "arm,cortex-a7-gic" "arm,arm11mp-gic" - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an @@ -39,8 +41,9 @@ Main node required properties: the GIC cpu interface register base and size. Optional -- interrupts : Interrupt source of the parent interrupt controller. Only - present on secondary GICs. +- interrupts : Interrupt source of the parent interrupt controller on + secondary GICs, or VGIC maintainance interrupt on primary GIC (see + below). - cpu-offset : per-cpu offset within the distributor and cpu interface regions, used when the GIC doesn't have banked registers. The offset is @@ -57,3 +60,31 @@ Example: <0xfff10100 0x100>; }; + +* GIC virtualization extensions (VGIC) + +For ARM cores that support the virtualization extensions, additional +properties must be described (they only exist if the GIC is the +primary interrupt controller). + +Required properties: + +- reg : Additional regions specifying the base physical address and + size of the VGIC registers. The first additional region is the GIC + virtual interface control register base and size. The 2nd additional + region is the GIC virtual cpu interface register base and size. + +- interrupts : VGIC maintainance interrupt. + +Example: + + interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x1000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; + };