MLK-16062-1: Fix PXL mipi csi0/1 clock gate register address
mipi csi0/1 clock gate register address swapped. It will cause mipi csi0/1 failed to work. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>pull/10/head
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c659592209
commit
8e076cc387
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@ -102,8 +102,8 @@
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#define IMG_PXL_LINK_DC1_LPCG 0x585C0000
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#define IMG_PXL_LINK_DC0_LPCG 0x585B0000
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#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000
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#define IMG_PXL_LINK_CSI0_LPCG 0x58590000
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#define IMG_PXL_LINK_CSI1_LPCG 0x58580000
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#define IMG_PXL_LINK_CSI1_LPCG 0x58590000
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#define IMG_PXL_LINK_CSI0_LPCG 0x58580000
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#define IMG_PDMA_7_LPCG 0x58570000
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#define IMG_PDMA_6_LPCG 0x58560000
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#define IMG_PDMA_5_LPCG 0x58550000
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@ -99,8 +99,8 @@
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#define IMG_PXL_LINK_DC1_LPCG 0x585C0000
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#define IMG_PXL_LINK_DC0_LPCG 0x585B0000
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#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000
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#define IMG_PXL_LINK_CSI0_LPCG 0x58590000
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#define IMG_PXL_LINK_CSI1_LPCG 0x58580000
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#define IMG_PXL_LINK_CSI1_LPCG 0x58590000
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#define IMG_PXL_LINK_CSI0_LPCG 0x58580000
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#define IMG_PDMA_7_LPCG 0x58570000
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#define IMG_PDMA_6_LPCG 0x58560000
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#define IMG_PDMA_5_LPCG 0x58550000
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