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MLK-20183-1: ARM64: dts：remove the workaround for HDMI on imx8qm A0 

Revert "MLK-17344-2: ARM64: dts: add constraint-rate for hdmi of imx8qm"

This reverts commit 86dbbb61cf.
On imx8qm B0 fix the DPLL jitter issue for HDMI module, so the constraint
for sample rate should be removed

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
pull/10/head
Shengjiu Wang 2018-11-02 17:30:52 +08:00
parent e3ee6d17c7
commit 8e510f8f4c
1 changed files with 5 additions and 18 deletions
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23
arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
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@ -22,7 +22,6 @@
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi-tx";
audio-cpu = <&sai_hdmi_tx>;
constraint-rate = <48000>;
protocol = <1>;
hdmi-out;
};
@ -68,26 +67,14 @@
status = "okay";
};
&amix {
status = "disabled";
};
&sai6 {
status = "disabled";
};
&sai7 {
status = "disabled";
};
&sai_hdmi_tx {
assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
<&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
fsl,sai-asynchronous;
status = "okay";
};