iommu coherency
In dmar_domain, more than one iommus may be included in iommu_bmp. Due to "Coherency" capability may be different across iommus, set this variable to indicate iommu access is coherent or not. Only when all related iommus in a dmar_domain are all coherent, iommu access of this domain is coherent. Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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@ -221,6 +221,8 @@ struct dmar_domain {
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int agaw;
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int flags; /* flags to find out type of domain */
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int iommu_coherency;/* indicate coherency of iommu access */
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};
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/* PCI domain-device relationship */
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@ -396,6 +398,23 @@ static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
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return g_iommus[iommu_id];
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}
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/* "Coherency" capability may be different across iommus */
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static void domain_update_iommu_coherency(struct dmar_domain *domain)
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{
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int i;
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domain->iommu_coherency = 1;
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i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
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for (; i < g_num_of_iommus; ) {
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if (!ecap_coherent(g_iommus[i]->ecap)) {
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domain->iommu_coherency = 0;
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break;
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}
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i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
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}
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}
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/* Gets context entry for a given bus and devfn */
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static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
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u8 bus, u8 devfn)
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@ -1346,6 +1365,11 @@ static int domain_init(struct dmar_domain *domain, int guest_width)
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domain->agaw = agaw;
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INIT_LIST_HEAD(&domain->devices);
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if (ecap_coherent(iommu->ecap))
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domain->iommu_coherency = 1;
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else
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domain->iommu_coherency = 0;
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/* always allocate the top pgd */
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domain->pgd = (struct dma_pte *)alloc_pgtable_page();
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if (!domain->pgd)
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