[TG3]: Add ASPM workaround.
This patch adds workaround to fix performance problems caused by slow PCIE L1->L0 transitions on ICH8 platforms. Changed all magic numbers to constants as suggested by Jeff Garzik. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -3019,6 +3019,16 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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}
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}
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if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
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u32 val = tr32(PCIE_PWR_MGMT_THRESH);
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if (!netif_carrier_ok(tp->dev))
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val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
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tp->pwrmgmt_thresh;
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else
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val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
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tw32(PCIE_PWR_MGMT_THRESH, val);
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}
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return err;
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}
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@ -10004,6 +10014,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
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tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
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}
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if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
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tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
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return;
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}
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@ -10131,6 +10143,14 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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/* bootcode if bit 18 is set */
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if (cfg2 & (1 << 18))
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tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
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if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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u32 cfg3;
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tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
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if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
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tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
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}
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}
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}
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@ -10998,6 +11018,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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*/
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tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
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if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
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tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
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PCIE_PWR_MGMT_L1_THRESH_MSK;
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return err;
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}
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@ -1150,6 +1150,9 @@
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#define VCPU_STATUS_INIT_DONE 0x04000000
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#define VCPU_STATUS_DRV_RESET 0x08000000
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#define VCPU_CFGSHDW 0x00005104
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#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
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/* Mailboxes */
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#define GRCMBOX_BASE 0x00005600
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#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
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@ -1507,6 +1510,8 @@
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#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
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#define PCIE_TRANS_CFG_LOM 0x00000020
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#define PCIE_PWR_MGMT_THRESH 0x00007d28
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#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
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#define TG3_EEPROM_MAGIC 0x669955aa
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#define TG3_EEPROM_MAGIC_FW 0xa5000000
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@ -1593,6 +1598,9 @@
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#define SHASTA_EXT_LED_MAC 0x00010000
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#define SHASTA_EXT_LED_COMBO 0x00018000
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#define NIC_SRAM_DATA_CFG_3 0x00000d3c
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#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
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#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
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#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
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@ -2200,6 +2208,7 @@ struct tg3 {
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#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
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#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
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#define TG3_FLAG_ENABLE_ASF 0x00000020
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#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
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#define TG3_FLAG_POLL_SERDES 0x00000080
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#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
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#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
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@ -2288,6 +2297,7 @@ struct tg3 {
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u32 grc_local_ctrl;
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u32 dma_rwctrl;
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u32 coalesce_mode;
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u32 pwrmgmt_thresh;
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/* PCI block */
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u16 pci_chip_rev_id;
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