EXP litmus_tests: Add comments explaining tests' purposes
This commit adds comments to the litmus tests summarizing what these tests are intended to demonstrate. [ paulmck: Apply Andrea's and Alan's feedback. ] Suggested-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: akiyks@gmail.com Cc: boqun.feng@gmail.com Cc: dhowells@redhat.com Cc: j.alglave@ucl.ac.uk Cc: linux-arch@vger.kernel.org Cc: luc.maranget@inria.fr Cc: nborisov@suse.com Cc: npiggin@gmail.com Cc: parri.andrea@gmail.com Cc: stern@rowland.harvard.edu Cc: will.deacon@arm.com Link: http://lkml.kernel.org/r/1519169112-20593-4-git-send-email-paulmck@linux.vnet.ibm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -1,5 +1,12 @@
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C CoRR+poonceonce+Once
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(*
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* Result: Never
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*
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* Test of read-read coherence, that is, whether or not two successive
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* reads from the same variable are ordered.
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*)
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{}
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P0(int *x)
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@ -1,5 +1,12 @@
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C CoRW+poonceonce+Once
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(*
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* Result: Never
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*
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* Test of read-write coherence, that is, whether or not a read from
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* a given variable and a later write to that same variable are ordered.
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*)
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{}
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P0(int *x)
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@ -1,5 +1,12 @@
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C CoWR+poonceonce+Once
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(*
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* Result: Never
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*
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* Test of write-read coherence, that is, whether or not a write to a
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* given variable and a later read from that same variable are ordered.
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*)
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{}
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P0(int *x)
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@ -1,5 +1,12 @@
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C CoWW+poonceonce
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(*
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* Result: Never
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*
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* Test of write-write coherence, that is, whether or not two successive
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* writes to the same variable are ordered.
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*)
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{}
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P0(int *x)
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@ -1,5 +1,15 @@
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C IRIW+mbonceonces+OnceOnce
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(*
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* Result: Never
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*
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* Test of independent reads from independent writes with smp_mb()
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* between each pairs of reads. In other words, is smp_mb() sufficient to
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* cause two different reading processes to agree on the order of a pair
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* of writes, where each write is to a different variable by a different
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* process?
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*)
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{}
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P0(int *x)
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@ -1,5 +1,15 @@
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C IRIW+poonceonces+OnceOnce
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(*
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* Result: Sometimes
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*
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* Test of independent reads from independent writes with nothing
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* between each pairs of reads. In other words, is anything at all
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* needed to cause two different reading processes to agree on the order
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* of a pair of writes, where each write is to a different variable by a
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* different process?
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*)
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{}
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P0(int *x)
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@ -1,5 +1,14 @@
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C ISA2+poonceonces
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(*
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* Result: Sometimes
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*
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* Given a release-acquire chain ordering the first process's store
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* against the last process's load, is ordering preserved if all of the
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* smp_store_release() invocations are replaced by WRITE_ONCE() and all
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* of the smp_load_acquire() invocations are replaced by READ_ONCE()?
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*)
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{}
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P0(int *x, int *y)
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C ISA2+pooncerelease+poacquirerelease+poacquireonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates that a release-acquire chain suffices
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* to order P0()'s initial write against P2()'s final read. The reason
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* that the release-acquire chain suffices is because in all but one
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* case (P2() to P0()), each process reads from the preceding process's
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* write. In memory-model-speak, there is only one non-reads-from
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* (AKA non-rf) link, so release-acquire is all that is needed.
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*)
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{}
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P0(int *x, int *y)
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C LB+ctrlonceonce+mbonceonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates that lightweight ordering suffices for
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* the load-buffering pattern, in other words, preventing all processes
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* reading from the preceding process's write. In this example, the
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* combination of a control dependency and a full memory barrier are enough
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* to do the trick. (But the full memory barrier could be replaced with
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* another control dependency and order would still be maintained.)
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*)
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{}
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P0(int *x, int *y)
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C LB+poacquireonce+pooncerelease
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(*
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* Result: Never
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*
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* Does a release-acquire pair suffice for the load-buffering litmus
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* test, where each process reads from one of two variables then writes
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* to the other?
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*)
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{}
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P0(int *x, int *y)
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C LB+poonceonces
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(*
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* Result: Sometimes
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*
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* Can the counter-intuitive outcome for the load-buffering pattern
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* be prevented even with no explicit ordering?
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*)
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{}
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P0(int *x, int *y)
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C MP+onceassign+derefonce.litmus
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C MP+onceassign+derefonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates that rcu_assign_pointer() and
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* rcu_dereference() suffice to ensure that an RCU reader will not see
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* pre-initialization garbage when it traverses an RCU-protected data
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* structure containing a newly inserted element.
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*)
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{
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y=z;
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C MP+polocks
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(*
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* Result: Never
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*
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* This litmus test demonstrates how lock acquisitions and releases can
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* stand in for smp_load_acquire() and smp_store_release(), respectively.
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* In other words, when holding a given lock (or indeed after releasing a
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* given lock), a CPU is not only guaranteed to see the accesses that other
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* CPUs made while previously holding that lock, it is also guaranteed
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* to see all prior accesses by those other CPUs.
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*)
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{}
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P0(int *x, int *y, spinlock_t *mylock)
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C MP+poonceonces
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(*
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* Result: Maybe
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*
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* Can the counter-intuitive message-passing outcome be prevented with
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* no ordering at all?
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*)
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{}
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P0(int *x, int *y)
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C MP+pooncerelease+poacquireonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates that smp_store_release() and
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* smp_load_acquire() provide sufficient ordering for the message-passing
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* pattern.
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*)
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{}
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P0(int *x, int *y)
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C MP+porevlocks
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(*
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* Result: Never
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*
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* This litmus test demonstrates how lock acquisitions and releases can
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* stand in for smp_load_acquire() and smp_store_release(), respectively.
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* In other words, when holding a given lock (or indeed after releasing a
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* given lock), a CPU is not only guaranteed to see the accesses that other
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* CPUs made while previously holding that lock, it is also guaranteed to
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* see all prior accesses by those other CPUs.
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*)
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{}
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P0(int *x, int *y, spinlock_t *mylock)
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C MP+wmbonceonce+rmbonceonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates that smp_wmb() and smp_rmb() provide
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* sufficient ordering for the message-passing pattern. However, it
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* is usually better to use smp_store_release() and smp_load_acquire().
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*)
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{}
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P0(int *x, int *y)
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C R+mbonceonces
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(*
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* Result: Never
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*
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* This is the fully ordered (via smp_mb()) version of one of the classic
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* counterintuitive litmus tests that illustrates the effects of store
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* propagation delays. Note that weakening either of the barriers would
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* cause the resulting test to be allowed.
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*)
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{}
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P0(int *x, int *y)
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C R+poonceonces
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(*
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* Result: Sometimes
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*
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* This is the unordered (thus lacking smp_mb()) version of one of the
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* classic counterintuitive litmus tests that illustrates the effects of
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* store propagation delays.
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*)
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{}
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P0(int *x, int *y)
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C S+poonceonces
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(*
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* Result: Sometimes
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*
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* Starting with a two-process release-acquire chain ordering P0()'s
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* first store against P1()'s final load, if the smp_store_release()
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* is replaced by WRITE_ONCE() and the smp_load_acquire() replaced by
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* READ_ONCE(), is ordering preserved?
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*)
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{}
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P0(int *x, int *y)
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C S+wmbonceonce+poacquireonce
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(*
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* Result: Never
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*
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* Can a smp_wmb(), instead of a release, and an acquire order a prior
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* store against a subsequent store?
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*)
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{}
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P0(int *x, int *y)
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C SB+mbonceonces
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(*
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* Result: Never
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*
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* This litmus test demonstrates that full memory barriers suffice to
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* order the store-buffering pattern, where each process writes to the
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* variable that the preceding process reads. (Locking and RCU can also
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* suffice, but not much else.)
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*)
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{}
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P0(int *x, int *y)
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C SB+poonceonces
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(*
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* Result: Sometimes
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*
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* This litmus test demonstrates that at least some ordering is required
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* to order the store-buffering pattern, where each process writes to the
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* variable that the preceding process reads.
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*)
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{}
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P0(int *x, int *y)
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C WRC+poonceonces+Once
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(*
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* Result: Sometimes
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*
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* This litmus test is an extension of the message-passing pattern,
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* where the first write is moved to a separate process. Note that this
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* test has no ordering at all.
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*)
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{}
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P0(int *x)
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C WRC+pooncerelease+rmbonceonce+Once
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(*
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* Result: Never
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*
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* This litmus test is an extension of the message-passing pattern, where
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* the first write is moved to a separate process. Because it features
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* a release and a read memory barrier, it should be forbidden.
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*)
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{}
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P0(int *x)
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C Z6.0+pooncelock+poonceLock+pombonce
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(*
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* Result: Never
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*
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* This litmus test demonstrates how smp_mb__after_spinlock() may be
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* used to ensure that accesses in different critical sections for a
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* given lock running on different CPUs are nevertheless seen in order
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* by CPUs not holding that lock.
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*)
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{}
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P0(int *x, int *y, spinlock_t *mylock)
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C Z6.0+pooncelock+pooncelock+pombonce
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(*
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* Result: Sometimes
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*
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* This example demonstrates that a pair of accesses made by different
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* processes each while holding a given lock will not necessarily be
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* seen as ordered by a third process not holding that lock.
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*)
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{}
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P0(int *x, int *y, spinlock_t *mylock)
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C Z6.0+pooncerelease+poacquirerelease+mbonceonce
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(*
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* Result: Sometimes
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*
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* This litmus test shows that a release-acquire chain, while sufficient
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* when there is but one non-reads-from (AKA non-rf) link, does not suffice
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* if there is more than one. Of the three processes, only P1() reads from
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* P0's write, which means that there are two non-rf links: P1() to P2()
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* is a write-to-write link (AKA a "coherence" or just "co" link) and P2()
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* to P0() is a read-to-write link (AKA a "from-reads" or just "fr" link).
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* When there are two or more non-rf links, you typically will need one
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* full barrier for each non-rf link. (Exceptions include some cases
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* involving locking.)
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*)
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{}
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P0(int *x, int *y)
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