i40evf: A0 silicon specific
A0 stepping silicon specific code Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -32,6 +32,7 @@
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#define I40E_FW_API_VERSION_MAJOR 0x0001
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#define I40E_FW_API_VERSION_MINOR 0x0001
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#define I40E_FW_API_VERSION_A0_MINOR 0x0000
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struct i40e_aq_desc {
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__le16 flags;
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@ -1198,6 +1199,9 @@ struct i40e_aqc_add_remove_cloud_filters_element_data {
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#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
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#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
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I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
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#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002
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#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004
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#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007
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/* 0x0000 reserved */
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#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
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/* 0x0002 reserved */
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@ -1977,7 +1981,9 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
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struct i40e_aqc_remove_udp_tunnel {
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u8 reserved[2];
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u8 index; /* 0 to 15 */
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u8 reserved2[13];
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u8 pf_filters;
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u8 total_filters;
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u8 reserved2[11];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
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@ -1987,13 +1993,31 @@ struct i40e_aqc_del_udp_tunnel_completion {
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u8 index; /* 0 to 15 */
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u8 multiple_pfs;
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u8 total_filters_used;
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u8 reserved1[11];
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u8 reserved;
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u8 tunnels_free;
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u8 reserved1[9];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
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/* tunnel key structure 0x0B10 */
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struct i40e_aqc_tunnel_key_structure_A0 {
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__le16 key1_off;
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__le16 key1_len;
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__le16 key2_off;
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__le16 key2_len;
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__le16 flags;
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#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
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/* response flags */
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#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
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#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
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#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
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u8 resreved[6];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
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struct i40e_aqc_tunnel_key_structure {
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u8 key1_off;
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u8 key2_off;
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@ -109,7 +109,7 @@ enum i40e_hmc_lan_object_size {
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#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
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#define I40E_HMC_OBJ_SIZE_TXQ 128
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#define I40E_HMC_OBJ_SIZE_RXQ 32
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#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 64
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#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
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#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64
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enum i40e_hmc_lan_rsrc_type {
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@ -186,7 +186,7 @@
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#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
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#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
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#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
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#define I40E_PFCM_LANCTXCTL 0x0010C300
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#define I40E_PFCM_LANCTXCTL(_pf) (0x0010C300 + ((_pf) * 4))/* _pf=0..15 */
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#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0
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#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK (0xFFF << I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
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#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12
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@ -195,11 +195,11 @@
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#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK (0x3 << I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
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#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17
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#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK (0x3 << I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
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#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */
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#define I40E_PFCM_LANCTXDATA(_i, _pf) (0x0010C100 + ((_i) * 4) + ((_pf) * 16))/* _i=0...3 _pf=0..15 */
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#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3
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#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
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#define I40E_PFCM_LANCTXDATA_DATA_MASK (0xFFFFFFFF << I40E_PFCM_LANCTXDATA_DATA_SHIFT)
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#define I40E_PFCM_LANCTXSTAT 0x0010C380
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#define I40E_PFCM_LANCTXSTAT(_pf) (0x0010C380 + ((_pf) * 4))/* _pf=0..15 */
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#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
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#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
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#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
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@ -2206,6 +2206,12 @@
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#define I40E_GLPCI_PCIERR 0x000BE4FC
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#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
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#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
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#define I40E_GLPCI_PCITEST2 0x000BE4BC
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#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0
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#define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK (0x1 << I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT)
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#define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT 1
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#define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK (0x1 << I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT)
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#define I40E_GLPCI_PKTCT 0x0009C4BC
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#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
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#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
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