i40e: keep allocated memory in structs
Save both a pointer to memory and the length in order to store all info about allocated kernel memory. This patch changes some adminq allocations to preserve the full i40e_dma_mem/i40e_virt_mem structs for every allocation. Change-Id: Ibcf96159aba4ba61f839d16d87d19478df28e630 Signed-off-by: David Cassard <david.g.cassard@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
04b03013a5
commit
90bb776ae5
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@ -66,9 +66,8 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
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static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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struct i40e_virt_mem mem;
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ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq_mem,
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ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
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i40e_mem_atq_ring,
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(hw->aq.num_asq_entries *
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sizeof(struct i40e_aq_desc)),
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@ -76,21 +75,14 @@ static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
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if (ret_code)
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return ret_code;
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hw->aq.asq.desc = hw->aq.asq_mem.va;
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hw->aq.asq.dma_addr = hw->aq.asq_mem.pa;
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ret_code = i40e_allocate_virt_mem(hw, &mem,
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ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
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(hw->aq.num_asq_entries *
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sizeof(struct i40e_asq_cmd_details)));
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if (ret_code) {
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i40e_free_dma_mem(hw, &hw->aq.asq_mem);
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hw->aq.asq_mem.va = NULL;
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hw->aq.asq_mem.pa = 0;
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i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
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return ret_code;
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}
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hw->aq.asq.details = mem.va;
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return ret_code;
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}
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@ -102,16 +94,11 @@ static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq_mem,
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ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
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i40e_mem_arq_ring,
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(hw->aq.num_arq_entries *
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sizeof(struct i40e_aq_desc)),
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I40E_ADMINQ_DESC_ALIGNMENT);
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if (ret_code)
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return ret_code;
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hw->aq.arq.desc = hw->aq.arq_mem.va;
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hw->aq.arq.dma_addr = hw->aq.arq_mem.pa;
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return ret_code;
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}
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@ -125,14 +112,7 @@ static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
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**/
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static void i40e_free_adminq_asq(struct i40e_hw *hw)
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{
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struct i40e_virt_mem mem;
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i40e_free_dma_mem(hw, &hw->aq.asq_mem);
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hw->aq.asq_mem.va = NULL;
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hw->aq.asq_mem.pa = 0;
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mem.va = hw->aq.asq.details;
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i40e_free_virt_mem(hw, &mem);
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hw->aq.asq.details = NULL;
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i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
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}
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/**
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@ -144,9 +124,7 @@ static void i40e_free_adminq_asq(struct i40e_hw *hw)
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**/
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static void i40e_free_adminq_arq(struct i40e_hw *hw)
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{
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i40e_free_dma_mem(hw, &hw->aq.arq_mem);
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hw->aq.arq_mem.va = NULL;
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hw->aq.arq_mem.pa = 0;
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i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
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}
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/**
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@ -157,7 +135,6 @@ static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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struct i40e_aq_desc *desc;
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struct i40e_virt_mem mem;
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struct i40e_dma_mem *bi;
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int i;
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@ -166,11 +143,11 @@ static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
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*/
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/* buffer_info structures do not need alignment */
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ret_code = i40e_allocate_virt_mem(hw, &mem, (hw->aq.num_arq_entries *
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sizeof(struct i40e_dma_mem)));
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ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
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(hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
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if (ret_code)
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goto alloc_arq_bufs;
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hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)mem.va;
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hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
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/* allocate the mapped buffers */
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for (i = 0; i < hw->aq.num_arq_entries; i++) {
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@ -212,8 +189,7 @@ unwind_alloc_arq_bufs:
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i--;
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for (; i >= 0; i--)
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i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
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mem.va = hw->aq.arq.r.arq_bi;
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i40e_free_virt_mem(hw, &mem);
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i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
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return ret_code;
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}
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@ -225,16 +201,15 @@ unwind_alloc_arq_bufs:
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static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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struct i40e_virt_mem mem;
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struct i40e_dma_mem *bi;
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int i;
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/* No mapped memory needed yet, just the buffer info structures */
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ret_code = i40e_allocate_virt_mem(hw, &mem, (hw->aq.num_asq_entries *
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sizeof(struct i40e_dma_mem)));
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ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
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(hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
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if (ret_code)
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goto alloc_asq_bufs;
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hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)mem.va;
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hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
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/* allocate the mapped buffers */
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for (i = 0; i < hw->aq.num_asq_entries; i++) {
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@ -254,8 +229,7 @@ unwind_alloc_asq_bufs:
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i--;
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for (; i >= 0; i--)
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i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
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mem.va = hw->aq.asq.r.asq_bi;
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i40e_free_virt_mem(hw, &mem);
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i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
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return ret_code;
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}
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@ -266,14 +240,17 @@ unwind_alloc_asq_bufs:
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**/
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static void i40e_free_arq_bufs(struct i40e_hw *hw)
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{
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struct i40e_virt_mem mem;
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int i;
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/* free descriptors */
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for (i = 0; i < hw->aq.num_arq_entries; i++)
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i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
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mem.va = hw->aq.arq.r.arq_bi;
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i40e_free_virt_mem(hw, &mem);
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/* free the descriptor memory */
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i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
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/* free the dma header */
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i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
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}
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/**
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@ -282,7 +259,6 @@ static void i40e_free_arq_bufs(struct i40e_hw *hw)
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**/
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static void i40e_free_asq_bufs(struct i40e_hw *hw)
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{
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struct i40e_virt_mem mem;
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int i;
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/* only unmap if the address is non-NULL */
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@ -290,9 +266,14 @@ static void i40e_free_asq_bufs(struct i40e_hw *hw)
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if (hw->aq.asq.r.asq_bi[i].pa)
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i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
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/* now free the buffer info list */
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mem.va = hw->aq.asq.r.asq_bi;
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i40e_free_virt_mem(hw, &mem);
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/* free the buffer info list */
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i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
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/* free the descriptor memory */
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i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
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/* free the dma header */
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i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
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}
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/**
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@ -305,14 +286,18 @@ static void i40e_config_asq_regs(struct i40e_hw *hw)
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{
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if (hw->mac.type == I40E_MAC_VF) {
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/* configure the transmit queue */
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wr32(hw, I40E_VF_ATQBAH1, upper_32_bits(hw->aq.asq.dma_addr));
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wr32(hw, I40E_VF_ATQBAL1, lower_32_bits(hw->aq.asq.dma_addr));
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wr32(hw, I40E_VF_ATQBAH1,
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upper_32_bits(hw->aq.asq.desc_buf.pa));
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wr32(hw, I40E_VF_ATQBAL1,
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lower_32_bits(hw->aq.asq.desc_buf.pa));
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wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
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I40E_VF_ATQLEN1_ATQENABLE_MASK));
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} else {
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/* configure the transmit queue */
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wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw->aq.asq.dma_addr));
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wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw->aq.asq.dma_addr));
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wr32(hw, I40E_PF_ATQBAH,
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upper_32_bits(hw->aq.asq.desc_buf.pa));
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wr32(hw, I40E_PF_ATQBAL,
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lower_32_bits(hw->aq.asq.desc_buf.pa));
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wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
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I40E_PF_ATQLEN_ATQENABLE_MASK));
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}
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@ -328,14 +313,18 @@ static void i40e_config_arq_regs(struct i40e_hw *hw)
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{
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if (hw->mac.type == I40E_MAC_VF) {
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/* configure the receive queue */
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wr32(hw, I40E_VF_ARQBAH1, upper_32_bits(hw->aq.arq.dma_addr));
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wr32(hw, I40E_VF_ARQBAL1, lower_32_bits(hw->aq.arq.dma_addr));
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wr32(hw, I40E_VF_ARQBAH1,
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upper_32_bits(hw->aq.arq.desc_buf.pa));
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wr32(hw, I40E_VF_ARQBAL1,
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lower_32_bits(hw->aq.arq.desc_buf.pa));
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wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
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I40E_VF_ARQLEN1_ARQENABLE_MASK));
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} else {
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/* configure the receive queue */
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wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw->aq.arq.dma_addr));
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wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw->aq.arq.dma_addr));
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wr32(hw, I40E_PF_ARQBAH,
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upper_32_bits(hw->aq.arq.desc_buf.pa));
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wr32(hw, I40E_PF_ARQBAL,
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lower_32_bits(hw->aq.arq.desc_buf.pa));
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wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
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I40E_PF_ARQLEN_ARQENABLE_MASK));
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}
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@ -483,8 +472,6 @@ static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
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/* free ring buffers */
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i40e_free_asq_bufs(hw);
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/* free the ring descriptors */
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i40e_free_adminq_asq(hw);
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mutex_unlock(&hw->aq.asq_mutex);
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@ -516,8 +503,6 @@ static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
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/* free ring buffers */
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i40e_free_arq_bufs(hw);
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/* free the ring descriptors */
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i40e_free_adminq_arq(hw);
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mutex_unlock(&hw->aq.arq_mutex);
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@ -32,20 +32,20 @@
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#include "i40e_adminq_cmd.h"
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#define I40E_ADMINQ_DESC(R, i) \
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(&(((struct i40e_aq_desc *)((R).desc))[i]))
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(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
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#define I40E_ADMINQ_DESC_ALIGNMENT 4096
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struct i40e_adminq_ring {
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void *desc; /* Descriptor ring memory */
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void *details; /* ASQ details */
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struct i40e_virt_mem dma_head; /* space for dma structures */
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struct i40e_dma_mem desc_buf; /* descriptor ring memory */
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struct i40e_virt_mem cmd_buf; /* command buffer memory */
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union {
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struct i40e_dma_mem *asq_bi;
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struct i40e_dma_mem *arq_bi;
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} r;
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u64 dma_addr; /* Physical address of the ring */
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u16 count; /* Number of descriptors */
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u16 rx_buf_len; /* Admin Receive Queue buffer length */
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};
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#define I40E_ADMINQ_DETAILS(R, i) \
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(&(((struct i40e_asq_cmd_details *)((R).details))[i]))
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(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
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/* ARQ event information */
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struct i40e_arq_event_info {
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@ -95,9 +95,6 @@ struct i40e_adminq_info {
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struct mutex asq_mutex; /* Send queue lock */
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struct mutex arq_mutex; /* Receive queue lock */
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struct i40e_dma_mem asq_mem; /* send queue dynamic memory */
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struct i40e_dma_mem arq_mem; /* receive queue dynamic memory */
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/* last status values on send and receive queues */
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enum i40e_admin_queue_err asq_last_status;
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enum i40e_admin_queue_err arq_last_status;
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@ -192,12 +192,12 @@ static ssize_t i40e_dbg_dump_write(struct file *filp,
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len = (sizeof(struct i40e_aq_desc)
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* pf->hw.aq.num_asq_entries);
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memcpy(p, pf->hw.aq.asq.desc, len);
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memcpy(p, pf->hw.aq.asq.desc_buf.va, len);
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p += len;
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len = (sizeof(struct i40e_aq_desc)
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* pf->hw.aq.num_arq_entries);
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memcpy(p, pf->hw.aq.arq.desc, len);
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memcpy(p, pf->hw.aq.arq.desc_buf.va, len);
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p += len;
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i40e_dbg_dump_data_len = buflen;
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