clk: tegra114: correctly output clk_32k
Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -127,6 +127,7 @@
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#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
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#define PMC_CTRL 0
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#define PMC_CTRL_BLINK_ENB 7
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#define PMC_BLINK_TIMER 0x40
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#define OSC_CTRL 0x50
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#define OSC_CTRL_OSC_FREQ_SHIFT 28
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@ -1625,6 +1626,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
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clks[clk_out_3] = clk;
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/* blink */
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/* clear the blink timer register to directly output clk_32k */
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writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
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clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
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pmc_base + PMC_DPD_PADS_ORIDE,
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PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
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