mfd: twl-core: Enable regcache for audio registers
Enable regmap's regcache for the audio registers: i2c address 0x49, register range 0x01 - 0x49 Mark all other registers as volatile to avoid any side effect for the non audio functions behind 0x49 i2c address. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>wifi-calibration
Peter Ujfalusi
Lee Jones
parent
3def927ea8
commit
9146070089
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@ -47,6 +47,9 @@
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#include <linux/i2c.h>
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#include <linux/i2c/twl.h>
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/* Register descriptions for audio */
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#include <linux/mfd/twl4030-audio.h>
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#include "twl-core.h"
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/*
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@ -200,6 +203,105 @@ static struct twl_mapping twl4030_map[] = {
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{ 2, TWL5031_BASEADD_INTERRUPTS },
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};
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static struct reg_default twl4030_49_defaults[] = {
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/* Audio Registers */
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{ 0x01, 0x00}, /* CODEC_MODE */
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{ 0x02, 0x00}, /* OPTION */
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/* 0x03 Unused */
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{ 0x04, 0x00}, /* MICBIAS_CTL */
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{ 0x05, 0x00}, /* ANAMICL */
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{ 0x06, 0x00}, /* ANAMICR */
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{ 0x07, 0x00}, /* AVADC_CTL */
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{ 0x08, 0x00}, /* ADCMICSEL */
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{ 0x09, 0x00}, /* DIGMIXING */
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{ 0x0a, 0x0f}, /* ATXL1PGA */
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{ 0x0b, 0x0f}, /* ATXR1PGA */
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{ 0x0c, 0x0f}, /* AVTXL2PGA */
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{ 0x0d, 0x0f}, /* AVTXR2PGA */
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{ 0x0e, 0x00}, /* AUDIO_IF */
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{ 0x0f, 0x00}, /* VOICE_IF */
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{ 0x10, 0x3f}, /* ARXR1PGA */
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{ 0x11, 0x3f}, /* ARXL1PGA */
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{ 0x12, 0x3f}, /* ARXR2PGA */
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{ 0x13, 0x3f}, /* ARXL2PGA */
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{ 0x14, 0x25}, /* VRXPGA */
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{ 0x15, 0x00}, /* VSTPGA */
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{ 0x16, 0x00}, /* VRX2ARXPGA */
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{ 0x17, 0x00}, /* AVDAC_CTL */
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{ 0x18, 0x00}, /* ARX2VTXPGA */
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{ 0x19, 0x32}, /* ARXL1_APGA_CTL*/
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{ 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
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{ 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
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{ 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
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{ 0x1d, 0x00}, /* ATX2ARXPGA */
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{ 0x1e, 0x00}, /* BT_IF */
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{ 0x1f, 0x55}, /* BTPGA */
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{ 0x20, 0x00}, /* BTSTPGA */
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{ 0x21, 0x00}, /* EAR_CTL */
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{ 0x22, 0x00}, /* HS_SEL */
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{ 0x23, 0x00}, /* HS_GAIN_SET */
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{ 0x24, 0x00}, /* HS_POPN_SET */
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{ 0x25, 0x00}, /* PREDL_CTL */
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{ 0x26, 0x00}, /* PREDR_CTL */
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{ 0x27, 0x00}, /* PRECKL_CTL */
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{ 0x28, 0x00}, /* PRECKR_CTL */
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{ 0x29, 0x00}, /* HFL_CTL */
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{ 0x2a, 0x00}, /* HFR_CTL */
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{ 0x2b, 0x05}, /* ALC_CTL */
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{ 0x2c, 0x00}, /* ALC_SET1 */
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{ 0x2d, 0x00}, /* ALC_SET2 */
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{ 0x2e, 0x00}, /* BOOST_CTL */
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{ 0x2f, 0x00}, /* SOFTVOL_CTL */
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{ 0x30, 0x13}, /* DTMF_FREQSEL */
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{ 0x31, 0x00}, /* DTMF_TONEXT1H */
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{ 0x32, 0x00}, /* DTMF_TONEXT1L */
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{ 0x33, 0x00}, /* DTMF_TONEXT2H */
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{ 0x34, 0x00}, /* DTMF_TONEXT2L */
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{ 0x35, 0x79}, /* DTMF_TONOFF */
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{ 0x36, 0x11}, /* DTMF_WANONOFF */
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{ 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
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{ 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
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{ 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
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{ 0x3a, 0x06}, /* APLL_CTL */
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{ 0x3b, 0x00}, /* DTMF_CTL */
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{ 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */
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{ 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */
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{ 0x3e, 0x00}, /* MISC_SET_1 */
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{ 0x3f, 0x00}, /* PCMBTMUX */
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/* 0x40 - 0x42 Unused */
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{ 0x43, 0x00}, /* RX_PATH_SEL */
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{ 0x44, 0x32}, /* VDL_APGA_CTL */
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{ 0x45, 0x00}, /* VIBRA_CTL */
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{ 0x46, 0x00}, /* VIBRA_SET */
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{ 0x47, 0x00}, /* VIBRA_PWM_SET */
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{ 0x48, 0x00}, /* ANAMIC_GAIN */
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{ 0x49, 0x00}, /* MISC_SET_2 */
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/* End of Audio Registers */
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};
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static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case 0:
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case 3:
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case 40:
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case 41:
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case 42:
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return false;
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default:
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return true;
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}
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}
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static const struct regmap_range twl4030_49_volatile_ranges[] = {
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regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
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};
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static const struct regmap_access_table twl4030_49_volatile_table = {
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.yes_ranges = twl4030_49_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
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};
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static struct regmap_config twl4030_regmap_config[4] = {
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{
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/* Address 0x48 */
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@ -212,6 +314,15 @@ static struct regmap_config twl4030_regmap_config[4] = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = 0xff,
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.readable_reg = twl4030_49_nop_reg,
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.writeable_reg = twl4030_49_nop_reg,
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.volatile_table = &twl4030_49_volatile_table,
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.reg_defaults = twl4030_49_defaults,
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.num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
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.cache_type = REGCACHE_RBTREE,
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},
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{
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/* Address 0x4a */
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