clk: renesas: r8a7796: Add watchdog clocks
Add all clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXtHgSAAoJEEgEtLw/Ve77DgcP/1620tFIcsgBC5bGlbA54+Zh z9r4cFiCgR7Xsi45UZijKvs8JtiBF5UwQIPokjHP7/KrQFyiQPga7IMUDDC3GwG2 K50zK9q+d1pRl3Gjw8TCvfzYx+ooaGryNrvxyxrMSc5oFG3NtiBLiBdY2muPzTY0 CYMW4dOy33FzG5wsYHEmUQAI+VOW65ovE2j0zoJ8Juj3KHJoe0kvf5dN4Pk0hUCR zZjGqUQ+9P5ZJG8/ToR8lrvOm8B6r9WmN9BLFD2eDmyU6osuPcmQ86pIICA9fHQS uoVv3qjmSqBenEhOKBB6Jp0fhAwwyu1XVSCmb17Rw93QfKDuy4yB1ZP8L+aTQoG9 y1k4H80FFZTVoL5DLHGnB7iJMKUP0ROovoLYs1teGhIj8825C4EtxTITKKHwdbKy 8hOCQBAENxIlX5y7cyhUkdR0O+8kV7r8NYt4LDnYp2oAMD6hgN/7kXf92+QeALxl B5u9Z2sKmPjfmXHE8eH2Z4/aAgMTqRfwaW6U8WFndF6IVsmGWz/p5fhvaLJY1zNf jK5LJWJmKiIkkpiGLhrhVVfl0pyJLQtmIxPv/fIMxUbp1rynT5o6jFOKaWsNRuA2 8Stmca2L/8/BfLpk6z5vRZ95U00++LS5GPSr3PGBfg45HrOVAEUSvvj+vjaggkXR 1YvK2hqYXGZ34pZcFA4i =0CHq -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Merge r8a7796 watchdog clk support from Geert Uytterhoeven: Add all clocks related to the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add watchdog module clock clk: renesas: r8a7796: Add watchdog core clocks
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commit
91d17dc341
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@ -45,6 +45,7 @@ enum clk_ids {
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
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@ -94,10 +95,16 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
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DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
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DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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};
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static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
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DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
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DEF_MOD("rwdt0", 402, R8A7796_CLK_R),
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DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
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};
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