gpio: sch: Consolidate similar algorithms
Consolidating similar algorithms into common functions to make GPIO SCH simpler and manageable. Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -41,7 +41,7 @@ struct sch_gpio {
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unsigned short resume_base;
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};
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#define to_sch_gpio(c) container_of(c, struct sch_gpio, chip)
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#define to_sch_gpio(gc) container_of(gc, struct sch_gpio, chip)
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static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
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unsigned reg)
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@ -63,75 +63,59 @@ static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
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return gpio % 8;
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}
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static void sch_gpio_enable(struct sch_gpio *sch, unsigned gpio)
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{
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unsigned short offset, bit;
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u8 enable;
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spin_lock(&sch->lock);
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offset = sch_gpio_offset(sch, gpio, GEN);
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bit = sch_gpio_bit(sch, gpio);
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enable = inb(sch->iobase + offset);
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if (!(enable & (1 << bit)))
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outb(enable | (1 << bit), sch->iobase + offset);
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spin_unlock(&sch->lock);
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}
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static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
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static int sch_gpio_reg_get(struct gpio_chip *gc, unsigned gpio, unsigned reg)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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u8 curr_dirs;
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unsigned short offset, bit;
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u8 reg_val;
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
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return reg_val;
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}
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static void sch_gpio_reg_set(struct gpio_chip *gc, unsigned gpio, unsigned reg,
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int val)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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unsigned short offset, bit;
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u8 reg_val;
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offset = sch_gpio_offset(sch, gpio, reg);
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bit = sch_gpio_bit(sch, gpio);
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reg_val = inb(sch->iobase + offset);
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if (val)
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outb(reg_val | BIT(bit), sch->iobase + offset);
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else
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outb((reg_val & ~BIT(bit)), sch->iobase + offset);
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}
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static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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spin_lock(&sch->lock);
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offset = sch_gpio_offset(sch, gpio_num, GIO);
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bit = sch_gpio_bit(sch, gpio_num);
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curr_dirs = inb(sch->iobase + offset);
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if (!(curr_dirs & (1 << bit)))
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outb(curr_dirs | (1 << bit), sch->iobase + offset);
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sch_gpio_reg_set(gc, gpio_num, GIO, 1);
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spin_unlock(&sch->lock);
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return 0;
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}
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static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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int res;
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unsigned short offset, bit;
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offset = sch_gpio_offset(sch, gpio_num, GLV);
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bit = sch_gpio_bit(sch, gpio_num);
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res = !!(inb(sch->iobase + offset) & (1 << bit));
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return res;
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return sch_gpio_reg_get(gc, gpio_num, GLV);
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}
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static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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u8 curr_vals;
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unsigned short offset, bit;
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spin_lock(&sch->lock);
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offset = sch_gpio_offset(sch, gpio_num, GLV);
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bit = sch_gpio_bit(sch, gpio_num);
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curr_vals = inb(sch->iobase + offset);
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if (val)
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outb(curr_vals | (1 << bit), sch->iobase + offset);
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else
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outb((curr_vals & ~(1 << bit)), sch->iobase + offset);
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sch_gpio_reg_set(gc, gpio_num, GLV, val);
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spin_unlock(&sch->lock);
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}
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@ -139,18 +123,9 @@ static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
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int val)
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{
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struct sch_gpio *sch = to_sch_gpio(gc);
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u8 curr_dirs;
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unsigned short offset, bit;
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spin_lock(&sch->lock);
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offset = sch_gpio_offset(sch, gpio_num, GIO);
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bit = sch_gpio_bit(sch, gpio_num);
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curr_dirs = inb(sch->iobase + offset);
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if (curr_dirs & (1 << bit))
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outb(curr_dirs & ~(1 << bit), sch->iobase + offset);
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sch_gpio_reg_set(gc, gpio_num, GIO, 0);
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spin_unlock(&sch->lock);
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/*
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@ -209,13 +184,13 @@ static int sch_gpio_probe(struct platform_device *pdev)
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* GPIO7 is configured by the CMC as SLPIOVR
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* Enable GPIO[9:8] core powered gpios explicitly
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*/
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sch_gpio_enable(sch, 8);
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sch_gpio_enable(sch, 9);
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sch_gpio_reg_set(&sch->chip, 8, GEN, 1);
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sch_gpio_reg_set(&sch->chip, 9, GEN, 1);
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/*
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* SUS_GPIO[2:0] enabled by default
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* Enable SUS_GPIO3 resume powered gpio explicitly
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*/
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sch_gpio_enable(sch, 13);
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sch_gpio_reg_set(&sch->chip, 13, GEN, 1);
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break;
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case PCI_DEVICE_ID_INTEL_ITC_LPC:
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