From 921aafde16c84facc76eb1ea24b3943520c988d5 Mon Sep 17 00:00:00 2001 From: Chenyan Feng Date: Thu, 12 Jul 2018 01:15:03 +0800 Subject: [PATCH] MGS-4073 [#ccc] Set GPU AHB CLK to 400M Set GPU AHB CLK to 400M to meet design requirement. Date: 11th Jul, 2018 Signed-off-by: Ella Feng --- arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi index a395b70488ac..f925e040d8d9 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm.dtsi @@ -1091,9 +1091,9 @@ "gpu2d_clk", "gpu2d_axi_clk", "gpu2d_ahb_clk"; - assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, <&clk IMX8MM_CLK_GPU2D_SRC>, <&clk IMX8MM_CLK_GPU_AXI_SRC>, <&clk IMX8MM_CLK_GPU_AHB_SRC>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_CLK_GPU_AHB_DIV>; assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>,<&clk IMX8MM_GPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>; + assigned-clock-rates = <0>, <0>, <0>,<0>,<1000000000>, <400000000>; power-domains = <&gpu_mix_pd>;