Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (96 commits) sh: add support for SMSC Polaris platform sh: fix the HD64461 level-triggered interrupts handling sh: sh-rtc wakeup support sh: sh-rtc invalid time rework sh: sh-rtc carry interrupt rework sh: disallow kexec virtual entry sh: kexec jump: fix for ftrace. sh: kexec: Drop SR.BL bit toggling. sh: add kexec jump support sh: rework kexec segment code sh: simplify kexec vbr code sh: Flush only the needed range when unmapping a VMA. sh: Update debugfs ASID dumping for 16-bit ASID support. sh: tlb-pteaex: Kill off legacy PTEA updates. sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores. sh: sh7763rdp: Change IRQ number for sh_eth of sh7763rdp sh: espt-giga board support sh: dma: Make G2 DMA configurable. sh: dma: Make PVR2 DMA configurable. sh: Move IRQ multi definition of DMAC to defconfig ...
This commit is contained in:
commit
928a726b0e
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@ -107,6 +107,9 @@ config SYS_SUPPORTS_NUMA
|
|||
config SYS_SUPPORTS_PCI
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||||
bool
|
||||
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config SYS_SUPPORTS_CMT
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bool
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config STACKTRACE_SUPPORT
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||||
def_bool y
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||||
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||||
|
@ -176,6 +179,10 @@ config CPU_SHX2
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|||
config CPU_SHX3
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bool
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||||
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config ARCH_SHMOBILE
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bool
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||||
select ARCH_SUSPEND_POSSIBLE
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||||
|
||||
choice
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prompt "Processor sub-type selection"
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||||
|
||||
|
@ -188,6 +195,7 @@ choice
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|||
config CPU_SUBTYPE_SH7619
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bool "Support SH7619 processor"
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select CPU_SH2
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select SYS_SUPPORTS_CMT
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|
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# SH-2A Processor Support
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||||
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||||
|
@ -200,15 +208,18 @@ config CPU_SUBTYPE_SH7203
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bool "Support SH7203 processor"
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select CPU_SH2A
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select CPU_HAS_FPU
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select SYS_SUPPORTS_CMT
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config CPU_SUBTYPE_SH7206
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bool "Support SH7206 processor"
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select CPU_SH2A
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select SYS_SUPPORTS_CMT
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||||
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config CPU_SUBTYPE_SH7263
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bool "Support SH7263 processor"
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select CPU_SH2A
|
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select CPU_HAS_FPU
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select SYS_SUPPORTS_CMT
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config CPU_SUBTYPE_MXG
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bool "Support MX-G processor"
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|
@ -323,7 +334,9 @@ config CPU_SUBTYPE_SH7723
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bool "Support SH7723 processor"
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select CPU_SH4A
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select CPU_SHX2
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select ARCH_SHMOBILE
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_CMT
|
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help
|
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Select SH7723 if you have an SH-MobileR2 CPU.
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|
||||
|
@ -348,6 +361,14 @@ config CPU_SUBTYPE_SH7785
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
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config CPU_SUBTYPE_SH7786
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bool "Support SH7786 processor"
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select CPU_SH4A
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select CPU_SHX3
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select CPU_HAS_PTEAEX
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
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config CPU_SUBTYPE_SHX3
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bool "Support SH-X3 processor"
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select CPU_SH4A
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@ -362,20 +383,26 @@ config CPU_SUBTYPE_SHX3
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config CPU_SUBTYPE_SH7343
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bool "Support SH7343 processor"
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select CPU_SH4AL_DSP
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select ARCH_SHMOBILE
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select SYS_SUPPORTS_CMT
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config CPU_SUBTYPE_SH7722
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bool "Support SH7722 processor"
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select CPU_SH4AL_DSP
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select CPU_SHX2
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select ARCH_SHMOBILE
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_NUMA
|
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select SYS_SUPPORTS_CMT
|
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|
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config CPU_SUBTYPE_SH7366
|
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bool "Support SH7366 processor"
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select CPU_SH4AL_DSP
|
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select CPU_SHX2
|
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select ARCH_SHMOBILE
|
||||
select ARCH_SPARSEMEM_ENABLE
|
||||
select SYS_SUPPORTS_NUMA
|
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select SYS_SUPPORTS_CMT
|
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|
||||
# SH-5 Processor Support
|
||||
|
||||
|
@ -398,25 +425,34 @@ source "arch/sh/boards/Kconfig"
|
|||
menu "Timer and clock configuration"
|
||||
|
||||
config SH_TMU
|
||||
def_bool y
|
||||
prompt "TMU timer support"
|
||||
bool "TMU timer support"
|
||||
depends on CPU_SH3 || CPU_SH4
|
||||
default y
|
||||
select GENERIC_TIME
|
||||
select GENERIC_CLOCKEVENTS
|
||||
help
|
||||
This enables the use of the TMU as the system timer.
|
||||
|
||||
config SH_CMT
|
||||
def_bool y
|
||||
prompt "CMT timer support"
|
||||
depends on CPU_SH2 && !CPU_SUBTYPE_MXG
|
||||
bool "CMT timer support"
|
||||
depends on SYS_SUPPORTS_CMT && CPU_SH2
|
||||
default y
|
||||
help
|
||||
This enables the use of the CMT as the system timer.
|
||||
|
||||
#
|
||||
# Support for the new-style CMT driver. This will replace SH_CMT
|
||||
# once its other dependencies are merged.
|
||||
#
|
||||
config SH_TIMER_CMT
|
||||
bool "CMT clockevents driver"
|
||||
depends on SYS_SUPPORTS_CMT && !SH_CMT
|
||||
select GENERIC_CLOCKEVENTS
|
||||
|
||||
config SH_MTU2
|
||||
def_bool n
|
||||
prompt "MTU2 timer support"
|
||||
bool "MTU2 timer support"
|
||||
depends on CPU_SH2A
|
||||
default y
|
||||
help
|
||||
This enables the use of the MTU2 as the system timer.
|
||||
|
||||
|
@ -426,7 +462,8 @@ config SH_TIMER_IRQ
|
|||
CPU_SUBTYPE_SH7763
|
||||
default "86" if CPU_SUBTYPE_SH7619
|
||||
default "140" if CPU_SUBTYPE_SH7206
|
||||
default "142" if CPU_SUBTYPE_SH7203
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||||
default "142" if CPU_SUBTYPE_SH7203 && SH_CMT
|
||||
default "153" if CPU_SUBTYPE_SH7203 && SH_MTU2
|
||||
default "238" if CPU_SUBTYPE_MXG
|
||||
default "16"
|
||||
|
||||
|
@ -438,7 +475,8 @@ config SH_PCLK_FREQ
|
|||
default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
|
||||
CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
|
||||
CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
|
||||
CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
|
||||
CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \
|
||||
CPU_SUBTYPE_SH7786
|
||||
default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
|
||||
default "66000000" if CPU_SUBTYPE_SH4_202
|
||||
default "50000000"
|
||||
|
@ -521,6 +559,13 @@ config CRASH_DUMP
|
|||
|
||||
For more details see Documentation/kdump/kdump.txt
|
||||
|
||||
config KEXEC_JUMP
|
||||
bool "kexec jump (EXPERIMENTAL)"
|
||||
depends on SUPERH32 && KEXEC && HIBERNATION && EXPERIMENTAL
|
||||
help
|
||||
Jump between original kernel and kexeced kernel and invoke
|
||||
code via KEXEC
|
||||
|
||||
config SECCOMP
|
||||
bool "Enable seccomp to safely compute untrusted bytecode"
|
||||
depends on PROC_FS
|
||||
|
|
|
@ -104,6 +104,9 @@ config CPU_HAS_SR_RB
|
|||
config CPU_HAS_PTEA
|
||||
bool
|
||||
|
||||
config CPU_HAS_PTEAEX
|
||||
bool
|
||||
|
||||
config CPU_HAS_DSP
|
||||
bool
|
||||
|
||||
|
|
|
@ -80,6 +80,7 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
|
|||
defaultimage-$(CONFIG_SUPERH32) := zImage
|
||||
defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
|
||||
defaultimage-$(CONFIG_SH_RSK) := uImage
|
||||
defaultimage-$(CONFIG_SH_URQUELL) := uImage
|
||||
defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
|
||||
defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
|
||||
|
||||
|
|
|
@ -155,17 +155,22 @@ config SH_SH7785LCR
|
|||
|
||||
config SH_SH7785LCR_29BIT_PHYSMAPS
|
||||
bool "SH7785LCR 29bit physmaps"
|
||||
depends on SH_SH7785LCR
|
||||
depends on SH_SH7785LCR && 29BIT
|
||||
default y
|
||||
help
|
||||
This board has 2 physical memory maps. It can be changed with
|
||||
DIP switch(S2-5). If you set the DIP switch for S2-5 = ON,
|
||||
you can access all on-board device in 29bit address mode.
|
||||
|
||||
config SH_URQUELL
|
||||
bool "Urquell"
|
||||
depends on CPU_SUBTYPE_SH7786
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
||||
config SH_MIGOR
|
||||
bool "Migo-R"
|
||||
depends on CPU_SUBTYPE_SH7722
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
help
|
||||
Select Migo-R if configuring for the SH7722 Migo-R platform
|
||||
by Renesas System Solutions Asia Pte. Ltd.
|
||||
|
@ -173,7 +178,7 @@ config SH_MIGOR
|
|||
config SH_AP325RXA
|
||||
bool "AP-325RXA"
|
||||
depends on CPU_SUBTYPE_SH7723
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
help
|
||||
Renesas "AP-325RXA" support.
|
||||
Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
|
||||
|
@ -185,6 +190,13 @@ config SH_SH7763RDP
|
|||
Select SH7763RDP if configuring for a Renesas SH7763
|
||||
evaluation board.
|
||||
|
||||
config SH_ESPT
|
||||
bool "ESPT"
|
||||
depends on CPU_SUBTYPE_SH7763
|
||||
help
|
||||
Select ESPT if configuring for a Renesas SH7763
|
||||
with gigabit ether evaluation board.
|
||||
|
||||
config SH_EDOSK7705
|
||||
bool "EDOSK7705"
|
||||
depends on CPU_SUBTYPE_SH7705
|
||||
|
@ -240,7 +252,7 @@ config SH_X3PROTO
|
|||
config SH_MAGIC_PANEL_R2
|
||||
bool "Magic Panel R2"
|
||||
depends on CPU_SUBTYPE_SH7720
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
help
|
||||
Select Magic Panel R2 if configuring for Magic Panel R2.
|
||||
|
||||
|
@ -249,6 +261,13 @@ config SH_CAYMAN
|
|||
depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
|
||||
select SYS_SUPPORTS_PCI
|
||||
|
||||
config SH_POLARIS
|
||||
bool "SMSC Polaris"
|
||||
select CPU_HAS_IPR_IRQ
|
||||
depends on CPU_SUBTYPE_SH7709
|
||||
help
|
||||
Select if configuring for an SMSC Polaris development board
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/sh/boards/mach-r2d/Kconfig"
|
||||
|
|
|
@ -4,5 +4,8 @@
|
|||
obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o
|
||||
obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
|
||||
obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
|
||||
obj-$(CONFIG_SH_URQUELL) += board-urquell.o
|
||||
obj-$(CONFIG_SH_SHMIN) += board-shmin.o
|
||||
obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
|
||||
obj-$(CONFIG_SH_ESPT) += board-espt.o
|
||||
obj-$(CONFIG_SH_POLARIS) += board-polaris.o
|
||||
|
|
|
@ -166,6 +166,16 @@ static void ap320_wvga_power_on(void *board_data)
|
|||
ctrl_outw(0x100, FPGA_BKLREG);
|
||||
}
|
||||
|
||||
static void ap320_wvga_power_off(void *board_data)
|
||||
{
|
||||
/* backlight */
|
||||
ctrl_outw(0, FPGA_BKLREG);
|
||||
gpio_set_value(GPIO_PTS3, 1);
|
||||
|
||||
/* ASD AP-320/325 LCD OFF */
|
||||
ctrl_outw(0, FPGA_LCDREG);
|
||||
}
|
||||
|
||||
static struct sh_mobile_lcdc_info lcdc_info = {
|
||||
.clock_source = LCDC_CLK_EXTERNAL,
|
||||
.ch[0] = {
|
||||
|
@ -191,6 +201,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
|
|||
},
|
||||
.board_cfg = {
|
||||
.display_on = ap320_wvga_power_on,
|
||||
.display_off = ap320_wvga_power_off,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
|
102
arch/sh/boards/board-espt.c
Normal file
102
arch/sh/boards/board-espt.c
Normal file
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Data Technology Inc. ESPT-GIGA board suport
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
|
||||
* Copyright (C) 2008, 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/sh_eth.h>
|
||||
|
||||
/* NOR Flash */
|
||||
static struct mtd_partition espt_nor_flash_partitions[] = {
|
||||
{
|
||||
.name = "U-Boot",
|
||||
.offset = 0,
|
||||
.size = (2 * SZ_128K),
|
||||
.mask_flags = MTD_WRITEABLE, /* Read-only */
|
||||
}, {
|
||||
.name = "Linux-Kernel",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = (20 * SZ_128K),
|
||||
}, {
|
||||
.name = "Root Filesystem",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct physmap_flash_data espt_nor_flash_data = {
|
||||
.width = 2,
|
||||
.parts = espt_nor_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(espt_nor_flash_partitions),
|
||||
};
|
||||
|
||||
static struct resource espt_nor_flash_resources[] = {
|
||||
[0] = {
|
||||
.name = "NOR Flash",
|
||||
.start = 0,
|
||||
.end = SZ_8M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device espt_nor_flash_device = {
|
||||
.name = "physmap-flash",
|
||||
.resource = espt_nor_flash_resources,
|
||||
.num_resources = ARRAY_SIZE(espt_nor_flash_resources),
|
||||
.dev = {
|
||||
.platform_data = &espt_nor_flash_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SH-Ether */
|
||||
static struct resource sh_eth_resources[] = {
|
||||
{
|
||||
.start = 0xFEE00800, /* use eth1 */
|
||||
.end = 0xFEE00F7C - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 57, /* irq number */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_eth_plat_data sh7763_eth_pdata = {
|
||||
.phy = 0,
|
||||
.edmac_endian = EDMAC_LITTLE_ENDIAN,
|
||||
};
|
||||
|
||||
static struct platform_device espt_eth_device = {
|
||||
.name = "sh-eth",
|
||||
.resource = sh_eth_resources,
|
||||
.num_resources = ARRAY_SIZE(sh_eth_resources),
|
||||
.dev = {
|
||||
.platform_data = &sh7763_eth_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *espt_devices[] __initdata = {
|
||||
&espt_nor_flash_device,
|
||||
&espt_eth_device,
|
||||
};
|
||||
|
||||
static int __init espt_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(espt_devices,
|
||||
ARRAY_SIZE(espt_devices));
|
||||
}
|
||||
device_initcall(espt_devices_setup);
|
||||
|
||||
static struct sh_machine_vector mv_espt __initmv = {
|
||||
.mv_name = "ESPT-GIGA",
|
||||
};
|
149
arch/sh/boards/board-polaris.c
Normal file
149
arch/sh/boards/board-polaris.c
Normal file
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* June 2006 steve.glendinning@smsc.com
|
||||
*
|
||||
* Polaris-specific resource declaration
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/heartbeat.h>
|
||||
#include <cpu/gpio.h>
|
||||
#include <mach-se/mach/se.h>
|
||||
|
||||
#define BCR2 (0xFFFFFF62)
|
||||
#define WCR2 (0xFFFFFF66)
|
||||
#define AREA5_WAIT_CTRL (0x1C00)
|
||||
#define WAIT_STATES_10 (0x7)
|
||||
|
||||
static struct resource smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.name = "smsc911x-memory",
|
||||
.start = PA_EXT5,
|
||||
.end = PA_EXT5 + 0x1fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.name = "smsc911x-irq",
|
||||
.start = IRQ0_IRQ,
|
||||
.end = IRQ0_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_config = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
|
||||
.flags = SMSC911X_USE_32BIT,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
};
|
||||
|
||||
static struct platform_device smsc911x_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
.resource = smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_config,
|
||||
},
|
||||
};
|
||||
|
||||
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
|
||||
|
||||
static struct heartbeat_data heartbeat_data = {
|
||||
.bit_pos = heartbeat_bit_pos,
|
||||
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
|
||||
.regsize = 8,
|
||||
};
|
||||
|
||||
static struct resource heartbeat_resources[] = {
|
||||
[0] = {
|
||||
.start = PORT_PCDR,
|
||||
.end = PORT_PCDR,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device heartbeat_device = {
|
||||
.name = "heartbeat",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &heartbeat_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(heartbeat_resources),
|
||||
.resource = heartbeat_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *polaris_devices[] __initdata = {
|
||||
&smsc911x_device,
|
||||
&heartbeat_device,
|
||||
};
|
||||
|
||||
static int __init polaris_initialise(void)
|
||||
{
|
||||
u16 wcr, bcr_mask;
|
||||
|
||||
printk(KERN_INFO "Configuring Polaris external bus\n");
|
||||
|
||||
/* Configure area 5 with 2 wait states */
|
||||
wcr = ctrl_inw(WCR2);
|
||||
wcr &= (~AREA5_WAIT_CTRL);
|
||||
wcr |= (WAIT_STATES_10 << 10);
|
||||
ctrl_outw(wcr, WCR2);
|
||||
|
||||
/* Configure area 5 for 32-bit access */
|
||||
bcr_mask = ctrl_inw(BCR2);
|
||||
bcr_mask |= 1 << 10;
|
||||
ctrl_outw(bcr_mask, BCR2);
|
||||
|
||||
return platform_add_devices(polaris_devices,
|
||||
ARRAY_SIZE(polaris_devices));
|
||||
}
|
||||
arch_initcall(polaris_initialise);
|
||||
|
||||
static struct ipr_data ipr_irq_table[] = {
|
||||
/* External IRQs */
|
||||
{ IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
|
||||
{ IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
|
||||
};
|
||||
|
||||
static unsigned long ipr_offsets[] = {
|
||||
INTC_IPRC
|
||||
};
|
||||
|
||||
static struct ipr_desc ipr_irq_desc = {
|
||||
.ipr_offsets = ipr_offsets,
|
||||
.nr_offsets = ARRAY_SIZE(ipr_offsets),
|
||||
|
||||
.ipr_data = ipr_irq_table,
|
||||
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
|
||||
.chip = {
|
||||
.name = "sh7709-ext",
|
||||
},
|
||||
};
|
||||
|
||||
static void __init init_polaris_irq(void)
|
||||
{
|
||||
/* Disable all interrupts */
|
||||
ctrl_outw(0, BCR_ILCRA);
|
||||
ctrl_outw(0, BCR_ILCRB);
|
||||
ctrl_outw(0, BCR_ILCRC);
|
||||
ctrl_outw(0, BCR_ILCRD);
|
||||
ctrl_outw(0, BCR_ILCRE);
|
||||
ctrl_outw(0, BCR_ILCRF);
|
||||
ctrl_outw(0, BCR_ILCRG);
|
||||
|
||||
register_ipr_controller(&ipr_irq_desc);
|
||||
}
|
||||
|
||||
static struct sh_machine_vector mv_polaris __initmv = {
|
||||
.mv_name = "Polaris",
|
||||
.mv_nr_irqs = 61,
|
||||
.mv_init_irq = init_polaris_irq,
|
||||
};
|
|
@ -275,7 +275,18 @@ void __init init_sh7785lcr_IRQ(void)
|
|||
|
||||
static void sh7785lcr_power_off(void)
|
||||
{
|
||||
ctrl_outb(0x01, P2SEGADDR(PLD_POFCR));
|
||||
unsigned char *p;
|
||||
|
||||
p = ioremap(PLD_POFCR, PLD_POFCR + 1);
|
||||
if (!p) {
|
||||
printk(KERN_ERR "%s: ioremap error.\n", __func__);
|
||||
return;
|
||||
}
|
||||
*p = 0x01;
|
||||
iounmap(p);
|
||||
set_bl_bit();
|
||||
while (1)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/* Initialize the board */
|
||||
|
|
162
arch/sh/boards/board-urquell.c
Normal file
162
arch/sh/boards/board-urquell.c
Normal file
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Renesas Technology Corp. SH7786 Urquell Support.
|
||||
*
|
||||
* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/smc91x.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/irq.h>
|
||||
#include <mach/urquell.h>
|
||||
#include <cpu/sh7786.h>
|
||||
#include <asm/heartbeat.h>
|
||||
#include <asm/sizes.h>
|
||||
|
||||
static struct resource heartbeat_resources[] = {
|
||||
[0] = {
|
||||
.start = BOARDREG(SLEDR),
|
||||
.end = BOARDREG(SLEDR),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct heartbeat_data heartbeat_data = {
|
||||
.regsize = 16,
|
||||
};
|
||||
|
||||
static struct platform_device heartbeat_device = {
|
||||
.name = "heartbeat",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &heartbeat_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(heartbeat_resources),
|
||||
.resource = heartbeat_resources,
|
||||
};
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
};
|
||||
|
||||
static struct resource smc91x_eth_resources[] = {
|
||||
[0] = {
|
||||
.name = "SMC91C111" ,
|
||||
.start = 0x05800300,
|
||||
.end = 0x0580030f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 11,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_eth_device = {
|
||||
.name = "smc91x",
|
||||
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
|
||||
.resource = smc91x_eth_resources,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mtd_partition nor_flash_partitions[] = {
|
||||
{
|
||||
.name = "loader",
|
||||
.offset = 0x00000000,
|
||||
.size = SZ_512K,
|
||||
.mask_flags = MTD_WRITEABLE, /* Read-only */
|
||||
},
|
||||
{
|
||||
.name = "bootenv",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = SZ_512K,
|
||||
.mask_flags = MTD_WRITEABLE, /* Read-only */
|
||||
},
|
||||
{
|
||||
.name = "kernel",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = SZ_4M,
|
||||
},
|
||||
{
|
||||
.name = "data",
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct physmap_flash_data nor_flash_data = {
|
||||
.width = 2,
|
||||
.parts = nor_flash_partitions,
|
||||
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
|
||||
};
|
||||
|
||||
static struct resource nor_flash_resources[] = {
|
||||
[0] = {
|
||||
.start = NOR_FLASH_ADDR,
|
||||
.end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device nor_flash_device = {
|
||||
.name = "physmap-flash",
|
||||
.dev = {
|
||||
.platform_data = &nor_flash_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(nor_flash_resources),
|
||||
.resource = nor_flash_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *urquell_devices[] __initdata = {
|
||||
&heartbeat_device,
|
||||
&smc91x_eth_device,
|
||||
&nor_flash_device,
|
||||
};
|
||||
|
||||
static int __init urquell_devices_setup(void)
|
||||
{
|
||||
/* USB */
|
||||
gpio_request(GPIO_FN_USB_OVC0, NULL);
|
||||
gpio_request(GPIO_FN_USB_PENC0, NULL);
|
||||
|
||||
return platform_add_devices(urquell_devices,
|
||||
ARRAY_SIZE(urquell_devices));
|
||||
}
|
||||
device_initcall(urquell_devices_setup);
|
||||
|
||||
static void urquell_power_off(void)
|
||||
{
|
||||
__raw_writew(0xa5a5, UBOARDREG(SRSTR));
|
||||
}
|
||||
|
||||
static void __init urquell_init_irq(void)
|
||||
{
|
||||
plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
|
||||
}
|
||||
|
||||
/* Initialize the board */
|
||||
static void __init urquell_setup(char **cmdline_p)
|
||||
{
|
||||
printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
|
||||
|
||||
pm_power_off = urquell_power_off;
|
||||
}
|
||||
|
||||
/*
|
||||
* The Machine Vector
|
||||
*/
|
||||
static struct sh_machine_vector mv_urquell __initmv = {
|
||||
.mv_name = "Urquell",
|
||||
.mv_setup = urquell_setup,
|
||||
.mv_init_irq = urquell_init_irq,
|
||||
};
|
|
@ -18,7 +18,7 @@ config SH_R7780MP
|
|||
config SH_R7785RP
|
||||
bool "R7785RP board support"
|
||||
depends on CPU_SUBTYPE_SH7785
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
|
@ -10,47 +10,32 @@
|
|||
#include <linux/linkage.h>
|
||||
#include <cpu/mmu_context.h>
|
||||
|
||||
#define k0 r0
|
||||
#define k1 r1
|
||||
#define k2 r2
|
||||
#define k3 r3
|
||||
#define k4 r4
|
||||
|
||||
/*
|
||||
* Kernel mode register usage:
|
||||
* k0 scratch
|
||||
* k1 scratch
|
||||
* k2 scratch (Exception code)
|
||||
* k3 scratch (Return address)
|
||||
* k4 scratch
|
||||
* k5 reserved
|
||||
* k6 Global Interrupt Mask (0--15 << 4)
|
||||
* k7 CURRENT_THREAD_INFO (pointer to current thread info)
|
||||
* For more details, please have a look at entry.S
|
||||
*/
|
||||
|
||||
#define k0 r0
|
||||
#define k1 r1
|
||||
|
||||
ENTRY(wakeup_start)
|
||||
! clear STBY bit
|
||||
mov #-126, k2
|
||||
mov #-126, k1
|
||||
and #127, k0
|
||||
mov.b k0, @k2
|
||||
mov.b k0, @k1
|
||||
! enable refresh
|
||||
mov.l 5f, k1
|
||||
mov.w 6f, k0
|
||||
mov.w k0, @k1
|
||||
! jump to handler
|
||||
mov.l 2f, k2
|
||||
mov.l 3f, k3
|
||||
mov.l @k2, k2
|
||||
|
||||
mov.l 4f, k1
|
||||
jmp @k1
|
||||
nop
|
||||
|
||||
.align 2
|
||||
1: .long EXPEVT
|
||||
2: .long INTEVT
|
||||
3: .long ret_from_irq
|
||||
4: .long handle_exception
|
||||
4: .long handle_interrupt
|
||||
5: .long 0xffffff68
|
||||
6: .word 0x0524
|
||||
|
||||
|
|
|
@ -115,7 +115,6 @@ static struct sh_machine_vector mv_hp6xx __initmv = {
|
|||
.mv_setup = hp6xx_setup,
|
||||
/* IRQ's : CPU(64) + CCHIP(16) + FREE_TO_USE(6) */
|
||||
.mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM + 6,
|
||||
.mv_irq_demux = hd64461_irq_demux,
|
||||
/* Enable IRQ0 -> IRQ3 in IRQ_MODE */
|
||||
.mv_init_irq = hp6xx_init_irq,
|
||||
};
|
||||
|
|
|
@ -450,6 +450,14 @@ static struct spi_board_info migor_spi_devices[] = {
|
|||
|
||||
static int __init migor_devices_setup(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
/* Let D11 LED show STATUS0 */
|
||||
gpio_request(GPIO_FN_STATUS0, NULL);
|
||||
|
||||
/* Lit D12 LED show PDSTATUS */
|
||||
gpio_request(GPIO_FN_PDSTATUS, NULL);
|
||||
#else
|
||||
/* Lit D11 LED */
|
||||
gpio_request(GPIO_PTJ7, NULL);
|
||||
gpio_direction_output(GPIO_PTJ7, 1);
|
||||
|
@ -459,6 +467,7 @@ static int __init migor_devices_setup(void)
|
|||
gpio_request(GPIO_PTJ5, NULL);
|
||||
gpio_direction_output(GPIO_PTJ5, 1);
|
||||
gpio_export(GPIO_PTJ5, 0);
|
||||
#endif
|
||||
|
||||
/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
|
||||
gpio_request(GPIO_FN_IRQ0, NULL);
|
||||
|
|
|
@ -10,7 +10,7 @@ config SH_RSK7201
|
|||
|
||||
config SH_RSK7203
|
||||
bool "RSK7203"
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
depends on CPU_SUBTYPE_SH7203
|
||||
|
||||
endchoice
|
||||
|
|
|
@ -63,15 +63,19 @@ static struct platform_device sh7763rdp_nor_flash_device = {
|
|||
},
|
||||
};
|
||||
|
||||
/* SH-Ether */
|
||||
/*
|
||||
* SH-Ether
|
||||
*
|
||||
* SH Ether of SH7763 has multi IRQ handling.
|
||||
* (57,58,59 -> 57)
|
||||
*/
|
||||
static struct resource sh_eth_resources[] = {
|
||||
{
|
||||
.start = 0xFEE00800, /* use eth1 */
|
||||
.end = 0xFEE00F7C - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = 58, /* irq number */
|
||||
.end = 58,
|
||||
.start = 57, /* irq number */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -33,20 +33,24 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
|
|||
$(obj)/compressed/vmlinux: FORCE
|
||||
$(Q)$(MAKE) $(build)=$(obj)/compressed $@
|
||||
|
||||
ifeq ($(CONFIG_32BIT),y)
|
||||
KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
|
||||
$$[$(CONFIG_PAGE_OFFSET) + \
|
||||
$(CONFIG_ZERO_PAGE_OFFSET)]')
|
||||
else
|
||||
KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
|
||||
$$[$(CONFIG_PAGE_OFFSET) + \
|
||||
$(CONFIG_MEMORY_START) + \
|
||||
$(CONFIG_ZERO_PAGE_OFFSET)]')
|
||||
KERNEL_MEMORY := 0x00000000
|
||||
ifeq ($(CONFIG_PMB_FIXED),y)
|
||||
KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
|
||||
$$[$(CONFIG_MEMORY_START) & 0x1fffffff]')
|
||||
endif
|
||||
ifeq ($(CONFIG_29BIT),y)
|
||||
KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
|
||||
$$[$(CONFIG_MEMORY_START)]')
|
||||
endif
|
||||
|
||||
KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
|
||||
$$[$(CONFIG_PAGE_OFFSET) + \
|
||||
$(KERNEL_MEMORY) + \
|
||||
$(CONFIG_ZERO_PAGE_OFFSET)]')
|
||||
|
||||
KERNEL_ENTRY := $(shell /bin/bash -c 'printf "0x%08x" \
|
||||
$$[$(CONFIG_PAGE_OFFSET) + \
|
||||
$(CONFIG_MEMORY_START) + \
|
||||
$(KERNEL_MEMORY) + \
|
||||
$(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]')
|
||||
|
||||
quiet_cmd_uimage = UIMAGE $@
|
||||
|
|
|
@ -53,21 +53,22 @@ static struct irq_chip hd64461_irq_chip = {
|
|||
.unmask = hd64461_unmask_irq,
|
||||
};
|
||||
|
||||
int hd64461_irq_demux(int irq)
|
||||
static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
if (irq == CONFIG_HD64461_IRQ) {
|
||||
unsigned short bit;
|
||||
unsigned short nirr = inw(HD64461_NIRR);
|
||||
unsigned short nimr = inw(HD64461_NIMR);
|
||||
int i;
|
||||
unsigned short intv = ctrl_inw(HD64461_NIRR);
|
||||
struct irq_desc *ext_desc;
|
||||
unsigned int ext_irq = HD64461_IRQBASE;
|
||||
|
||||
nirr &= ~nimr;
|
||||
for (bit = 1, i = 0; i < 16; bit <<= 1, i++)
|
||||
if (nirr & bit)
|
||||
break;
|
||||
irq = HD64461_IRQBASE + i;
|
||||
intv &= (1 << HD64461_IRQ_NUM) - 1;
|
||||
|
||||
while (intv) {
|
||||
if (intv & 1) {
|
||||
ext_desc = irq_desc + ext_irq;
|
||||
handle_level_irq(ext_irq, ext_desc);
|
||||
}
|
||||
intv >>= 1;
|
||||
ext_irq++;
|
||||
}
|
||||
return irq;
|
||||
}
|
||||
|
||||
int __init setup_hd64461(void)
|
||||
|
@ -93,6 +94,9 @@ int __init setup_hd64461(void)
|
|||
set_irq_chip_and_handler(i, &hd64461_irq_chip,
|
||||
handle_level_irq);
|
||||
|
||||
set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
|
||||
set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
#ifdef CONFIG_HD64461_ENABLER
|
||||
printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
|
||||
__raw_writeb(0x4c, HD64461_PCC1CSCIER);
|
||||
|
|
1190
arch/sh/configs/espt_defconfig
Normal file
1190
arch/sh/configs/espt_defconfig
Normal file
File diff suppressed because it is too large
Load diff
969
arch/sh/configs/polaris_defconfig
Normal file
969
arch/sh/configs/polaris_defconfig
Normal file
|
@ -0,0 +1,969 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.29-rc4
|
||||
# Wed Feb 11 18:41:59 2009
|
||||
#
|
||||
CONFIG_SUPERH=y
|
||||
CONFIG_SUPERH32=y
|
||||
CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
# CONFIG_GENERIC_GPIO is not set
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
|
||||
# CONFIG_ARCH_HIBERNATION_POSSIBLE is not set
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_LOCKDEP_SUPPORT=y
|
||||
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
|
||||
CONFIG_ARCH_NO_VIRT_TO_BUS=y
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_LOCK_KERNEL=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
CONFIG_LOCALVERSION=""
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_SYSVIPC_SYSCTL=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
# CONFIG_TASKSTATS is not set
|
||||
CONFIG_AUDIT=y
|
||||
# CONFIG_AUDITSYSCALL is not set
|
||||
|
||||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_GROUP_SCHED=y
|
||||
CONFIG_FAIR_GROUP_SCHED=y
|
||||
# CONFIG_RT_GROUP_SCHED is not set
|
||||
CONFIG_USER_SCHED=y
|
||||
# CONFIG_CGROUP_SCHED is not set
|
||||
# CONFIG_CGROUPS is not set
|
||||
CONFIG_SYSFS_DEPRECATED=y
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
# CONFIG_RELAY is not set
|
||||
# CONFIG_NAMESPACES is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_UID16=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
CONFIG_HOTPLUG=y
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_COMPAT_BRK=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_ANON_INODES=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_SIGNALFD=y
|
||||
CONFIG_TIMERFD=y
|
||||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
# CONFIG_SLOB is not set
|
||||
# CONFIG_PROFILING is not set
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
# CONFIG_KPROBES is not set
|
||||
CONFIG_HAVE_IOREMAP_PROT=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_SLABINFO=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
CONFIG_BASE_SMALL=0
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_MODULE_FORCE_LOAD is not set
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_MODULE_FORCE_UNLOAD is not set
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
# CONFIG_IOSCHED_AS is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
# CONFIG_DEFAULT_AS is not set
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
# System type
|
||||
#
|
||||
CONFIG_CPU_SH3=y
|
||||
# CONFIG_CPU_SUBTYPE_SH7619 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7201 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7203 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7206 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7263 is not set
|
||||
# CONFIG_CPU_SUBTYPE_MXG is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7705 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7706 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7707 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7708 is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7709=y
|
||||
# CONFIG_CPU_SUBTYPE_SH7710 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7712 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7720 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7721 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7750 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7091 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7750R is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7750S is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7751 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7751R is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7760 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7723 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7763 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7770 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7780 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7785 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SHX3 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7343 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7722 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH7366 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH5_101 is not set
|
||||
# CONFIG_CPU_SUBTYPE_SH5_103 is not set
|
||||
|
||||
#
|
||||
# Memory management options
|
||||
#
|
||||
CONFIG_QUICKLIST=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_PAGE_OFFSET=0x80000000
|
||||
CONFIG_MEMORY_START=0x0C000000
|
||||
CONFIG_MEMORY_SIZE=0x04000000
|
||||
CONFIG_29BIT=y
|
||||
CONFIG_VSYSCALL=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
||||
CONFIG_MAX_ACTIVE_REGIONS=1
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_PAGE_SIZE_4KB=y
|
||||
# CONFIG_PAGE_SIZE_8KB is not set
|
||||
# CONFIG_PAGE_SIZE_16KB is not set
|
||||
# CONFIG_PAGE_SIZE_64KB is not set
|
||||
CONFIG_ENTRY_OFFSET=0x00001000
|
||||
CONFIG_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
# CONFIG_DISCONTIGMEM_MANUAL is not set
|
||||
# CONFIG_SPARSEMEM_MANUAL is not set
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
CONFIG_SPARSEMEM_STATIC=y
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_NR_QUICK=2
|
||||
CONFIG_UNEVICTABLE_LRU=y
|
||||
|
||||
#
|
||||
# Cache configuration
|
||||
#
|
||||
# CONFIG_SH_DIRECT_MAPPED is not set
|
||||
CONFIG_CACHE_WRITEBACK=y
|
||||
# CONFIG_CACHE_WRITETHROUGH is not set
|
||||
# CONFIG_CACHE_OFF is not set
|
||||
|
||||
#
|
||||
# Processor features
|
||||
#
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
CONFIG_SH_FPU_EMU=y
|
||||
CONFIG_SH_ADC=y
|
||||
CONFIG_CPU_HAS_INTEVT=y
|
||||
CONFIG_CPU_HAS_IPR_IRQ=y
|
||||
CONFIG_CPU_HAS_SR_RB=y
|
||||
|
||||
#
|
||||
# Board support
|
||||
#
|
||||
# CONFIG_SH_SOLUTION_ENGINE is not set
|
||||
# CONFIG_SH_HP6XX is not set
|
||||
CONFIG_SH_POLARIS=y
|
||||
|
||||
#
|
||||
# Timer and clock configuration
|
||||
#
|
||||
CONFIG_SH_TMU=y
|
||||
CONFIG_SH_TIMER_IRQ=16
|
||||
CONFIG_SH_PCLK_FREQ=33000000
|
||||
CONFIG_TICK_ONESHOT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
|
||||
#
|
||||
# CPU Frequency scaling
|
||||
#
|
||||
# CONFIG_CPU_FREQ is not set
|
||||
|
||||
#
|
||||
# DMA support
|
||||
#
|
||||
CONFIG_SH_DMA_API=y
|
||||
CONFIG_SH_DMA=y
|
||||
CONFIG_NR_ONCHIP_DMA_CHANNELS=4
|
||||
# CONFIG_NR_DMA_CHANNELS_BOOL is not set
|
||||
|
||||
#
|
||||
# Companion Chips
|
||||
#
|
||||
|
||||
#
|
||||
# Additional SuperH Device Drivers
|
||||
#
|
||||
CONFIG_HEARTBEAT=y
|
||||
# CONFIG_PUSH_SWITCH is not set
|
||||
|
||||
#
|
||||
# Kernel features
|
||||
#
|
||||
CONFIG_HZ_100=y
|
||||
# CONFIG_HZ_250 is not set
|
||||
# CONFIG_HZ_300 is not set
|
||||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=100
|
||||
CONFIG_SCHED_HRTICK=y
|
||||
# CONFIG_KEXEC is not set
|
||||
# CONFIG_CRASH_DUMP is not set
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_GUSA=y
|
||||
# CONFIG_GUSA_RB is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
#
|
||||
CONFIG_ZERO_PAGE_OFFSET=0x00001000
|
||||
CONFIG_BOOT_LINK_OFFSET=0x00800000
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="console=ttySC1,115200 root=/dev/mtdblock2 rootfstype=jffs2 mem=63M mtdparts=physmap-flash.0:0x00100000(bootloader)ro,0x00500000(Kernel)ro,0x00A00000(Filesystem)"
|
||||
|
||||
#
|
||||
# Bus options
|
||||
#
|
||||
# CONFIG_ARCH_SUPPORTS_MSI is not set
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
#
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_HAVE_AOUT is not set
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
|
||||
#
|
||||
# Power management options (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_PM is not set
|
||||
# CONFIG_CPU_IDLE is not set
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
CONFIG_COMPAT_NET_DEV_OPS=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_MMAP=y
|
||||
CONFIG_UNIX=y
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
# CONFIG_IP_PNP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
# CONFIG_TCP_MD5SIG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
# CONFIG_IP_DCCP is not set
|
||||
# CONFIG_IP_SCTP is not set
|
||||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_NET_DSA is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_DCB is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_CAN is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
# CONFIG_WIMAX is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
# CONFIG_NET_9P is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
CONFIG_FW_LOADER=y
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_EXTRA_FIRMWARE=""
|
||||
# CONFIG_DEBUG_DRIVER is not set
|
||||
# CONFIG_DEBUG_DEVRES is not set
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
# CONFIG_CONNECTOR is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_DEBUG is not set
|
||||
# CONFIG_MTD_CONCAT is not set
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
# CONFIG_FTL is not set
|
||||
# CONFIG_NFTL is not set
|
||||
# CONFIG_INFTL is not set
|
||||
# CONFIG_RFD_FTL is not set
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
|
||||
#
|
||||
# RAM/ROM/Flash chip drivers
|
||||
#
|
||||
CONFIG_MTD_CFI=y
|
||||
# CONFIG_MTD_JEDECPROBE is not set
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_NOSWAP=y
|
||||
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
|
||||
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
|
||||
# CONFIG_MTD_CFI_GEOMETRY is not set
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
# CONFIG_MTD_CFI_I4 is not set
|
||||
# CONFIG_MTD_CFI_I8 is not set
|
||||
# CONFIG_MTD_OTP is not set
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
# CONFIG_MTD_CFI_AMDSTD is not set
|
||||
# CONFIG_MTD_CFI_STAA is not set
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
# CONFIG_MTD_RAM is not set
|
||||
# CONFIG_MTD_ROM is not set
|
||||
# CONFIG_MTD_ABSENT is not set
|
||||
|
||||
#
|
||||
# Mapping drivers for chip access
|
||||
#
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_COMPAT=y
|
||||
CONFIG_MTD_PHYSMAP_START=0x00000000
|
||||
CONFIG_MTD_PHYSMAP_LEN=0x01000000
|
||||
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
# CONFIG_MTD_PHRAM is not set
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
# CONFIG_MTD_BLOCK2MTD is not set
|
||||
|
||||
#
|
||||
# Disk-On-Chip Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
# LPDDR flash memory drivers
|
||||
#
|
||||
# CONFIG_MTD_LPDDR is not set
|
||||
# CONFIG_MTD_QINFO_PROBE is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_DMA is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_MACVLAN is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_TUN is not set
|
||||
# CONFIG_VETH is not set
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_MARVELL_PHY is not set
|
||||
# CONFIG_DAVICOM_PHY is not set
|
||||
# CONFIG_QSEMI_PHY is not set
|
||||
# CONFIG_LXT_PHY is not set
|
||||
# CONFIG_CICADA_PHY is not set
|
||||
# CONFIG_VITESSE_PHY is not set
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_ICPLUS_PHY is not set
|
||||
# CONFIG_REALTEK_PHY is not set
|
||||
# CONFIG_NATIONAL_PHY is not set
|
||||
# CONFIG_STE10XP is not set
|
||||
# CONFIG_LSI_ET1011C_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
# CONFIG_MDIO_BITBANG is not set
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_AX88796 is not set
|
||||
# CONFIG_STNIC is not set
|
||||
# CONFIG_SMC91X is not set
|
||||
# CONFIG_SMC911X is not set
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_IBM_NEW_EMAC_ZMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
|
||||
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
|
||||
#
|
||||
# Wireless LAN
|
||||
#
|
||||
# CONFIG_WLAN_PRE80211 is not set
|
||||
# CONFIG_WLAN_80211 is not set
|
||||
# CONFIG_IWLWIFI_LEDS is not set
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
# CONFIG_ISDN is not set
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
CONFIG_VT=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_DEVKMEM=y
|
||||
CONFIG_SERIAL_NONSTANDARD=y
|
||||
# CONFIG_N_HDLC is not set
|
||||
# CONFIG_RISCOM8 is not set
|
||||
# CONFIG_SPECIALIX is not set
|
||||
# CONFIG_RIO is not set
|
||||
# CONFIG_STALDRV is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=3
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_I2C is not set
|
||||
# CONFIG_SPI is not set
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_POWER_SUPPLY is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_THERMAL is not set
|
||||
# CONFIG_THERMAL_HWMON is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
|
||||
#
|
||||
# Sonics Silicon Backplane
|
||||
#
|
||||
# CONFIG_SSB is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_CORE is not set
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia core support
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
# CONFIG_DVB_CORE is not set
|
||||
# CONFIG_VIDEO_MEDIA is not set
|
||||
|
||||
#
|
||||
# Multimedia drivers
|
||||
#
|
||||
# CONFIG_DAB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_VGASTATE is not set
|
||||
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Display device support
|
||||
#
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Console display driver support
|
||||
#
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_SOUND is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_HCTOSYS=y
|
||||
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
|
||||
# CONFIG_RTC_DEBUG is not set
|
||||
|
||||
#
|
||||
# RTC interfaces
|
||||
#
|
||||
CONFIG_RTC_INTF_SYSFS=y
|
||||
CONFIG_RTC_INTF_PROC=y
|
||||
CONFIG_RTC_INTF_DEV=y
|
||||
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||
# CONFIG_RTC_DRV_TEST is not set
|
||||
|
||||
#
|
||||
# SPI RTC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_DS1286 is not set
|
||||
# CONFIG_RTC_DRV_DS1511 is not set
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
# CONFIG_RTC_DRV_DS1742 is not set
|
||||
# CONFIG_RTC_DRV_STK17TA8 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_M48T35 is not set
|
||||
# CONFIG_RTC_DRV_M48T59 is not set
|
||||
# CONFIG_RTC_DRV_BQ4802 is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# on-CPU RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_SH=y
|
||||
# CONFIG_DMADEVICES is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_BTRFS_FS is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY is not set
|
||||
# CONFIG_QUOTA is not set
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
# CONFIG_HUGETLBFS is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
CONFIG_MISC_FILESYSTEMS=y
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_DEBUG=0
|
||||
# CONFIG_JFFS2_FS_WRITEBUFFER is not set
|
||||
# CONFIG_JFFS2_SUMMARY is not set
|
||||
# CONFIG_JFFS2_FS_XATTR is not set
|
||||
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
# CONFIG_JFFS2_LZO is not set
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
# CONFIG_JFFS2_RUBIN is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_SQUASHFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_OMFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_SUNRPC_REGISTER_V4 is not set
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
# CONFIG_NLS is not set
|
||||
# CONFIG_DLM is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_WARN_DEPRECATED=y
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_SHIRQ=y
|
||||
CONFIG_DETECT_SOFTLOCKUP=y
|
||||
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
|
||||
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_SCHEDSTATS is not set
|
||||
# CONFIG_TIMER_STATS is not set
|
||||
# CONFIG_DEBUG_OBJECTS is not set
|
||||
# CONFIG_DEBUG_SLAB is not set
|
||||
CONFIG_DEBUG_PREEMPT=y
|
||||
CONFIG_DEBUG_RT_MUTEXES=y
|
||||
CONFIG_DEBUG_PI_LIST=y
|
||||
# CONFIG_RT_MUTEX_TESTER is not set
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_LOCK_ALLOC=y
|
||||
# CONFIG_PROVE_LOCKING is not set
|
||||
CONFIG_LOCKDEP=y
|
||||
# CONFIG_LOCK_STAT is not set
|
||||
# CONFIG_DEBUG_LOCKDEP is not set
|
||||
CONFIG_DEBUG_SPINLOCK_SLEEP=y
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_DEBUG_WRITECOUNT is not set
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_DEBUG_LIST is not set
|
||||
CONFIG_DEBUG_SG=y
|
||||
# CONFIG_DEBUG_NOTIFIERS is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
# CONFIG_BACKTRACE_SELF_TEST is not set
|
||||
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
|
||||
# CONFIG_FAULT_INJECTION is not set
|
||||
# CONFIG_LATENCYTOP is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_FUNCTION_TRACER is not set
|
||||
# CONFIG_IRQSOFF_TRACER is not set
|
||||
# CONFIG_PREEMPT_TRACER is not set
|
||||
# CONFIG_SCHED_TRACER is not set
|
||||
# CONFIG_CONTEXT_SWITCH_TRACER is not set
|
||||
# CONFIG_BOOT_TRACER is not set
|
||||
# CONFIG_TRACE_BRANCH_PROFILING is not set
|
||||
# CONFIG_STACK_TRACER is not set
|
||||
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_KGDB is not set
|
||||
# CONFIG_SH_STANDARD_BIOS is not set
|
||||
CONFIG_EARLY_SCIF_CONSOLE=y
|
||||
CONFIG_EARLY_SCIF_CONSOLE_PORT=0x00000000
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
# CONFIG_DEBUG_BOOTMEM is not set
|
||||
# CONFIG_DEBUG_STACKOVERFLOW is not set
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
# CONFIG_4KSTACKS is not set
|
||||
# CONFIG_IRQSTACKS is not set
|
||||
CONFIG_DUMP_CODE=y
|
||||
# CONFIG_SH_NO_BSS_INIT is not set
|
||||
# CONFIG_MORE_COMPILE_OPTIONS is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
CONFIG_GENERIC_FIND_LAST_BIT=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CRC7 is not set
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_AUDIT_GENERIC=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
1553
arch/sh/configs/sh7785lcr_32bit_defconfig
Normal file
1553
arch/sh/configs/sh7785lcr_32bit_defconfig
Normal file
File diff suppressed because it is too large
Load diff
1332
arch/sh/configs/urquell_defconfig
Normal file
1332
arch/sh/configs/urquell_defconfig
Normal file
File diff suppressed because it is too large
Load diff
|
@ -9,13 +9,21 @@ config SH_DMA
|
|||
select SH_DMA_API
|
||||
default n
|
||||
|
||||
config SH_DMA_IRQ_MULTI
|
||||
bool
|
||||
depends on SH_DMA
|
||||
default y if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \
|
||||
CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \
|
||||
CPU_SUBTYPE_SH7091 || CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \
|
||||
CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
|
||||
|
||||
config NR_ONCHIP_DMA_CHANNELS
|
||||
int
|
||||
depends on SH_DMA
|
||||
default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
|
||||
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
|
||||
default "12" if CPU_SUBTYPE_SH7780
|
||||
default "4"
|
||||
default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S
|
||||
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760
|
||||
default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
|
||||
default "6"
|
||||
help
|
||||
This allows you to specify the number of channels that the on-chip
|
||||
DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the
|
||||
|
@ -46,4 +54,28 @@ config SH_DMABRG
|
|||
of the SH7760.
|
||||
Say Y if you want to use Audio/USB DMA on your SH7760 board.
|
||||
|
||||
config PVR2_DMA
|
||||
tristate "PowerVR 2 DMAC support"
|
||||
depends on SH_DREAMCAST && SH_DMA
|
||||
help
|
||||
Selecting this will enable support for the PVR2 DMA controller.
|
||||
As this chains off of the on-chip DMAC, that must also be
|
||||
enabled by default.
|
||||
|
||||
This is primarily used by the pvr2fb framebuffer driver for
|
||||
certain optimizations, but is not necessary for functionality.
|
||||
|
||||
If in doubt, say N.
|
||||
|
||||
config G2_DMA
|
||||
tristate "G2 Bus DMA support"
|
||||
depends on SH_DREAMCAST
|
||||
select SH_DMA_API
|
||||
help
|
||||
This enables support for the DMA controller for the Dreamcast's
|
||||
G2 bus. Drivers that want this will generally enable this on
|
||||
their own.
|
||||
|
||||
If in doubt, say N.
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -4,5 +4,6 @@
|
|||
|
||||
obj-$(CONFIG_SH_DMA_API) += dma-api.o dma-sysfs.o
|
||||
obj-$(CONFIG_SH_DMA) += dma-sh.o
|
||||
obj-$(CONFIG_SH_DREAMCAST) += dma-pvr2.o dma-g2.o
|
||||
obj-$(CONFIG_PVR2_DMA) += dma-pvr2.o
|
||||
obj-$(CONFIG_G2_DMA) += dma-g2.o
|
||||
obj-$(CONFIG_SH_DMABRG) += dmabrg.o
|
||||
|
|
|
@ -17,28 +17,16 @@
|
|||
#include <mach-dreamcast/mach/dma.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/io.h>
|
||||
#include "dma-sh.h"
|
||||
#include <asm/dma-sh.h>
|
||||
|
||||
static int dmte_irq_map[] = {
|
||||
DMTE0_IRQ,
|
||||
DMTE1_IRQ,
|
||||
DMTE2_IRQ,
|
||||
DMTE3_IRQ,
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
DMTE4_IRQ,
|
||||
DMTE5_IRQ,
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
DMTE6_IRQ,
|
||||
DMTE7_IRQ,
|
||||
#if defined(DMAE1_IRQ)
|
||||
#define NR_DMAE 2
|
||||
#else
|
||||
#define NR_DMAE 1
|
||||
#endif
|
||||
|
||||
static const char *dmae_name[] = {
|
||||
"DMAC Address Error0", "DMAC Address Error1"
|
||||
};
|
||||
|
||||
static inline unsigned int get_dmte_irq(unsigned int chan)
|
||||
|
@ -46,7 +34,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
|
|||
unsigned int irq = 0;
|
||||
if (chan < ARRAY_SIZE(dmte_irq_map))
|
||||
irq = dmte_irq_map[chan];
|
||||
|
||||
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
|
||||
if (irq > DMTE6_IRQ)
|
||||
return DMTE6_IRQ;
|
||||
return DMTE0_IRQ;
|
||||
#else
|
||||
return irq;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -59,7 +54,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
|
|||
*/
|
||||
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
|
||||
{
|
||||
u32 chcr = ctrl_inl(CHCR[chan->chan]);
|
||||
u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
|
||||
|
||||
return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
|
||||
}
|
||||
|
@ -75,13 +70,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
|
|||
struct dma_channel *chan = dev_id;
|
||||
u32 chcr;
|
||||
|
||||
chcr = ctrl_inl(CHCR[chan->chan]);
|
||||
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
|
||||
|
||||
if (!(chcr & CHCR_TE))
|
||||
return IRQ_NONE;
|
||||
|
||||
chcr &= ~(CHCR_IE | CHCR_DE);
|
||||
ctrl_outl(chcr, CHCR[chan->chan]);
|
||||
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
|
||||
|
||||
wake_up(&chan->wait_queue);
|
||||
|
||||
|
@ -94,7 +89,12 @@ static int sh_dmac_request_dma(struct dma_channel *chan)
|
|||
return 0;
|
||||
|
||||
return request_irq(get_dmte_irq(chan->chan), dma_tei,
|
||||
IRQF_DISABLED, chan->dev_id, chan);
|
||||
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
|
||||
IRQF_SHARED,
|
||||
#else
|
||||
IRQF_DISABLED,
|
||||
#endif
|
||||
chan->dev_id, chan);
|
||||
}
|
||||
|
||||
static void sh_dmac_free_dma(struct dma_channel *chan)
|
||||
|
@ -115,7 +115,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
|
|||
chan->flags &= ~DMA_TEI_CAPABLE;
|
||||
}
|
||||
|
||||
ctrl_outl(chcr, CHCR[chan->chan]);
|
||||
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
|
||||
|
||||
chan->flags |= DMA_CONFIGURED;
|
||||
return 0;
|
||||
|
@ -126,13 +126,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
|
|||
int irq;
|
||||
u32 chcr;
|
||||
|
||||
chcr = ctrl_inl(CHCR[chan->chan]);
|
||||
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
|
||||
chcr |= CHCR_DE;
|
||||
|
||||
if (chan->flags & DMA_TEI_CAPABLE)
|
||||
chcr |= CHCR_IE;
|
||||
|
||||
ctrl_outl(chcr, CHCR[chan->chan]);
|
||||
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
|
||||
|
||||
if (chan->flags & DMA_TEI_CAPABLE) {
|
||||
irq = get_dmte_irq(chan->chan);
|
||||
|
@ -150,9 +150,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
|
|||
disable_irq(irq);
|
||||
}
|
||||
|
||||
chcr = ctrl_inl(CHCR[chan->chan]);
|
||||
chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
|
||||
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
|
||||
ctrl_outl(chcr, CHCR[chan->chan]);
|
||||
ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
|
||||
}
|
||||
|
||||
static int sh_dmac_xfer_dma(struct dma_channel *chan)
|
||||
|
@ -183,12 +183,13 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
|
|||
*/
|
||||
if (chan->sar || (mach_is_dreamcast() &&
|
||||
chan->chan == PVR2_CASCADE_CHAN))
|
||||
ctrl_outl(chan->sar, SAR[chan->chan]);
|
||||
ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
|
||||
if (chan->dar || (mach_is_dreamcast() &&
|
||||
chan->chan == PVR2_CASCADE_CHAN))
|
||||
ctrl_outl(chan->dar, DAR[chan->chan]);
|
||||
ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
|
||||
|
||||
ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
|
||||
ctrl_outl(chan->count >> calc_xmit_shift(chan),
|
||||
(dma_base_addr[chan->chan] + TCR));
|
||||
|
||||
sh_dmac_enable_dma(chan);
|
||||
|
||||
|
@ -197,36 +198,26 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
|
|||
|
||||
static int sh_dmac_get_dma_residue(struct dma_channel *chan)
|
||||
{
|
||||
if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
|
||||
if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
|
||||
return 0;
|
||||
|
||||
return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
|
||||
return ctrl_inl(dma_base_addr[chan->chan] + TCR)
|
||||
<< calc_xmit_shift(chan);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
#define dmaor_read_reg() ctrl_inw(DMAOR)
|
||||
#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
|
||||
#else
|
||||
#define dmaor_read_reg() ctrl_inl(DMAOR)
|
||||
#define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
|
||||
#endif
|
||||
|
||||
static inline int dmaor_reset(void)
|
||||
static inline int dmaor_reset(int no)
|
||||
{
|
||||
unsigned long dmaor = dmaor_read_reg();
|
||||
unsigned long dmaor = dmaor_read_reg(no);
|
||||
|
||||
/* Try to clear the error flags first, incase they are set */
|
||||
dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
|
||||
dmaor_write_reg(dmaor);
|
||||
dmaor_write_reg(no, dmaor);
|
||||
|
||||
dmaor |= DMAOR_INIT;
|
||||
dmaor_write_reg(dmaor);
|
||||
dmaor_write_reg(no, dmaor);
|
||||
|
||||
/* See if we got an error again */
|
||||
if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
|
||||
if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
|
||||
printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -237,10 +228,33 @@ static inline int dmaor_reset(void)
|
|||
#if defined(CONFIG_CPU_SH4)
|
||||
static irqreturn_t dma_err(int irq, void *dummy)
|
||||
{
|
||||
dmaor_reset();
|
||||
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
|
||||
int cnt = 0;
|
||||
switch (irq) {
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
||||
case DMTE6_IRQ:
|
||||
cnt++;
|
||||
#endif
|
||||
case DMTE0_IRQ:
|
||||
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
|
||||
disable_irq(irq);
|
||||
/* DMA multi and error IRQ */
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
default:
|
||||
return IRQ_NONE;
|
||||
}
|
||||
#else
|
||||
dmaor_reset(0);
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
dmaor_reset(1);
|
||||
#endif
|
||||
disable_irq(irq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -259,24 +273,59 @@ static struct dma_info sh_dmac_info = {
|
|||
.flags = DMAC_CHANNELS_TEI_CAPABLE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
static unsigned int get_dma_error_irq(int n)
|
||||
{
|
||||
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
|
||||
return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
|
||||
#else
|
||||
return (n == 0) ? DMAE0_IRQ :
|
||||
#if defined(DMAE1_IRQ)
|
||||
DMAE1_IRQ;
|
||||
#else
|
||||
-1;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
static int __init sh_dmac_init(void)
|
||||
{
|
||||
struct dma_info *info = &sh_dmac_info;
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
|
||||
if (unlikely(i < 0))
|
||||
return i;
|
||||
int n;
|
||||
|
||||
for (n = 0; n < NR_DMAE; n++) {
|
||||
i = request_irq(get_dma_error_irq(n), dma_err,
|
||||
#if defined(CONFIG_SH_DMA_IRQ_MULTI)
|
||||
IRQF_SHARED,
|
||||
#else
|
||||
IRQF_DISABLED,
|
||||
#endif
|
||||
dmae_name[n], (void *)dmae_name[n]);
|
||||
if (unlikely(i < 0)) {
|
||||
printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
|
||||
return i;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_CPU_SH4 */
|
||||
|
||||
/*
|
||||
* Initialize DMAOR, and clean up any error flags that may have
|
||||
* been set.
|
||||
*/
|
||||
i = dmaor_reset();
|
||||
i = dmaor_reset(0);
|
||||
if (unlikely(i != 0))
|
||||
return i;
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
i = dmaor_reset(1);
|
||||
if (unlikely(i != 0))
|
||||
return i;
|
||||
#endif
|
||||
|
||||
return register_dmac(info);
|
||||
}
|
||||
|
@ -284,8 +333,12 @@ static int __init sh_dmac_init(void)
|
|||
static void __exit sh_dmac_exit(void)
|
||||
{
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
free_irq(DMAE_IRQ, 0);
|
||||
#endif
|
||||
int n;
|
||||
|
||||
for (n = 0; n < NR_DMAE; n++) {
|
||||
free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
|
||||
}
|
||||
#endif /* CONFIG_CPU_SH4 */
|
||||
unregister_dmac(&sh_dmac_info);
|
||||
}
|
||||
|
||||
|
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* arch/sh/drivers/dma/dma-sh.h
|
||||
*
|
||||
* Copyright (C) 2000 Takashi YOSHII
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __DMA_SH_H
|
||||
#define __DMA_SH_H
|
||||
|
||||
#include <cpu/dma.h>
|
||||
|
||||
/* Definitions for the SuperH DMAC */
|
||||
#define REQ_L 0x00000000
|
||||
#define REQ_E 0x00080000
|
||||
#define RACK_H 0x00000000
|
||||
#define RACK_L 0x00040000
|
||||
#define ACK_R 0x00000000
|
||||
#define ACK_W 0x00020000
|
||||
#define ACK_H 0x00000000
|
||||
#define ACK_L 0x00010000
|
||||
#define DM_INC 0x00004000
|
||||
#define DM_DEC 0x00008000
|
||||
#define SM_INC 0x00001000
|
||||
#define SM_DEC 0x00002000
|
||||
#define RS_IN 0x00000200
|
||||
#define RS_OUT 0x00000300
|
||||
#define TS_BLK 0x00000040
|
||||
#define TM_BUR 0x00000020
|
||||
#define CHCR_DE 0x00000001
|
||||
#define CHCR_TE 0x00000002
|
||||
#define CHCR_IE 0x00000004
|
||||
|
||||
/* DMAOR definitions */
|
||||
#define DMAOR_AE 0x00000004
|
||||
#define DMAOR_NMIF 0x00000002
|
||||
#define DMAOR_DME 0x00000001
|
||||
|
||||
/*
|
||||
* Define the default configuration for dual address memory-memory transfer.
|
||||
* The 0x400 value represents auto-request, external->external.
|
||||
*/
|
||||
#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
|
||||
|
||||
#define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
|
||||
|
||||
/*
|
||||
* Subtypes that have fewer channels than this simply need to change
|
||||
* CONFIG_NR_ONCHIP_DMA_CHANNELS. Likewise, subtypes with a larger number
|
||||
* of channels should expand on this.
|
||||
*
|
||||
* For most subtypes we can easily figure these values out with some
|
||||
* basic calculation, unfortunately on other subtypes these are more
|
||||
* scattered, so we just leave it unrolled for simplicity.
|
||||
*/
|
||||
#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
|
||||
SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30, \
|
||||
SH_DMAC_BASE + 0x50, SH_DMAC_BASE + 0x60})
|
||||
#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
|
||||
SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34, \
|
||||
SH_DMAC_BASE + 0x54, SH_DMAC_BASE + 0x64})
|
||||
#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
|
||||
SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38, \
|
||||
SH_DMAC_BASE + 0x58, SH_DMAC_BASE + 0x68})
|
||||
#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
|
||||
SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c, \
|
||||
SH_DMAC_BASE + 0x5c, SH_DMAC_BASE + 0x6c})
|
||||
|
||||
#define DMAOR (SH_DMAC_BASE + 0x40)
|
||||
|
||||
#endif /* __DMA_SH_H */
|
||||
|
|
@ -127,8 +127,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
|
|||
pci_write_reg(word, SH4_PCILSR0);
|
||||
pci_write_reg(0x00000001, SH4_PCILSR1);
|
||||
/* Set the values on window 0 PCI config registers */
|
||||
word = (CONFIG_MEMORY_SIZE > 0x08000000) ? 0x10000000 : 0x08000000;
|
||||
pci_write_reg(word | 0xa0000000, SH4_PCILAR0);
|
||||
word = CONFIG_MEMORY_START | (CONFIG_MEMORY_SIZE - 0x01000000);
|
||||
pci_write_reg(word, SH4_PCILAR0);
|
||||
pci_write_reg(word, SH7780_PCIMBAR0);
|
||||
/* Set the values on window 1 PCI config registers */
|
||||
pci_write_reg(0x00000000, SH4_PCILAR1);
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
/* Returns the physical address of a PnSEG (n=1,2) address */
|
||||
#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
|
||||
|
||||
#ifdef CONFIG_29BIT
|
||||
#if defined(CONFIG_29BIT) || defined(CONFIG_PMB_FIXED)
|
||||
/*
|
||||
* Map an address to a certain privileged segment
|
||||
*/
|
||||
|
@ -43,7 +43,7 @@
|
|||
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
|
||||
#define P4SEGADDR(a) \
|
||||
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
|
||||
#endif /* 29BIT */
|
||||
#endif /* 29BIT || PMB_FIXED */
|
||||
#endif /* P1SEG */
|
||||
|
||||
/* Check if an address can be reached in 29 bits */
|
||||
|
|
|
@ -11,7 +11,7 @@ static inline void atomic_add(int i, atomic_t *v)
|
|||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
*(long *)v += i;
|
||||
v->counter += i;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
@ -20,7 +20,7 @@ static inline void atomic_sub(int i, atomic_t *v)
|
|||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
*(long *)v -= i;
|
||||
v->counter -= i;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
@ -29,9 +29,9 @@ static inline int atomic_add_return(int i, atomic_t *v)
|
|||
unsigned long temp, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
temp = *(long *)v;
|
||||
temp = v->counter;
|
||||
temp += i;
|
||||
*(long *)v = temp;
|
||||
v->counter = temp;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return temp;
|
||||
|
@ -42,9 +42,9 @@ static inline int atomic_sub_return(int i, atomic_t *v)
|
|||
unsigned long temp, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
temp = *(long *)v;
|
||||
temp = v->counter;
|
||||
temp -= i;
|
||||
*(long *)v = temp;
|
||||
v->counter = temp;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return temp;
|
||||
|
@ -55,7 +55,7 @@ static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
|
|||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
*(long *)v &= ~mask;
|
||||
v->counter &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
@ -64,7 +64,7 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
|
|||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
*(long *)v |= mask;
|
||||
v->counter |= mask;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef __ASM_SH_BITOPS_LLSC_H
|
||||
#define __ASM_SH_BITOPS_LLSC_H
|
||||
|
||||
static inline void set_bit(int nr, volatile void * addr)
|
||||
static inline void set_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
|
@ -13,16 +13,16 @@ static inline void set_bit(int nr, volatile void * addr)
|
|||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! set_bit \n\t"
|
||||
"or %3, %0 \n\t"
|
||||
"or %2, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"bf 1b \n\t"
|
||||
: "=&z" (tmp), "=r" (a)
|
||||
: "1" (a), "r" (mask)
|
||||
: "=&z" (tmp)
|
||||
: "r" (a), "r" (mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void clear_bit(int nr, volatile void * addr)
|
||||
static inline void clear_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
|
@ -34,16 +34,16 @@ static inline void clear_bit(int nr, volatile void * addr)
|
|||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! clear_bit \n\t"
|
||||
"and %3, %0 \n\t"
|
||||
"and %2, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"bf 1b \n\t"
|
||||
: "=&z" (tmp), "=r" (a)
|
||||
: "1" (a), "r" (~mask)
|
||||
: "=&z" (tmp)
|
||||
: "r" (a), "r" (~mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void change_bit(int nr, volatile void * addr)
|
||||
static inline void change_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask;
|
||||
volatile unsigned int *a = addr;
|
||||
|
@ -55,86 +55,86 @@ static inline void change_bit(int nr, volatile void * addr)
|
|||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! change_bit \n\t"
|
||||
"xor %2, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"bf 1b \n\t"
|
||||
: "=&z" (tmp)
|
||||
: "r" (a), "r" (mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline int test_and_set_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%2, %0 ! test_and_set_bit \n\t"
|
||||
"mov %0, %1 \n\t"
|
||||
"or %3, %0 \n\t"
|
||||
"movco.l %0, @%2 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"and %3, %1 \n\t"
|
||||
: "=&z" (tmp), "=&r" (retval)
|
||||
: "r" (a), "r" (mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
return retval != 0;
|
||||
}
|
||||
|
||||
static inline int test_and_clear_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%2, %0 ! test_and_clear_bit \n\t"
|
||||
"mov %0, %1 \n\t"
|
||||
"and %4, %0 \n\t"
|
||||
"movco.l %0, @%2 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"and %3, %1 \n\t"
|
||||
"synco \n\t"
|
||||
: "=&z" (tmp), "=&r" (retval)
|
||||
: "r" (a), "r" (mask), "r" (~mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
return retval != 0;
|
||||
}
|
||||
|
||||
static inline int test_and_change_bit(int nr, volatile void *addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%2, %0 ! test_and_change_bit \n\t"
|
||||
"mov %0, %1 \n\t"
|
||||
"xor %3, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"movco.l %0, @%2 \n\t"
|
||||
"bf 1b \n\t"
|
||||
: "=&z" (tmp), "=r" (a)
|
||||
: "1" (a), "r" (mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline int test_and_set_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! test_and_set_bit \n\t"
|
||||
"mov %0, %2 \n\t"
|
||||
"or %4, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"and %4, %2 \n\t"
|
||||
: "=&z" (tmp), "=r" (a), "=&r" (retval)
|
||||
: "1" (a), "r" (mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
return retval != 0;
|
||||
}
|
||||
|
||||
static inline int test_and_clear_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! test_and_clear_bit \n\t"
|
||||
"mov %0, %2 \n\t"
|
||||
"and %5, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"and %4, %2 \n\t"
|
||||
"and %3, %1 \n\t"
|
||||
"synco \n\t"
|
||||
: "=&z" (tmp), "=r" (a), "=&r" (retval)
|
||||
: "1" (a), "r" (mask), "r" (~mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
return retval != 0;
|
||||
}
|
||||
|
||||
static inline int test_and_change_bit(int nr, volatile void * addr)
|
||||
{
|
||||
int mask, retval;
|
||||
volatile unsigned int *a = addr;
|
||||
unsigned long tmp;
|
||||
|
||||
a += nr >> 5;
|
||||
mask = 1 << (nr & 0x1f);
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! test_and_change_bit \n\t"
|
||||
"mov %0, %2 \n\t"
|
||||
"xor %4, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"and %4, %2 \n\t"
|
||||
"synco \n\t"
|
||||
: "=&z" (tmp), "=r" (a), "=&r" (retval)
|
||||
: "1" (a), "r" (mask)
|
||||
: "=&z" (tmp), "=&r" (retval)
|
||||
: "r" (a), "r" (mask)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
|
|
|
@ -15,6 +15,7 @@ struct clk_ops {
|
|||
void (*disable)(struct clk *clk);
|
||||
void (*recalc)(struct clk *clk);
|
||||
int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
|
||||
int (*set_parent)(struct clk *clk, struct clk *parent);
|
||||
long (*round_rate)(struct clk *clk, unsigned long rate);
|
||||
};
|
||||
|
||||
|
|
|
@ -8,14 +8,14 @@ static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
|
|||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! xchg_u32 \n\t"
|
||||
"mov %0, %2 \n\t"
|
||||
"mov %4, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"movli.l @%2, %0 ! xchg_u32 \n\t"
|
||||
"mov %0, %1 \n\t"
|
||||
"mov %3, %0 \n\t"
|
||||
"movco.l %0, @%2 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"synco \n\t"
|
||||
: "=&z"(tmp), "=r" (m), "=&r" (retval)
|
||||
: "1" (m), "r" (val)
|
||||
: "=&z"(tmp), "=&r" (retval)
|
||||
: "r" (m), "r" (val)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
|
@ -29,14 +29,14 @@ static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
|
|||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! xchg_u8 \n\t"
|
||||
"mov %0, %2 \n\t"
|
||||
"mov %4, %0 \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"movli.l @%2, %0 ! xchg_u8 \n\t"
|
||||
"mov %0, %1 \n\t"
|
||||
"mov %3, %0 \n\t"
|
||||
"movco.l %0, @%2 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"synco \n\t"
|
||||
: "=&z"(tmp), "=r" (m), "=&r" (retval)
|
||||
: "1" (m), "r" (val & 0xff)
|
||||
: "=&z"(tmp), "=&r" (retval)
|
||||
: "r" (m), "r" (val & 0xff)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
|
@ -51,17 +51,17 @@ __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
|
|||
|
||||
__asm__ __volatile__ (
|
||||
"1: \n\t"
|
||||
"movli.l @%1, %0 ! __cmpxchg_u32 \n\t"
|
||||
"mov %0, %2 \n\t"
|
||||
"cmp/eq %2, %4 \n\t"
|
||||
"movli.l @%2, %0 ! __cmpxchg_u32 \n\t"
|
||||
"mov %0, %1 \n\t"
|
||||
"cmp/eq %1, %3 \n\t"
|
||||
"bf 2f \n\t"
|
||||
"mov %5, %0 \n\t"
|
||||
"mov %3, %0 \n\t"
|
||||
"2: \n\t"
|
||||
"movco.l %0, @%1 \n\t"
|
||||
"movco.l %0, @%2 \n\t"
|
||||
"bf 1b \n\t"
|
||||
"synco \n\t"
|
||||
: "=&z" (tmp), "=r" (m), "=&r" (retval)
|
||||
: "1" (m), "r" (old), "r" (new)
|
||||
: "=&z" (tmp), "=&r" (retval)
|
||||
: "r" (m), "r" (old), "r" (new)
|
||||
: "t", "memory"
|
||||
);
|
||||
|
||||
|
|
|
@ -21,5 +21,6 @@
|
|||
#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
|
||||
#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
|
||||
#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
|
||||
#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
|
||||
|
||||
#endif /* __ASM_SH_CPU_FEATURES_H */
|
||||
|
|
118
arch/sh/include/asm/dma-sh.h
Normal file
118
arch/sh/include/asm/dma-sh.h
Normal file
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* arch/sh/include/asm/dma-sh.h
|
||||
*
|
||||
* Copyright (C) 2000 Takashi YOSHII
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __DMA_SH_H
|
||||
#define __DMA_SH_H
|
||||
|
||||
#include <asm/dma.h>
|
||||
#include <cpu/dma.h>
|
||||
|
||||
/* DMAOR contorl: The DMAOR access size is different by CPU.*/
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define dmaor_read_reg(n) \
|
||||
(n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
|
||||
: ctrl_inw(SH_DMAC_BASE0 + DMAOR))
|
||||
#define dmaor_write_reg(n, data) \
|
||||
(n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
|
||||
: ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
|
||||
#else /* Other CPU */
|
||||
#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
|
||||
#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
|
||||
#endif
|
||||
|
||||
static int dmte_irq_map[] __maybe_unused = {
|
||||
#if (MAX_DMA_CHANNELS >= 4)
|
||||
DMTE0_IRQ,
|
||||
DMTE0_IRQ + 1,
|
||||
DMTE0_IRQ + 2,
|
||||
DMTE0_IRQ + 3,
|
||||
#endif
|
||||
#if (MAX_DMA_CHANNELS >= 6)
|
||||
DMTE4_IRQ,
|
||||
DMTE4_IRQ + 1,
|
||||
#endif
|
||||
#if (MAX_DMA_CHANNELS >= 8)
|
||||
DMTE6_IRQ,
|
||||
DMTE6_IRQ + 1,
|
||||
#endif
|
||||
#if (MAX_DMA_CHANNELS >= 12)
|
||||
DMTE8_IRQ,
|
||||
DMTE9_IRQ,
|
||||
DMTE10_IRQ,
|
||||
DMTE11_IRQ,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Definitions for the SuperH DMAC */
|
||||
#define REQ_L 0x00000000
|
||||
#define REQ_E 0x00080000
|
||||
#define RACK_H 0x00000000
|
||||
#define RACK_L 0x00040000
|
||||
#define ACK_R 0x00000000
|
||||
#define ACK_W 0x00020000
|
||||
#define ACK_H 0x00000000
|
||||
#define ACK_L 0x00010000
|
||||
#define DM_INC 0x00004000
|
||||
#define DM_DEC 0x00008000
|
||||
#define SM_INC 0x00001000
|
||||
#define SM_DEC 0x00002000
|
||||
#define RS_IN 0x00000200
|
||||
#define RS_OUT 0x00000300
|
||||
#define TS_BLK 0x00000040
|
||||
#define TM_BUR 0x00000020
|
||||
#define CHCR_DE 0x00000001
|
||||
#define CHCR_TE 0x00000002
|
||||
#define CHCR_IE 0x00000004
|
||||
|
||||
/* DMAOR definitions */
|
||||
#define DMAOR_AE 0x00000004
|
||||
#define DMAOR_NMIF 0x00000002
|
||||
#define DMAOR_DME 0x00000001
|
||||
|
||||
/*
|
||||
* Define the default configuration for dual address memory-memory transfer.
|
||||
* The 0x400 value represents auto-request, external->external.
|
||||
*/
|
||||
#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
|
||||
|
||||
/* DMA base address */
|
||||
static u32 dma_base_addr[] __maybe_unused = {
|
||||
#if (MAX_DMA_CHANNELS >= 4)
|
||||
SH_DMAC_BASE0 + 0x00, /* channel 0 */
|
||||
SH_DMAC_BASE0 + 0x10,
|
||||
SH_DMAC_BASE0 + 0x20,
|
||||
SH_DMAC_BASE0 + 0x30,
|
||||
#endif
|
||||
#if (MAX_DMA_CHANNELS >= 6)
|
||||
SH_DMAC_BASE0 + 0x50,
|
||||
SH_DMAC_BASE0 + 0x60,
|
||||
#endif
|
||||
#if (MAX_DMA_CHANNELS >= 8)
|
||||
SH_DMAC_BASE1 + 0x00,
|
||||
SH_DMAC_BASE1 + 0x10,
|
||||
#endif
|
||||
#if (MAX_DMA_CHANNELS >= 12)
|
||||
SH_DMAC_BASE1 + 0x20,
|
||||
SH_DMAC_BASE1 + 0x30,
|
||||
SH_DMAC_BASE1 + 0x50,
|
||||
SH_DMAC_BASE1 + 0x60, /* channel 11 */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* DMA register */
|
||||
#define SAR 0x00
|
||||
#define DAR 0x04
|
||||
#define TCR 0x08
|
||||
#define CHCR 0x0C
|
||||
#define DMAOR 0x40
|
||||
|
||||
#endif /* __DMA_SH_H */
|
|
@ -31,3 +31,8 @@
|
|||
#endif
|
||||
.endm
|
||||
|
||||
#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
|
||||
# define PREF(x) pref @x
|
||||
#else
|
||||
# define PREF(x) nop
|
||||
#endif
|
||||
|
|
|
@ -19,8 +19,42 @@
|
|||
#include <cpu/gpio.h>
|
||||
#endif
|
||||
|
||||
#define ARCH_NR_GPIOS 512
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
|
||||
static inline int gpio_get_value(unsigned gpio)
|
||||
{
|
||||
return __gpio_get_value(gpio);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value(unsigned gpio, int value)
|
||||
{
|
||||
__gpio_set_value(gpio, value);
|
||||
}
|
||||
|
||||
static inline int gpio_cansleep(unsigned gpio)
|
||||
{
|
||||
return __gpio_cansleep(gpio);
|
||||
}
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIOLIB */
|
||||
|
||||
typedef unsigned short pinmux_enum_t;
|
||||
typedef unsigned char pinmux_flag_t;
|
||||
typedef unsigned short pinmux_flag_t;
|
||||
|
||||
#define PINMUX_TYPE_NONE 0
|
||||
#define PINMUX_TYPE_FUNCTION 1
|
||||
|
@ -34,6 +68,11 @@ typedef unsigned char pinmux_flag_t;
|
|||
#define PINMUX_FLAG_WANT_PULLUP (1 << 3)
|
||||
#define PINMUX_FLAG_WANT_PULLDOWN (1 << 4)
|
||||
|
||||
#define PINMUX_FLAG_DBIT_SHIFT 5
|
||||
#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
|
||||
#define PINMUX_FLAG_DREG_SHIFT 10
|
||||
#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
|
||||
|
||||
struct pinmux_gpio {
|
||||
pinmux_enum_t enum_id;
|
||||
pinmux_flag_t flags;
|
||||
|
@ -54,7 +93,7 @@ struct pinmux_cfg_reg {
|
|||
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \
|
||||
|
||||
struct pinmux_data_reg {
|
||||
unsigned long reg, reg_width;
|
||||
unsigned long reg, reg_width, reg_shadow;
|
||||
pinmux_enum_t *enum_ids;
|
||||
};
|
||||
|
||||
|
@ -89,34 +128,9 @@ struct pinmux_info {
|
|||
unsigned int gpio_data_size;
|
||||
|
||||
unsigned long *gpio_in_use;
|
||||
struct gpio_chip chip;
|
||||
};
|
||||
|
||||
int register_pinmux(struct pinmux_info *pip);
|
||||
|
||||
int __gpio_request(unsigned gpio);
|
||||
static inline int gpio_request(unsigned gpio, const char *label)
|
||||
{
|
||||
return __gpio_request(gpio);
|
||||
}
|
||||
void gpio_free(unsigned gpio);
|
||||
int gpio_direction_input(unsigned gpio);
|
||||
int gpio_direction_output(unsigned gpio, int value);
|
||||
int gpio_get_value(unsigned gpio);
|
||||
void gpio_set_value(unsigned gpio, int value);
|
||||
|
||||
/* IRQ modes are unspported */
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned irq)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* __ASM_SH_GPIO_H */
|
||||
|
|
|
@ -242,7 +242,6 @@
|
|||
#include <asm/io_generic.h>
|
||||
|
||||
/* arch/sh/cchips/hd6446x/hd64461/setup.c */
|
||||
int hd64461_irq_demux(int irq);
|
||||
void hd64461_register_irq_demux(int irq,
|
||||
int (*demux) (int irq, void *dev), void *dev);
|
||||
void hd64461_unregister_irq_demux(int irq);
|
||||
|
|
|
@ -238,7 +238,7 @@ extern void onchip_unmap(unsigned long vaddr);
|
|||
static inline void __iomem *
|
||||
__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
|
||||
{
|
||||
#ifdef CONFIG_SUPERH32
|
||||
#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
|
||||
unsigned long last_addr = offset + size - 1;
|
||||
#endif
|
||||
void __iomem *ret;
|
||||
|
@ -247,7 +247,7 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
|
||||
/*
|
||||
* For P1 and P2 space this is trivial, as everything is already
|
||||
* mapped. Uncached access for P1 addresses are done through P2.
|
||||
|
|
|
@ -16,7 +16,7 @@ typedef u16 kprobe_opcode_t;
|
|||
? (MAX_STACK_SIZE) \
|
||||
: (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
|
||||
|
||||
#define regs_return_value(regs) ((regs)->regs[0])
|
||||
#define regs_return_value(_regs) ((_regs)->regs[0])
|
||||
#define flush_insn_slot(p) do { } while (0)
|
||||
#define kretprobe_blacklist_size 0
|
||||
|
||||
|
|
|
@ -19,13 +19,18 @@
|
|||
* (a) TLB cache version (or round, cycle whatever expression you like)
|
||||
* (b) ASID (Address Space IDentifier)
|
||||
*/
|
||||
#ifdef CONFIG_CPU_HAS_PTEAEX
|
||||
#define MMU_CONTEXT_ASID_MASK 0x0000ffff
|
||||
#else
|
||||
#define MMU_CONTEXT_ASID_MASK 0x000000ff
|
||||
#define MMU_CONTEXT_VERSION_MASK 0xffffff00
|
||||
#define MMU_CONTEXT_FIRST_VERSION 0x00000100
|
||||
#define NO_CONTEXT 0UL
|
||||
#endif
|
||||
|
||||
/* ASID is 8-bit value, so it can't be 0x100 */
|
||||
#define MMU_NO_ASID 0x100
|
||||
#define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK)
|
||||
#define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1)
|
||||
|
||||
/* Impossible ASID value, to differentiate from NO_CONTEXT. */
|
||||
#define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION
|
||||
#define NO_CONTEXT 0UL
|
||||
|
||||
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
|
||||
|
||||
|
|
|
@ -10,6 +10,17 @@ static inline void destroy_context(struct mm_struct *mm)
|
|||
/* Do nothing */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PTEAEX
|
||||
static inline void set_asid(unsigned long asid)
|
||||
{
|
||||
__raw_writel(asid, MMU_PTEAEX);
|
||||
}
|
||||
|
||||
static inline unsigned long get_asid(void)
|
||||
{
|
||||
return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK;
|
||||
}
|
||||
#else
|
||||
static inline void set_asid(unsigned long asid)
|
||||
{
|
||||
unsigned long __dummy;
|
||||
|
@ -33,6 +44,7 @@ static inline unsigned long get_asid(void)
|
|||
asid &= MMU_CONTEXT_ASID_MASK;
|
||||
return asid;
|
||||
}
|
||||
#endif /* CONFIG_CPU_HAS_PTEAEX */
|
||||
|
||||
/* MMU_TTB is used for optimizing the fault handling. */
|
||||
static inline void set_TTB(pgd_t *pgd)
|
||||
|
|
|
@ -129,7 +129,12 @@ typedef struct page *pgtable_t;
|
|||
* is not visible (it is part of the PMB mapping) and so needs to be
|
||||
* added or subtracted as required.
|
||||
*/
|
||||
#ifdef CONFIG_32BIT
|
||||
#if defined(CONFIG_PMB_FIXED)
|
||||
/* phys = virt - PAGE_OFFSET - (__MEMORY_START & 0xe0000000) */
|
||||
#define PMB_OFFSET (PAGE_OFFSET - PXSEG(__MEMORY_START))
|
||||
#define __pa(x) ((unsigned long)(x) - PMB_OFFSET)
|
||||
#define __va(x) ((void *)((unsigned long)(x) + PMB_OFFSET))
|
||||
#elif defined(CONFIG_32BIT)
|
||||
#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
|
||||
#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
|
||||
#else
|
||||
|
|
|
@ -31,7 +31,7 @@ enum cpu_type {
|
|||
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
|
||||
|
||||
/* SH-4A types */
|
||||
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
|
||||
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
|
||||
CPU_SH7723, CPU_SHX3,
|
||||
|
||||
/* SH4AL-DSP types */
|
||||
|
|
|
@ -108,12 +108,12 @@ extern int ubc_usercnt;
|
|||
/*
|
||||
* Do necessary setup to start up a newly executed thread.
|
||||
*/
|
||||
#define start_thread(regs, new_pc, new_sp) \
|
||||
#define start_thread(_regs, new_pc, new_sp) \
|
||||
set_fs(USER_DS); \
|
||||
regs->pr = 0; \
|
||||
regs->sr = SR_FD; /* User mode. */ \
|
||||
regs->pc = new_pc; \
|
||||
regs->regs[15] = new_sp
|
||||
_regs->pr = 0; \
|
||||
_regs->sr = SR_FD; /* User mode. */ \
|
||||
_regs->pc = new_pc; \
|
||||
_regs->regs[15] = new_sp
|
||||
|
||||
/* Forward declaration, a strange C thing */
|
||||
struct task_struct;
|
||||
|
@ -189,10 +189,9 @@ extern unsigned long get_wchan(struct task_struct *p);
|
|||
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
|
||||
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
|
||||
|
||||
#define user_stack_pointer(regs) ((regs)->regs[15])
|
||||
#define user_stack_pointer(_regs) ((_regs)->regs[15])
|
||||
|
||||
#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH3) || \
|
||||
defined(CONFIG_CPU_SH4)
|
||||
#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
|
||||
#define PREFETCH_STRIDE L1_CACHE_BYTES
|
||||
#define ARCH_HAS_PREFETCH
|
||||
#define ARCH_HAS_PREFETCHW
|
||||
|
|
|
@ -145,13 +145,13 @@ struct thread_struct {
|
|||
*/
|
||||
#define SR_USER (SR_MMU | SR_FD)
|
||||
|
||||
#define start_thread(regs, new_pc, new_sp) \
|
||||
#define start_thread(_regs, new_pc, new_sp) \
|
||||
set_fs(USER_DS); \
|
||||
regs->sr = SR_USER; /* User mode. */ \
|
||||
regs->pc = new_pc - 4; /* Compensate syscall exit */ \
|
||||
regs->pc |= 1; /* Set SHmedia ! */ \
|
||||
regs->regs[18] = 0; \
|
||||
regs->regs[15] = new_sp
|
||||
_regs->sr = SR_USER; /* User mode. */ \
|
||||
_regs->pc = new_pc - 4; /* Compensate syscall exit */ \
|
||||
_regs->pc |= 1; /* Set SHmedia ! */ \
|
||||
_regs->regs[18] = 0; \
|
||||
_regs->regs[15] = new_sp
|
||||
|
||||
/* Forward declaration, a strange C thing */
|
||||
struct task_struct;
|
||||
|
@ -226,7 +226,7 @@ extern unsigned long get_wchan(struct task_struct *p);
|
|||
#define KSTK_EIP(tsk) ((tsk)->thread.pc)
|
||||
#define KSTK_ESP(tsk) ((tsk)->thread.sp)
|
||||
|
||||
#define user_stack_pointer(regs) ((regs)->regs[15])
|
||||
#define user_stack_pointer(_regs) ((_regs)->regs[15])
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_SH_PROCESSOR_64_H */
|
||||
|
|
|
@ -122,14 +122,12 @@ extern void user_disable_single_step(struct task_struct *);
|
|||
#ifdef CONFIG_SH_DSP
|
||||
#define task_pt_regs(task) \
|
||||
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
|
||||
- sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
|
||||
- sizeof(struct pt_dspregs)) - 1)
|
||||
#define task_pt_dspregs(task) \
|
||||
((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE \
|
||||
- sizeof(unsigned long)) - 1)
|
||||
((struct pt_dspregs *) (task_stack_page(task) + THREAD_SIZE) - 1)
|
||||
#else
|
||||
#define task_pt_regs(task) \
|
||||
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
|
||||
- sizeof(unsigned long)) - 1)
|
||||
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE) - 1)
|
||||
#endif
|
||||
|
||||
static inline unsigned long profile_pc(struct pt_regs *regs)
|
||||
|
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
#include <asm-generic/sections.h>
|
||||
|
||||
extern void __nosave_begin, __nosave_end;
|
||||
extern long __machvec_start, __machvec_end;
|
||||
extern char __uncached_start, __uncached_end;
|
||||
extern char _ebss[];
|
||||
|
|
22
arch/sh/include/asm/suspend.h
Normal file
22
arch/sh/include/asm/suspend.h
Normal file
|
@ -0,0 +1,22 @@
|
|||
#ifndef _ASM_SH_SUSPEND_H
|
||||
#define _ASM_SH_SUSPEND_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline int arch_prepare_suspend(void) { return 0; }
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
struct swsusp_arch_regs {
|
||||
struct pt_regs user_regs;
|
||||
unsigned long bank1_regs[8];
|
||||
};
|
||||
#endif
|
||||
|
||||
/* flags passed to assembly suspend code */
|
||||
#define SUSP_SH_SLEEP (1 << 0) /* Regular sleep mode */
|
||||
#define SUSP_SH_STANDBY (1 << 1) /* SH-Mobile Software standby mode */
|
||||
#define SUSP_SH_RSTANDBY (1 << 2) /* SH-Mobile R-standby mode */
|
||||
#define SUSP_SH_USTANDBY (1 << 3) /* SH-Mobile U-standby mode */
|
||||
#define SUSP_SH_SF (1 << 4) /* Enable self-refresh */
|
||||
|
||||
#endif /* _ASM_SH_SUSPEND_H */
|
|
@ -9,7 +9,6 @@ struct sys_timer_ops {
|
|||
int (*init)(void);
|
||||
int (*start)(void);
|
||||
int (*stop)(void);
|
||||
cycle_t (*read)(void);
|
||||
#ifndef CONFIG_GENERIC_TIME
|
||||
unsigned long (*get_offset)(void);
|
||||
#endif
|
||||
|
@ -39,6 +38,7 @@ struct sys_timer *get_sys_timer(void);
|
|||
|
||||
/* arch/sh/kernel/time.c */
|
||||
void handle_timer_tick(void);
|
||||
extern unsigned long sh_hpt_frequency;
|
||||
|
||||
extern struct clocksource clocksource_sh;
|
||||
|
||||
#endif /* __ASM_SH_TIMER_H */
|
||||
|
|
|
@ -6,22 +6,106 @@
|
|||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/pagemap.h>
|
||||
|
||||
#define tlb_start_vma(tlb, vma) \
|
||||
flush_cache_range(vma, vma->vm_start, vma->vm_end)
|
||||
|
||||
#define tlb_end_vma(tlb, vma) \
|
||||
flush_tlb_range(vma, vma->vm_start, vma->vm_end)
|
||||
|
||||
#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
|
||||
#ifdef CONFIG_MMU
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
/*
|
||||
* Flush whole TLBs for MM
|
||||
* TLB handling. This allows us to remove pages from the page
|
||||
* tables, and efficiently handle the TLB issues.
|
||||
*/
|
||||
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
|
||||
struct mmu_gather {
|
||||
struct mm_struct *mm;
|
||||
unsigned int fullmm;
|
||||
unsigned long start, end;
|
||||
};
|
||||
|
||||
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
|
||||
|
||||
static inline void init_tlb_gather(struct mmu_gather *tlb)
|
||||
{
|
||||
tlb->start = TASK_SIZE;
|
||||
tlb->end = 0;
|
||||
|
||||
if (tlb->fullmm) {
|
||||
tlb->start = 0;
|
||||
tlb->end = TASK_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
static inline struct mmu_gather *
|
||||
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
|
||||
{
|
||||
struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
|
||||
|
||||
tlb->mm = mm;
|
||||
tlb->fullmm = full_mm_flush;
|
||||
|
||||
init_tlb_gather(tlb);
|
||||
|
||||
return tlb;
|
||||
}
|
||||
|
||||
static inline void
|
||||
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
|
||||
{
|
||||
if (tlb->fullmm)
|
||||
flush_tlb_mm(tlb->mm);
|
||||
|
||||
/* keep the page table cache within bounds */
|
||||
check_pgt_cache();
|
||||
|
||||
put_cpu_var(mmu_gathers);
|
||||
}
|
||||
|
||||
static inline void
|
||||
tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
|
||||
{
|
||||
if (tlb->start > address)
|
||||
tlb->start = address;
|
||||
if (tlb->end < address + PAGE_SIZE)
|
||||
tlb->end = address + PAGE_SIZE;
|
||||
}
|
||||
|
||||
/*
|
||||
* In the case of tlb vma handling, we can optimise these away in the
|
||||
* case where we're doing a full MM flush. When we're doing a munmap,
|
||||
* the vmas are adjusted to only cover the region to be torn down.
|
||||
*/
|
||||
static inline void
|
||||
tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
|
||||
{
|
||||
if (!tlb->fullmm)
|
||||
flush_cache_range(vma, vma->vm_start, vma->vm_end);
|
||||
}
|
||||
|
||||
static inline void
|
||||
tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
|
||||
{
|
||||
if (!tlb->fullmm && tlb->end) {
|
||||
flush_tlb_range(vma, tlb->start, tlb->end);
|
||||
init_tlb_gather(tlb);
|
||||
}
|
||||
}
|
||||
|
||||
#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
|
||||
#define pte_free_tlb(tlb, ptep) pte_free((tlb)->mm, ptep)
|
||||
#define pmd_free_tlb(tlb, pmdp) pmd_free((tlb)->mm, pmdp)
|
||||
#define pud_free_tlb(tlb, pudp) pud_free((tlb)->mm, pudp)
|
||||
|
||||
#define tlb_migrate_finish(mm) do { } while (0)
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
#define tlb_start_vma(tlb, vma) do { } while (0)
|
||||
#define tlb_end_vma(tlb, vma) do { } while (0)
|
||||
#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
|
||||
#define tlb_flush(tlb) do { } while (0)
|
||||
|
||||
#include <linux/pagemap.h>
|
||||
#include <asm-generic/tlb.h>
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_SH_TLB_H */
|
||||
|
|
|
@ -1,22 +1,17 @@
|
|||
#ifndef __ASM_CPU_SH3_DMA_H
|
||||
#define __ASM_CPU_SH3_DMA_H
|
||||
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
#define SH_DMAC_BASE 0xa4010020
|
||||
#else
|
||||
#define SH_DMAC_BASE 0xa4000020
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
#define SH_DMAC_BASE0 0xa4010020
|
||||
#else /* SH7705/06/07/09 */
|
||||
#define SH_DMAC_BASE0 0xa4000020
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#endif
|
||||
|
||||
/* Definitions for the SuperH DMAC */
|
||||
#define TM_BURST 0x00000020
|
||||
|
|
94
arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
Normal file
94
arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
Normal file
|
@ -0,0 +1,94 @@
|
|||
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
|
||||
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7722) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7730)
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
|
||||
#define SH_DMAC_BASE0 0xFE008020
|
||||
#define SH_DMARS_BASE 0xFE009000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7764)
|
||||
#define DMTE0_IRQ 34
|
||||
#define DMTE4_IRQ 44
|
||||
#define DMAE0_IRQ 38
|
||||
#define SH_DMAC_BASE0 0xFF608020
|
||||
#define SH_DMARS_BASE 0xFF609000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
#define DMTE0_IRQ 48 /* DMAC0A*/
|
||||
#define DMTE4_IRQ 40 /* DMAC0B */
|
||||
#define DMTE6_IRQ 42
|
||||
#define DMTE8_IRQ 76 /* DMAC1A */
|
||||
#define DMTE9_IRQ 77
|
||||
#define DMTE10_IRQ 72 /* DMAC1B */
|
||||
#define DMTE11_IRQ 73
|
||||
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
|
||||
#define DMAE1_IRQ 74 /* DMA Error IRQ*/
|
||||
#define SH_DMAC_BASE0 0xFE008020
|
||||
#define SH_DMAC_BASE1 0xFDC08020
|
||||
#define SH_DMARS_BASE 0xFDC09000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define DMTE0_IRQ 34
|
||||
#define DMTE4_IRQ 44
|
||||
#define DMTE6_IRQ 46
|
||||
#define DMTE8_IRQ 92
|
||||
#define DMTE9_IRQ 93
|
||||
#define DMTE10_IRQ 94
|
||||
#define DMTE11_IRQ 95
|
||||
#define DMAE0_IRQ 38 /* DMA Error IRQ */
|
||||
#define SH_DMAC_BASE0 0xFC808020
|
||||
#define SH_DMAC_BASE1 0xFC818020
|
||||
#define SH_DMARS_BASE 0xFC809000
|
||||
#else /* SH7785 */
|
||||
#define DMTE0_IRQ 33
|
||||
#define DMTE4_IRQ 37
|
||||
#define DMTE6_IRQ 52
|
||||
#define DMTE8_IRQ 54
|
||||
#define DMTE9_IRQ 55
|
||||
#define DMTE10_IRQ 56
|
||||
#define DMTE11_IRQ 57
|
||||
#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
|
||||
#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
|
||||
#define SH_DMAC_BASE0 0xFC808020
|
||||
#define SH_DMAC_BASE1 0xFCC08020
|
||||
#define SH_DMARS_BASE 0xFC809000
|
||||
#endif
|
||||
|
||||
#define REQ_HE 0x000000C0
|
||||
#define REQ_H 0x00000080
|
||||
#define REQ_LE 0x00000040
|
||||
#define TM_BURST 0x0000020
|
||||
#define TS_8 0x00000000
|
||||
#define TS_16 0x00000008
|
||||
#define TS_32 0x00000010
|
||||
#define TS_16BLK 0x00000018
|
||||
#define TS_32BLK 0x00100000
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*
|
||||
* Defaults to a 64-bit transfer size.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT,
|
||||
XMIT_SZ_16BIT,
|
||||
XMIT_SZ_32BIT,
|
||||
XMIT_SZ_128BIT,
|
||||
XMIT_SZ_256BIT,
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA count is defined as the number of bytes to transfer.
|
||||
*/
|
||||
static unsigned int ts_shift[] __maybe_unused = {
|
||||
[XMIT_SZ_8BIT] = 0,
|
||||
[XMIT_SZ_16BIT] = 1,
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
[XMIT_SZ_128BIT] = 4,
|
||||
[XMIT_SZ_256BIT] = 5,
|
||||
};
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
|
|
@ -1,39 +0,0 @@
|
|||
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
|
||||
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
|
||||
|
||||
#define REQ_HE 0x000000C0
|
||||
#define REQ_H 0x00000080
|
||||
#define REQ_LE 0x00000040
|
||||
#define TM_BURST 0x0000020
|
||||
#define TS_8 0x00000000
|
||||
#define TS_16 0x00000008
|
||||
#define TS_32 0x00000010
|
||||
#define TS_16BLK 0x00000018
|
||||
#define TS_32BLK 0x00100000
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*
|
||||
* Defaults to a 64-bit transfer size.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT,
|
||||
XMIT_SZ_16BIT,
|
||||
XMIT_SZ_32BIT,
|
||||
XMIT_SZ_128BIT,
|
||||
XMIT_SZ_256BIT,
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA count is defined as the number of bytes to transfer.
|
||||
*/
|
||||
static unsigned int ts_shift[] __maybe_unused = {
|
||||
[XMIT_SZ_8BIT] = 0,
|
||||
[XMIT_SZ_16BIT] = 1,
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
[XMIT_SZ_128BIT] = 4,
|
||||
[XMIT_SZ_256BIT] = 5,
|
||||
};
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
|
|
@ -1,31 +1,29 @@
|
|||
#ifndef __ASM_CPU_SH4_DMA_H
|
||||
#define __ASM_CPU_SH4_DMA_H
|
||||
|
||||
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
|
||||
|
||||
/* SH7751/7760/7780 DMA IRQ sources */
|
||||
#define DMTE0_IRQ 34
|
||||
#define DMTE1_IRQ 35
|
||||
#define DMTE2_IRQ 36
|
||||
#define DMTE3_IRQ 37
|
||||
#define DMTE4_IRQ 44
|
||||
#define DMTE5_IRQ 45
|
||||
#define DMTE6_IRQ 46
|
||||
#define DMTE7_IRQ 47
|
||||
#define DMAE_IRQ 38
|
||||
|
||||
#ifdef CONFIG_CPU_SH4A
|
||||
#define SH_DMAC_BASE 0xfc808020
|
||||
|
||||
#define DMAOR_INIT (DMAOR_DME)
|
||||
#define CHCR_TS_MASK 0x18
|
||||
#define CHCR_TS_SHIFT 3
|
||||
|
||||
#include <cpu/dma-sh7780.h>
|
||||
#else
|
||||
#define SH_DMAC_BASE 0xffa00000
|
||||
#include <cpu/dma-sh4a.h>
|
||||
#else /* CONFIG_CPU_SH4A */
|
||||
/*
|
||||
* SH7750/SH7751/SH7760
|
||||
*/
|
||||
#define DMTE0_IRQ 34
|
||||
#define DMTE4_IRQ 44
|
||||
#define DMTE6_IRQ 46
|
||||
#define DMAE0_IRQ 38
|
||||
|
||||
#define DMAOR_INIT (0x8000|DMAOR_DME)
|
||||
#define SH_DMAC_BASE0 0xffa00000
|
||||
#define SH_DMAC_BASE1 0xffa00070
|
||||
/* Definitions for the SuperH DMAC */
|
||||
#define TM_BURST 0x0000080
|
||||
#define TM_BURST 0x00000080
|
||||
#define TS_8 0x00000010
|
||||
#define TS_16 0x00000020
|
||||
#define TS_32 0x00000030
|
||||
|
|
|
@ -29,6 +29,10 @@
|
|||
#define FRQCR0 0xffc80000
|
||||
#define FRQCR1 0xffc80004
|
||||
#define FRQMR1 0xffc80014
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
#define FRQCR0 0xffc40000
|
||||
#define FRQCR1 0xffc40004
|
||||
#define FRQMR1 0xffc40014
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
#define FRQCR 0xffc00014
|
||||
#else
|
||||
|
|
|
@ -14,28 +14,35 @@
|
|||
#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
|
||||
#define MMU_TTB 0xFF000008 /* Translation table base register */
|
||||
#define MMU_TEA 0xFF00000C /* TLB Exception Address */
|
||||
#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
|
||||
#define MMU_PTEA 0xFF000034 /* PTE assistance register */
|
||||
#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
|
||||
|
||||
#define MMUCR 0xFF000010 /* MMU Control Register */
|
||||
|
||||
#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
|
||||
#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
|
||||
#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
|
||||
#define MMU_PAGE_ASSOC_BIT 0x80
|
||||
|
||||
#define MMUCR_TI (1<<2)
|
||||
|
||||
#ifdef CONFIG_X2TLB
|
||||
#define MMUCR_ME (1 << 7)
|
||||
#else
|
||||
#define MMUCR_ME (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
|
||||
#define MMUCR_SE (1 << 4)
|
||||
#else
|
||||
#define MMUCR_SE (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PTEAEX
|
||||
#define MMUCR_AEX (1 << 6)
|
||||
#else
|
||||
#define MMUCR_AEX (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_X2TLB
|
||||
#define MMUCR_ME (1 << 7)
|
||||
#else
|
||||
#define MMUCR_ME (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SH_STORE_QUEUES
|
||||
#define MMUCR_SQMD (1 << 9)
|
||||
#else
|
||||
|
@ -43,17 +50,7 @@
|
|||
#endif
|
||||
|
||||
#define MMU_NTLB_ENTRIES 64
|
||||
#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
|
||||
|
||||
#define MMU_ITLB_DATA_ARRAY 0xF3000000
|
||||
#define MMU_UTLB_DATA_ARRAY 0xF7000000
|
||||
|
||||
#define MMU_UTLB_ENTRIES 64
|
||||
#define MMU_U_ENTRY_SHIFT 8
|
||||
#define MMU_UTLB_VALID 0x100
|
||||
#define MMU_ITLB_ENTRIES 4
|
||||
#define MMU_I_ENTRY_SHIFT 8
|
||||
#define MMU_ITLB_VALID 0x100
|
||||
#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX)
|
||||
|
||||
#define TRA 0xff000020
|
||||
#define EXPEVT 0xff000024
|
||||
|
|
192
arch/sh/include/cpu-sh4/cpu/sh7786.h
Normal file
192
arch/sh/include/cpu-sh4/cpu/sh7786.h
Normal file
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* SH7786 Pinmux
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on sh7785.h
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef __CPU_SH7786_H__
|
||||
#define __CPU_SH7786_H__
|
||||
|
||||
enum {
|
||||
/* PA */
|
||||
GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
|
||||
GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
|
||||
|
||||
/* PB */
|
||||
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
|
||||
GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
|
||||
|
||||
/* PC */
|
||||
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
|
||||
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
|
||||
|
||||
/* PD */
|
||||
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
|
||||
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
|
||||
|
||||
/* PE */
|
||||
GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
|
||||
GPIO_PE1, GPIO_PE0,
|
||||
|
||||
/* PF */
|
||||
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
|
||||
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
|
||||
|
||||
/* PG */
|
||||
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
|
||||
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
|
||||
|
||||
/* PH */
|
||||
GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
|
||||
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
|
||||
|
||||
/* PJ */
|
||||
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
|
||||
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
|
||||
|
||||
GPIO_FN_CDE,
|
||||
GPIO_FN_ETH_MAGIC,
|
||||
GPIO_FN_DISP,
|
||||
GPIO_FN_ETH_LINK,
|
||||
GPIO_FN_DR5,
|
||||
GPIO_FN_ETH_TX_ER,
|
||||
GPIO_FN_DR4,
|
||||
GPIO_FN_ETH_TX_EN,
|
||||
GPIO_FN_DR3,
|
||||
GPIO_FN_ETH_TXD3,
|
||||
GPIO_FN_DR2,
|
||||
GPIO_FN_ETH_TXD2,
|
||||
GPIO_FN_DR1,
|
||||
GPIO_FN_ETH_TXD1,
|
||||
GPIO_FN_DR0,
|
||||
GPIO_FN_ETH_TXD0,
|
||||
GPIO_FN_VSYNC,
|
||||
GPIO_FN_HSPI_CLK,
|
||||
GPIO_FN_ODDF,
|
||||
GPIO_FN_HSPI_CS,
|
||||
GPIO_FN_DG5,
|
||||
GPIO_FN_ETH_MDIO,
|
||||
GPIO_FN_DG4,
|
||||
GPIO_FN_ETH_RX_CLK,
|
||||
GPIO_FN_DG3,
|
||||
GPIO_FN_ETH_MDC,
|
||||
GPIO_FN_DG2,
|
||||
GPIO_FN_ETH_COL,
|
||||
GPIO_FN_DG1,
|
||||
GPIO_FN_ETH_TX_CLK,
|
||||
GPIO_FN_DG0,
|
||||
GPIO_FN_ETH_CRS,
|
||||
GPIO_FN_DCLKIN,
|
||||
GPIO_FN_HSPI_RX,
|
||||
GPIO_FN_HSYNC,
|
||||
GPIO_FN_HSPI_TX,
|
||||
GPIO_FN_DB5,
|
||||
GPIO_FN_ETH_RXD3,
|
||||
GPIO_FN_DB4,
|
||||
GPIO_FN_ETH_RXD2,
|
||||
GPIO_FN_DB3,
|
||||
GPIO_FN_ETH_RXD1,
|
||||
GPIO_FN_DB2,
|
||||
GPIO_FN_ETH_RXD0,
|
||||
GPIO_FN_DB1,
|
||||
GPIO_FN_ETH_RX_DV,
|
||||
GPIO_FN_DB0,
|
||||
GPIO_FN_ETH_RX_ER,
|
||||
GPIO_FN_DCLKOUT,
|
||||
GPIO_FN_SCIF1_SLK,
|
||||
GPIO_FN_SCIF1_RXD,
|
||||
GPIO_FN_SCIF1_TXD,
|
||||
GPIO_FN_DACK1,
|
||||
GPIO_FN_BACK,
|
||||
GPIO_FN_FALE,
|
||||
GPIO_FN_DACK0,
|
||||
GPIO_FN_FCLE,
|
||||
GPIO_FN_DREQ1,
|
||||
GPIO_FN_BREQ,
|
||||
GPIO_FN_USB_OVC1,
|
||||
GPIO_FN_DREQ0,
|
||||
GPIO_FN_USB_OVC0,
|
||||
GPIO_FN_USB_PENC1,
|
||||
GPIO_FN_USB_PENC0,
|
||||
GPIO_FN_HAC1_SDOUT,
|
||||
GPIO_FN_SSI1_SDATA,
|
||||
GPIO_FN_SDIF1CMD,
|
||||
GPIO_FN_HAC1_SDIN,
|
||||
GPIO_FN_SSI1_SCK,
|
||||
GPIO_FN_SDIF1CD,
|
||||
GPIO_FN_HAC1_SYNC,
|
||||
GPIO_FN_SSI1_WS,
|
||||
GPIO_FN_SDIF1WP,
|
||||
GPIO_FN_HAC1_BITCLK,
|
||||
GPIO_FN_SSI1_CLK,
|
||||
GPIO_FN_SDIF1CLK,
|
||||
GPIO_FN_HAC0_SDOUT,
|
||||
GPIO_FN_SSI0_SDATA,
|
||||
GPIO_FN_SDIF1D3,
|
||||
GPIO_FN_HAC0_SDIN,
|
||||
GPIO_FN_SSI0_SCK,
|
||||
GPIO_FN_SDIF1D2,
|
||||
GPIO_FN_HAC0_SYNC,
|
||||
GPIO_FN_SSI0_WS,
|
||||
GPIO_FN_SDIF1D1,
|
||||
GPIO_FN_HAC0_BITCLK,
|
||||
GPIO_FN_SSI0_CLK,
|
||||
GPIO_FN_SDIF1D0,
|
||||
GPIO_FN_SCIF3_SCK,
|
||||
GPIO_FN_SSI2_SDATA,
|
||||
GPIO_FN_SCIF3_RXD,
|
||||
GPIO_FN_TCLK,
|
||||
GPIO_FN_SSI2_SCK,
|
||||
GPIO_FN_SCIF3_TXD,
|
||||
GPIO_FN_HAC_RES,
|
||||
GPIO_FN_SSI2_WS,
|
||||
GPIO_FN_DACK3,
|
||||
GPIO_FN_SDIF0CMD,
|
||||
GPIO_FN_DACK2,
|
||||
GPIO_FN_SDIF0CD,
|
||||
GPIO_FN_DREQ3,
|
||||
GPIO_FN_SDIF0WP,
|
||||
GPIO_FN_SCIF0_CTS,
|
||||
GPIO_FN_DREQ2,
|
||||
GPIO_FN_SDIF0CLK,
|
||||
GPIO_FN_SCIF0_RTS,
|
||||
GPIO_FN_IRL7,
|
||||
GPIO_FN_SDIF0D3,
|
||||
GPIO_FN_SCIF0_SCK,
|
||||
GPIO_FN_IRL6,
|
||||
GPIO_FN_SDIF0D2,
|
||||
GPIO_FN_SCIF0_RXD,
|
||||
GPIO_FN_IRL5,
|
||||
GPIO_FN_SDIF0D1,
|
||||
GPIO_FN_SCIF0_TXD,
|
||||
GPIO_FN_IRL4,
|
||||
GPIO_FN_SDIF0D0,
|
||||
GPIO_FN_SCIF5_SCK,
|
||||
GPIO_FN_FRB,
|
||||
GPIO_FN_SCIF5_RXD,
|
||||
GPIO_FN_IOIS16,
|
||||
GPIO_FN_SCIF5_TXD,
|
||||
GPIO_FN_CE2B,
|
||||
GPIO_FN_DRAK3,
|
||||
GPIO_FN_CE2A,
|
||||
GPIO_FN_SCIF4_SCK,
|
||||
GPIO_FN_DRAK2,
|
||||
GPIO_FN_SSI3_WS,
|
||||
GPIO_FN_SCIF4_RXD,
|
||||
GPIO_FN_DRAK1,
|
||||
GPIO_FN_SSI3_SDATA,
|
||||
GPIO_FN_FSTATUS,
|
||||
GPIO_FN_SCIF4_TXD,
|
||||
GPIO_FN_DRAK0,
|
||||
GPIO_FN_SSI3_SCK,
|
||||
GPIO_FN_FSE,
|
||||
};
|
||||
|
||||
#endif /* __CPU_SH7786_H__ */
|
68
arch/sh/include/mach-common/mach/urquell.h
Normal file
68
arch/sh/include/mach-common/mach/urquell.h
Normal file
|
@ -0,0 +1,68 @@
|
|||
#ifndef __MACH_URQUELL_H
|
||||
#define __MACH_URQUELL_H
|
||||
|
||||
/*
|
||||
* ------ 0x00000000 ------------------------------------
|
||||
* CS0 | (SW1,SW47) EEPROM, SRAM, NOR FLASH
|
||||
* -----+ 0x04000000 ------------------------------------
|
||||
* CS1 | (SW47) SRAM, SRAM-LAN-PCMCIA, NOR FLASH
|
||||
* -----+ 0x08000000 ------------------------------------
|
||||
* CS2 | DDR3
|
||||
* CS3 |
|
||||
* -----+ 0x10000000 ------------------------------------
|
||||
* CS4 | PCIe
|
||||
* -----+ 0x14000000 ------------------------------------
|
||||
* CS5 | (SW47) LRAM/URAM, SRAM-LAN-PCMCIA
|
||||
* -----+ 0x18000000 ------------------------------------
|
||||
* CS6 | ATA, NAND FLASH
|
||||
* -----+ 0x1c000000 ------------------------------------
|
||||
* CS7 | SH7786 register
|
||||
* -----+------------------------------------------------
|
||||
*/
|
||||
|
||||
#define NOR_FLASH_ADDR 0x00000000
|
||||
#define NOR_FLASH_SIZE 0x04000000
|
||||
|
||||
#define CS1_BASE 0x05000000
|
||||
#define CS5_BASE 0x15000000
|
||||
#define FPGA_BASE CS1_BASE
|
||||
|
||||
#define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS)
|
||||
#define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS)
|
||||
|
||||
#define SRSTR_OFS 0x0000 /* System reset register */
|
||||
#define BDMR_OFS 0x0010 /* Board operating mode resister */
|
||||
#define IRL0SR_OFS 0x0020 /* IRL0 Status register */
|
||||
#define IRL0MSKR_OFS 0x0030 /* IRL0 Mask register */
|
||||
#define IRL1SR_OFS 0x0040 /* IRL1 Status register */
|
||||
#define IRL1MSKR_OFS 0x0050 /* IRL1 Mask register */
|
||||
#define IRL2SR_OFS 0x0060 /* IRL2 Status register */
|
||||
#define IRL2MSKR_OFS 0x0070 /* IRL2 Mask register */
|
||||
#define IRL3SR_OFS 0x0080 /* IRL3 Status register */
|
||||
#define IRL3MSKR_OFS 0x0090 /* IRL3 Mask register */
|
||||
#define SOFTINTR_OFS 0x0120 /* Softwear Interrupt register */
|
||||
#define SLEDR_OFS 0x0130 /* LED control resister */
|
||||
#define MAPSCIFSWR_OFS 0x0140 /* Map/SCIF Switch register */
|
||||
#define FPVERR_OFS 0x0150 /* FPGA Version register */
|
||||
#define FPDATER_OFS 0x0160 /* FPGA Date register */
|
||||
#define FPYEARR_OFS 0x0170 /* FPGA Year register */
|
||||
#define TCLKCR_OFS 0x0180 /* TCLK Control register */
|
||||
#define DIPSWMR_OFS 0x1000 /* DIPSW monitor register */
|
||||
#define FPODR_OFS 0x1010 /* Output port data register */
|
||||
#define ATACNR_OFS 0x1020 /* ATA-CN Control/status register */
|
||||
#define FPINDR_OFS 0x1030 /* Input port data register */
|
||||
#define MDSWMR_OFS 0x1040 /* MODE SW monitor register */
|
||||
#define DDR3BUPCR_OFS 0x1050 /* DDR3 Backup control register */
|
||||
#define SSICODECCR_OFS 0x1060 /* SSI-CODEC control register */
|
||||
#define PCIESLOTSR_OFS 0x1070 /* PCIexpress Slot status register */
|
||||
#define ETHERPORTSR_OFS 0x1080 /* EtherPhy Port status register */
|
||||
#define LATCHCR_OFS 0x3000 /* Latch control register */
|
||||
#define LATCUAR_OFS 0x3010 /* Latch upper address register */
|
||||
#define LATCLAR_OFS 0x3012 /* Latch lower address register */
|
||||
#define LATCLUDR_OFS 0x3024 /* Latch D31-16 register */
|
||||
#define LATCLLDR_OFS 0x3026 /* Latch D15-0 register */
|
||||
|
||||
#define CHARLED_OFS 0x2000 /* Character LED */
|
||||
|
||||
#endif /* __MACH_URQUELL_H */
|
||||
|
|
@ -30,5 +30,6 @@ obj-$(CONFIG_KPROBES) += kprobes.o
|
|||
obj-$(CONFIG_GENERIC_GPIO) += gpio.o
|
||||
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
|
||||
obj-$(CONFIG_DUMP_CODE) += disassemble.o
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp.o
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
|
|
|
@ -12,8 +12,10 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/kbuild.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
|
@ -25,5 +27,11 @@ int main(void)
|
|||
DEFINE(TI_PRE_COUNT, offsetof(struct thread_info, preempt_count));
|
||||
DEFINE(TI_RESTART_BLOCK,offsetof(struct thread_info, restart_block));
|
||||
|
||||
#ifdef CONFIG_HIBERNATION
|
||||
DEFINE(PBE_ADDRESS, offsetof(struct pbe, address));
|
||||
DEFINE(PBE_ORIG_ADDRESS, offsetof(struct pbe, orig_address));
|
||||
DEFINE(PBE_NEXT, offsetof(struct pbe, next));
|
||||
DEFINE(SWSUSP_ARCH_REGS_SIZE, sizeof(struct swsusp_arch_regs));
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SH5) = sh5/
|
|||
# Special cases for family ancestry.
|
||||
|
||||
obj-$(CONFIG_CPU_SH4A) += sh4a/
|
||||
obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
|
||||
|
||||
# Common interfaces.
|
||||
|
||||
|
|
|
@ -20,6 +20,8 @@
|
|||
#include <linux/mutex.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/kref.h>
|
||||
#include <linux/kobject.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
@ -239,6 +241,35 @@ void clk_recalc_rate(struct clk *clk)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(clk_recalc_rate);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
struct clk *old;
|
||||
|
||||
if (!parent || !clk)
|
||||
return ret;
|
||||
|
||||
old = clk->parent;
|
||||
if (likely(clk->ops && clk->ops->set_parent)) {
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&clock_lock, flags);
|
||||
ret = clk->ops->set_parent(clk, parent);
|
||||
spin_unlock_irqrestore(&clock_lock, flags);
|
||||
clk->parent = (ret ? old : parent);
|
||||
}
|
||||
|
||||
if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
|
||||
propagate_rate(clk);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_parent);
|
||||
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (likely(clk->ops && clk->ops->round_rate)) {
|
||||
|
@ -329,6 +360,70 @@ static int show_clocks(char *buf, char **start, off_t off,
|
|||
return p - buf;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
static pm_message_t prev_state;
|
||||
struct clk *clkp;
|
||||
|
||||
switch (state.event) {
|
||||
case PM_EVENT_ON:
|
||||
/* Resumeing from hibernation */
|
||||
if (prev_state.event == PM_EVENT_FREEZE) {
|
||||
list_for_each_entry(clkp, &clock_list, node)
|
||||
if (likely(clkp->ops)) {
|
||||
unsigned long rate = clkp->rate;
|
||||
|
||||
if (likely(clkp->ops->set_parent))
|
||||
clkp->ops->set_parent(clkp,
|
||||
clkp->parent);
|
||||
if (likely(clkp->ops->set_rate))
|
||||
clkp->ops->set_rate(clkp,
|
||||
rate, NO_CHANGE);
|
||||
else if (likely(clkp->ops->recalc))
|
||||
clkp->ops->recalc(clkp);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PM_EVENT_FREEZE:
|
||||
break;
|
||||
case PM_EVENT_SUSPEND:
|
||||
break;
|
||||
}
|
||||
|
||||
prev_state = state;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clks_sysdev_resume(struct sys_device *dev)
|
||||
{
|
||||
return clks_sysdev_suspend(dev, PMSG_ON);
|
||||
}
|
||||
|
||||
static struct sysdev_class clks_sysdev_class = {
|
||||
.name = "clks",
|
||||
};
|
||||
|
||||
static struct sysdev_driver clks_sysdev_driver = {
|
||||
.suspend = clks_sysdev_suspend,
|
||||
.resume = clks_sysdev_resume,
|
||||
};
|
||||
|
||||
static struct sys_device clks_sysdev_dev = {
|
||||
.cls = &clks_sysdev_class,
|
||||
};
|
||||
|
||||
static int __init clk_sysdev_init(void)
|
||||
{
|
||||
sysdev_class_register(&clks_sysdev_class);
|
||||
sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver);
|
||||
sysdev_register(&clks_sysdev_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(clk_sysdev_init);
|
||||
#endif
|
||||
|
||||
int __init clk_init(void)
|
||||
{
|
||||
int i, ret = 0;
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* SH7619 Setup
|
||||
*
|
||||
* Copyright (C) 2006 Yoshinori Sato
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -18,15 +19,10 @@ enum {
|
|||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
WDT, EDMAC, CMT0, CMT1,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
|
||||
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
|
||||
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
|
||||
SCIF0, SCIF1, SCIF2,
|
||||
HIF_HIFI, HIF_HIFBI,
|
||||
DMAC0, DMAC1, DMAC2, DMAC3,
|
||||
SIOF,
|
||||
|
||||
/* interrupt groups */
|
||||
SCIF0, SCIF1, SCIF2,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
|
@ -36,24 +32,18 @@ static struct intc_vect vectors[] __initdata = {
|
|||
INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
|
||||
INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
|
||||
INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
|
||||
INTC_IRQ(SCIF0_ERI, 88), INTC_IRQ(SCIF0_RXI, 89),
|
||||
INTC_IRQ(SCIF0_BRI, 90), INTC_IRQ(SCIF0_TXI, 91),
|
||||
INTC_IRQ(SCIF1_ERI, 92), INTC_IRQ(SCIF1_RXI, 93),
|
||||
INTC_IRQ(SCIF1_BRI, 94), INTC_IRQ(SCIF1_TXI, 95),
|
||||
INTC_IRQ(SCIF2_ERI, 96), INTC_IRQ(SCIF2_RXI, 97),
|
||||
INTC_IRQ(SCIF2_BRI, 98), INTC_IRQ(SCIF2_TXI, 99),
|
||||
INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
|
||||
INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
|
||||
INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
|
||||
INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
|
||||
INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
|
||||
INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
|
||||
INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
|
||||
INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
|
||||
INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
|
||||
INTC_IRQ(SIOF, 108),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
|
@ -64,7 +54,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
{ 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, groups,
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
|
@ -72,17 +62,17 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xf8400000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 88, 89, 91, 90},
|
||||
.irqs = { 88, 88, 88, 88 },
|
||||
}, {
|
||||
.mapbase = 0xf8410000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 92, 93, 95, 94},
|
||||
.irqs = { 92, 92, 92, 92 },
|
||||
}, {
|
||||
.mapbase = 0xf8420000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 96, 97, 99, 98},
|
||||
.irqs = { 96, 96, 96, 96 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Renesas MX-G (R8A03022BG) Setup
|
||||
*
|
||||
* Copyright (C) 2008 Paul Mundt
|
||||
* Copyright (C) 2008, 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -20,23 +20,15 @@ enum {
|
|||
IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
|
||||
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
|
||||
SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
|
||||
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF0, SCIF1,
|
||||
|
||||
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
|
||||
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
|
||||
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
|
||||
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
|
||||
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
|
||||
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
|
||||
MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
|
||||
MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
|
||||
MTU2_TGI3B, MTU2_TGI3C,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT, SCIF0, SCIF1,
|
||||
MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
|
@ -59,47 +51,36 @@ static struct intc_vect vectors[] __initdata = {
|
|||
INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
|
||||
INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
|
||||
|
||||
INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221),
|
||||
INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223),
|
||||
INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225),
|
||||
INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227),
|
||||
INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
|
||||
INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
|
||||
INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
|
||||
INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
|
||||
|
||||
INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229),
|
||||
INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231),
|
||||
INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233),
|
||||
INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
|
||||
INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
|
||||
INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
|
||||
|
||||
INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235),
|
||||
INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237),
|
||||
INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239),
|
||||
INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
|
||||
INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
|
||||
INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
|
||||
|
||||
INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241),
|
||||
INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243),
|
||||
INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
|
||||
INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
|
||||
|
||||
INTC_IRQ(MTU2_TGI3B, 244),
|
||||
INTC_IRQ(MTU2_TGI3C, 245),
|
||||
|
||||
INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247),
|
||||
INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249),
|
||||
INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251),
|
||||
INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
|
||||
INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
|
||||
INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
|
||||
|
||||
INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253),
|
||||
INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255),
|
||||
INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
|
||||
INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
|
||||
MTU2_TCI0V, MTU2_TGI0E),
|
||||
INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
|
||||
MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
|
||||
INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
|
||||
MTU2_TGI3A),
|
||||
INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
|
||||
MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
|
||||
INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
|
@ -137,7 +118,7 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xff804000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 223, 220, 221, 222 },
|
||||
.irqs = { 220, 220, 220, 220 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* SH7201 setup
|
||||
*
|
||||
* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -18,57 +19,32 @@ enum {
|
|||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
|
||||
ADC_ADI,
|
||||
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
|
||||
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
|
||||
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
|
||||
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
|
||||
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
|
||||
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
|
||||
MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
|
||||
RTC_ARM, RTC_PRD, RTC_CUP,
|
||||
WDT,
|
||||
IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
|
||||
IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
|
||||
IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
|
||||
|
||||
MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
|
||||
MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
|
||||
|
||||
RTC, WDT,
|
||||
|
||||
IIC30, IIC31, IIC32,
|
||||
|
||||
DMAC0_DMINT0, DMAC1_DMINT1,
|
||||
DMAC2_DMINT2, DMAC3_DMINT3,
|
||||
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
|
||||
SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
|
||||
SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
|
||||
SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
|
||||
SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
|
||||
SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
|
||||
|
||||
DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
|
||||
DMAC7_DMINT7,
|
||||
|
||||
RCAN0_ERS, RCAN0_OVR,
|
||||
RCAN0_SLE,
|
||||
RCAN0_RM0, RCAN0_RM1,
|
||||
|
||||
RCAN1_ERS, RCAN1_OVR,
|
||||
RCAN1_SLE,
|
||||
RCAN1_RM0, RCAN1_RM1,
|
||||
RCAN0, RCAN1,
|
||||
|
||||
SSI0_SSII, SSI1_SSII,
|
||||
|
||||
TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0,
|
||||
TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1,
|
||||
TMR0, TMR1,
|
||||
|
||||
/* interrupt groups */
|
||||
|
||||
IRQ, PINT, ADC,
|
||||
MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
|
||||
MTU23_ABCD, MTU24_ABCD, MTU25_UVW,
|
||||
RTC, IIC30, IIC31, IIC32,
|
||||
SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
|
||||
RCAN0, RCAN1, TMR0, TMR1
|
||||
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
|
@ -76,6 +52,7 @@ static struct intc_vect vectors[] __initdata = {
|
|||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
|
@ -83,123 +60,92 @@ static struct intc_vect vectors[] __initdata = {
|
|||
|
||||
INTC_IRQ(ADC_ADI, 92),
|
||||
|
||||
INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109),
|
||||
INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111),
|
||||
INTC_IRQ(MTU2_TCI0V, 112),
|
||||
INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114),
|
||||
INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
|
||||
INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
|
||||
|
||||
INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117),
|
||||
INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121),
|
||||
INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
|
||||
INTC_IRQ(MTU20_VEF, 114),
|
||||
|
||||
INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125),
|
||||
INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129),
|
||||
INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
|
||||
INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
|
||||
|
||||
INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
|
||||
INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
|
||||
|
||||
INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
|
||||
INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
|
||||
|
||||
INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133),
|
||||
INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135),
|
||||
INTC_IRQ(MTU2_TCI3V, 136),
|
||||
|
||||
INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141),
|
||||
INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143),
|
||||
INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
|
||||
INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
|
||||
|
||||
INTC_IRQ(MTU2_TCI4V, 144),
|
||||
|
||||
INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149),
|
||||
INTC_IRQ(MTU2_TGI5W, 150),
|
||||
INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
|
||||
INTC_IRQ(MTU25_UVW, 150),
|
||||
|
||||
INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153),
|
||||
INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156),
|
||||
INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
|
||||
INTC_IRQ(RTC, 154),
|
||||
|
||||
INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158),
|
||||
INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160),
|
||||
INTC_IRQ(IIC30_TEI, 161),
|
||||
INTC_IRQ(WDT, 156),
|
||||
|
||||
INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165),
|
||||
INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167),
|
||||
INTC_IRQ(IIC31_TEI, 168),
|
||||
INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
|
||||
INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
|
||||
INTC_IRQ(IIC30, 161),
|
||||
|
||||
INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171),
|
||||
INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173),
|
||||
INTC_IRQ(IIC32_TEI, 174),
|
||||
INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
|
||||
INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
|
||||
INTC_IRQ(IIC31, 168),
|
||||
|
||||
INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
|
||||
INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
|
||||
INTC_IRQ(IIC32, 174),
|
||||
|
||||
INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
|
||||
INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
|
||||
|
||||
INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181),
|
||||
INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183),
|
||||
INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185),
|
||||
INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187),
|
||||
INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189),
|
||||
INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191),
|
||||
INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193),
|
||||
INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195),
|
||||
INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197),
|
||||
INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199),
|
||||
INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201),
|
||||
INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203),
|
||||
INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205),
|
||||
INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207),
|
||||
INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209),
|
||||
INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211),
|
||||
INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
|
||||
INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
|
||||
INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
|
||||
INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
|
||||
INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
|
||||
INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
|
||||
INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
|
||||
INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
|
||||
INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
|
||||
INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
|
||||
INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
|
||||
INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
|
||||
INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
|
||||
INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
|
||||
INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
|
||||
INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
|
||||
|
||||
INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
|
||||
INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
|
||||
INTC_IRQ(DMAC7_DMINT7, 219),
|
||||
|
||||
INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229),
|
||||
INTC_IRQ(RCAN0_SLE, 230),
|
||||
INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232),
|
||||
INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
|
||||
INTC_IRQ(RCAN0, 230),
|
||||
INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
|
||||
|
||||
INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235),
|
||||
INTC_IRQ(RCAN1_SLE, 236),
|
||||
INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238),
|
||||
INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
|
||||
INTC_IRQ(RCAN1, 236),
|
||||
INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
|
||||
|
||||
INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
|
||||
|
||||
INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247),
|
||||
INTC_IRQ(TMR0_OVI0, 248),
|
||||
|
||||
INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253),
|
||||
INTC_IRQ(TMR1_OVI1, 254),
|
||||
INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
|
||||
INTC_IRQ(TMR0, 248),
|
||||
|
||||
INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
|
||||
INTC_IRQ(TMR1, 254),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
|
||||
INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
|
||||
|
||||
INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B),
|
||||
INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U),
|
||||
INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B),
|
||||
INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U),
|
||||
INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
|
||||
INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
|
||||
INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
|
||||
INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ),
|
||||
|
||||
INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
|
||||
IIC30_TEI),
|
||||
INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
|
||||
IIC31_TEI),
|
||||
INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
|
||||
IIC32_TEI),
|
||||
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
|
||||
INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
|
||||
INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
|
||||
INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
|
||||
|
||||
INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
|
||||
RCAN0_SLE),
|
||||
INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
|
||||
RCAN1_SLE),
|
||||
|
||||
INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0),
|
||||
INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
|
@ -212,7 +158,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
|
||||
{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
|
||||
{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
|
||||
{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } },
|
||||
{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
|
||||
{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
|
||||
{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
|
||||
{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
|
||||
|
@ -234,42 +180,42 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xfffe8000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 181, 182, 183, 180}
|
||||
.irqs = { 180, 180, 180, 180 }
|
||||
}, {
|
||||
.mapbase = 0xfffe8800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 185, 186, 187, 184}
|
||||
.irqs = { 184, 184, 184, 184 }
|
||||
}, {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 189, 186, 187, 188}
|
||||
.irqs = { 188, 188, 188, 188 }
|
||||
}, {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 193, 194, 195, 192}
|
||||
.irqs = { 192, 192, 192, 192 }
|
||||
}, {
|
||||
.mapbase = 0xfffea000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 196, 198, 199, 196}
|
||||
.irqs = { 196, 196, 196, 196 }
|
||||
}, {
|
||||
.mapbase = 0xfffea800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 201, 202, 203, 200}
|
||||
.irqs = { 200, 200, 200, 200 }
|
||||
}, {
|
||||
.mapbase = 0xfffeb000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 205, 206, 207, 204}
|
||||
.irqs = { 204, 204, 204, 204 }
|
||||
}, {
|
||||
.mapbase = 0xfffeb800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 209, 210, 211, 208}
|
||||
.irqs = { 208, 208, 208, 208 }
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
@ -290,17 +236,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 153,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 154,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 152,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SH7203 and SH7263 Setup
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
* Copyright (C) 2007 - 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -18,50 +18,27 @@ enum {
|
|||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
|
||||
DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
|
||||
DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
|
||||
DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
USB, LCDC, CMT0, CMT1, BSC, WDT,
|
||||
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
|
||||
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
|
||||
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
|
||||
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
|
||||
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
|
||||
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
|
||||
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
|
||||
|
||||
ADC_ADI,
|
||||
IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
|
||||
IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
|
||||
IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
|
||||
IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
|
||||
SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
|
||||
SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
|
||||
|
||||
IIC30, IIC31, IIC32, IIC33,
|
||||
SCIF0, SCIF1, SCIF2, SCIF3,
|
||||
|
||||
SSU0, SSU1,
|
||||
|
||||
SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
|
||||
|
||||
/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
|
||||
ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF,
|
||||
ROMDEC_IREADY,
|
||||
|
||||
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
|
||||
|
||||
SDHI3, SDHI0, SDHI1,
|
||||
|
||||
RTC_ARM, RTC_PRD, RTC_CUP,
|
||||
RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
|
||||
RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
|
||||
|
||||
SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI,
|
||||
ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
|
||||
SRC, IEBI,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU4_ABCD,
|
||||
IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
|
||||
SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
|
@ -73,79 +50,80 @@ static struct intc_vect vectors[] __initdata = {
|
|||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
|
||||
INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
|
||||
INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
|
||||
INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
|
||||
INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
|
||||
INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
|
||||
INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
|
||||
INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
|
||||
INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
|
||||
INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
|
||||
INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147),
|
||||
INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149),
|
||||
INTC_IRQ(MTU2_TCI0V, 150),
|
||||
INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152),
|
||||
INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154),
|
||||
INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156),
|
||||
INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158),
|
||||
INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160),
|
||||
INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162),
|
||||
INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164),
|
||||
INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
|
||||
INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
|
||||
INTC_IRQ(MTU0_VEF, 150),
|
||||
INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
|
||||
INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
|
||||
INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
|
||||
INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
|
||||
INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
|
||||
INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
|
||||
INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
|
||||
INTC_IRQ(MTU2_TCI3V, 165),
|
||||
INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167),
|
||||
INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169),
|
||||
INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
|
||||
INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
|
||||
INTC_IRQ(MTU2_TCI4V, 170),
|
||||
INTC_IRQ(ADC_ADI, 171),
|
||||
INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173),
|
||||
INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175),
|
||||
INTC_IRQ(IIC30_TEI, 176),
|
||||
INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178),
|
||||
INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180),
|
||||
INTC_IRQ(IIC31_TEI, 181),
|
||||
INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183),
|
||||
INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185),
|
||||
INTC_IRQ(IIC32_TEI, 186),
|
||||
INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188),
|
||||
INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190),
|
||||
INTC_IRQ(IIC33_TEI, 191),
|
||||
INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193),
|
||||
INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195),
|
||||
INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197),
|
||||
INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199),
|
||||
INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201),
|
||||
INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203),
|
||||
INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205),
|
||||
INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207),
|
||||
INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209),
|
||||
INTC_IRQ(SSU0_SSTXI, 210),
|
||||
INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212),
|
||||
INTC_IRQ(SSU1_SSTXI, 213),
|
||||
INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
|
||||
INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
|
||||
INTC_IRQ(IIC30, 176),
|
||||
INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
|
||||
INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
|
||||
INTC_IRQ(IIC31, 181),
|
||||
INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
|
||||
INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
|
||||
INTC_IRQ(IIC32, 186),
|
||||
INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
|
||||
INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
|
||||
INTC_IRQ(IIC33, 191),
|
||||
INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
|
||||
INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
|
||||
INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
|
||||
INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
|
||||
INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
|
||||
INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
|
||||
INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
|
||||
INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
|
||||
INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
|
||||
INTC_IRQ(SSU0, 210),
|
||||
INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
|
||||
INTC_IRQ(SSU1, 213),
|
||||
INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
|
||||
INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
|
||||
INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225),
|
||||
INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227),
|
||||
INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232),
|
||||
INTC_IRQ(RTC_CUP, 233),
|
||||
INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235),
|
||||
INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237),
|
||||
INTC_IRQ(RCAN0_SLE, 238),
|
||||
INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240),
|
||||
INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242),
|
||||
INTC_IRQ(RCAN1_SLE, 243),
|
||||
INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
|
||||
INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
|
||||
INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
|
||||
INTC_IRQ(RTC, 233),
|
||||
INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
|
||||
INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
|
||||
INTC_IRQ(RCAN0, 238),
|
||||
INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
|
||||
INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
|
||||
INTC_IRQ(RCAN1, 243),
|
||||
|
||||
/* SH7263-specific trash */
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7263
|
||||
INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219),
|
||||
INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221),
|
||||
INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223),
|
||||
INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
|
||||
INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
|
||||
INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
|
||||
|
||||
INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230),
|
||||
INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
|
||||
INTC_IRQ(SDHI, 230),
|
||||
|
||||
INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245),
|
||||
INTC_IRQ(SRC_IDEI, 246),
|
||||
INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
|
||||
INTC_IRQ(SRC, 246),
|
||||
|
||||
INTC_IRQ(IEBI, 247),
|
||||
#endif
|
||||
|
@ -154,50 +132,6 @@ static struct intc_vect vectors[] __initdata = {
|
|||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
|
||||
INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
|
||||
INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
|
||||
INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
|
||||
INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
|
||||
INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
|
||||
INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
|
||||
INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
|
||||
INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
|
||||
INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
|
||||
INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
|
||||
INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
|
||||
INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
|
||||
INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
|
||||
INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
|
||||
INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
|
||||
INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
|
||||
IIC30_TEI),
|
||||
INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
|
||||
IIC31_TEI),
|
||||
INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
|
||||
IIC32_TEI),
|
||||
INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
|
||||
IIC33_TEI),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
|
||||
INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
|
||||
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
|
||||
FLCTL_FLTREQ1I),
|
||||
INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
|
||||
INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
|
||||
RCAN0_SLE),
|
||||
INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
|
||||
RCAN1_SLE),
|
||||
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7263
|
||||
INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,
|
||||
ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),
|
||||
INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),
|
||||
INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
|
@ -242,22 +176,22 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xfffe8000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 193, 194, 195, 192 },
|
||||
.irqs = { 192, 192, 192, 192 },
|
||||
}, {
|
||||
.mapbase = 0xfffe8800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 197, 198, 199, 196 },
|
||||
.irqs = { 196, 196, 196, 196 },
|
||||
}, {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 201, 202, 203, 200 },
|
||||
.irqs = { 200, 200, 200, 200 },
|
||||
}, {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 205, 206, 207, 204 },
|
||||
.irqs = { 204, 204, 204, 204 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
@ -278,17 +212,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 232,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 233,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 231,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* SH7206 Setup
|
||||
*
|
||||
* Copyright (C) 2006 Yoshinori Sato
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -19,34 +20,23 @@ enum {
|
|||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
ADC_ADI0, ADC_ADI1,
|
||||
DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
|
||||
DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
|
||||
DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
|
||||
DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
|
||||
CMT0, CMT1, BSC, WDT,
|
||||
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
|
||||
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
|
||||
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
|
||||
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
|
||||
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
|
||||
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
|
||||
MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
|
||||
POE2_OEI1, POE2_OEI2,
|
||||
MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V,
|
||||
MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V,
|
||||
MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W,
|
||||
POE2_OEI3,
|
||||
IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI,
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
|
||||
IIC3, SCIF0, SCIF1, SCIF2, SCIF3,
|
||||
IIC3,
|
||||
|
||||
CMT0, CMT1, BSC, WDT,
|
||||
|
||||
MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
|
||||
|
||||
POE2_OEI3,
|
||||
|
||||
SCIF0, SCIF1, SCIF2, SCIF3,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
|
@ -59,86 +49,58 @@ static struct intc_vect vectors[] __initdata = {
|
|||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
|
||||
INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
|
||||
INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
|
||||
INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
|
||||
INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
|
||||
INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
|
||||
INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
|
||||
INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
|
||||
INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
|
||||
INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
|
||||
INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157),
|
||||
INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159),
|
||||
INTC_IRQ(MTU2_TCI0V, 160),
|
||||
INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162),
|
||||
INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165),
|
||||
INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169),
|
||||
INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173),
|
||||
INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177),
|
||||
INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181),
|
||||
INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183),
|
||||
INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
|
||||
INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
|
||||
INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
|
||||
INTC_IRQ(MTU0_VEF, 162),
|
||||
INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
|
||||
INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
|
||||
INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
|
||||
INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
|
||||
INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
|
||||
INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
|
||||
INTC_IRQ(MTU2_TCI3V, 184),
|
||||
INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189),
|
||||
INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191),
|
||||
INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
|
||||
INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
|
||||
INTC_IRQ(MTU2_TCI4V, 192),
|
||||
INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197),
|
||||
INTC_IRQ(MTU2_TGI5W, 198),
|
||||
INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201),
|
||||
INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205),
|
||||
INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207),
|
||||
INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
|
||||
INTC_IRQ(MTU5, 198),
|
||||
INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
|
||||
INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
|
||||
INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
|
||||
INTC_IRQ(MTU2S_TCI3V, 208),
|
||||
INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213),
|
||||
INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215),
|
||||
INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
|
||||
INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
|
||||
INTC_IRQ(MTU2S_TCI4V, 216),
|
||||
INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221),
|
||||
INTC_IRQ(MTU2S_TGI5W, 222),
|
||||
INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
|
||||
INTC_IRQ(MTU5S, 222),
|
||||
INTC_IRQ(POE2_OEI3, 224),
|
||||
INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229),
|
||||
INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231),
|
||||
INTC_IRQ(IIC3_TEI, 232),
|
||||
INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241),
|
||||
INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243),
|
||||
INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245),
|
||||
INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247),
|
||||
INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249),
|
||||
INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251),
|
||||
INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253),
|
||||
INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255),
|
||||
INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
|
||||
INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
|
||||
INTC_IRQ(IIC3, 232),
|
||||
INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
|
||||
INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
|
||||
INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
|
||||
INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
|
||||
INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
|
||||
INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
|
||||
INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
|
||||
INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
|
||||
INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
|
||||
INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
|
||||
INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
|
||||
INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
|
||||
INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
|
||||
INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
|
||||
INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
|
||||
INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
|
||||
INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
|
||||
INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
|
||||
INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
|
||||
INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
|
||||
INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
|
||||
INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
|
||||
INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
|
||||
INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
|
||||
INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2),
|
||||
INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B,
|
||||
MTU2S_TGI3C, MTU2S_TGI3D),
|
||||
INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B,
|
||||
MTU2S_TGI4C, MTU2S_TGI4D),
|
||||
INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W),
|
||||
INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
|
@ -174,22 +136,22 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xfffe8000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 241, 242, 243, 240 },
|
||||
.irqs = { 240, 240, 240, 240 },
|
||||
}, {
|
||||
.mapbase = 0xfffe8800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 245, 246, 247, 244 },
|
||||
.irqs = { 244, 244, 244, 244 },
|
||||
}, {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 249, 250, 251, 248 },
|
||||
.irqs = { 248, 248, 248, 248 },
|
||||
}, {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 253, 254, 255, 252 },
|
||||
.irqs = { 252, 252, 252, 252 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
|
|
@ -4,6 +4,8 @@
|
|||
|
||||
obj-y := ex.o probe.o entry.o setup-sh3.o
|
||||
|
||||
obj-$(CONFIG_HIBERNATION) += swsusp.o
|
||||
|
||||
# CPU subtype setup
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <asm/unistd.h>
|
||||
#include <cpu/mmu_context.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
! NOTE:
|
||||
! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
|
||||
|
@ -187,44 +188,35 @@ call_dae:
|
|||
#if defined(CONFIG_SH_STANDARD_BIOS)
|
||||
/* Unwind the stack and jmp to the debug entry */
|
||||
ENTRY(sh_bios_handler)
|
||||
mov.l @r15+, r0
|
||||
mov.l @r15+, r1
|
||||
mov.l @r15+, r2
|
||||
mov.l @r15+, r3
|
||||
mov.l @r15+, r4
|
||||
mov.l @r15+, r5
|
||||
mov.l @r15+, r6
|
||||
mov.l @r15+, r7
|
||||
stc sr, r8
|
||||
mov.l 1f, r9 ! BL =1, RB=1, IMASK=0x0F
|
||||
or r9, r8
|
||||
ldc r8, sr ! here, change the register bank
|
||||
mov.l @r15+, r8
|
||||
mov.l @r15+, r9
|
||||
mov.l @r15+, r10
|
||||
mov.l @r15+, r11
|
||||
mov.l @r15+, r12
|
||||
mov.l @r15+, r13
|
||||
mov.l @r15+, r14
|
||||
mov.l @r15+, k0
|
||||
ldc.l @r15+, spc
|
||||
lds.l @r15+, pr
|
||||
mov.l @r15+, k1
|
||||
ldc.l @r15+, gbr
|
||||
lds.l @r15+, mach
|
||||
lds.l @r15+, macl
|
||||
mov k0, r15
|
||||
mov.l 1f, r8
|
||||
bsr restore_regs
|
||||
nop
|
||||
|
||||
lds k2, pr ! restore pr
|
||||
mov k4, r15
|
||||
!
|
||||
mov.l 2f, k0
|
||||
mov.l @k0, k0
|
||||
jmp @k0
|
||||
ldc k1, ssr
|
||||
ldc k3, ssr
|
||||
.align 2
|
||||
1: .long 0x300000f0
|
||||
2: .long gdb_vbr_vector
|
||||
#endif /* CONFIG_SH_STANDARD_BIOS */
|
||||
|
||||
restore_all:
|
||||
! restore_regs()
|
||||
! - restore r0, r1, r2, r3, r4, r5, r6, r7 from the stack
|
||||
! - switch bank
|
||||
! - restore r8, r9, r10, r11, r12, r13, r14, r15 from the stack
|
||||
! - restore spc, pr*, ssr, gbr, mach, macl, skip default tra
|
||||
! k2 returns original pr
|
||||
! k3 returns original sr
|
||||
! k4 returns original stack pointer
|
||||
! r8 passes SR bitmask, overwritten with restored data on return
|
||||
! r9 trashed
|
||||
! BL=0 on entry, on exit BL=1 (depending on r8).
|
||||
|
||||
ENTRY(restore_regs)
|
||||
mov.l @r15+, r0
|
||||
mov.l @r15+, r1
|
||||
mov.l @r15+, r2
|
||||
|
@ -234,10 +226,9 @@ restore_all:
|
|||
mov.l @r15+, r6
|
||||
mov.l @r15+, r7
|
||||
!
|
||||
stc sr, r8
|
||||
mov.l 7f, r9
|
||||
or r9, r8 ! BL =1, RB=1
|
||||
ldc r8, sr ! here, change the register bank
|
||||
stc sr, r9
|
||||
or r8, r9
|
||||
ldc r9, sr
|
||||
!
|
||||
mov.l @r15+, r8
|
||||
mov.l @r15+, r9
|
||||
|
@ -248,12 +239,20 @@ restore_all:
|
|||
mov.l @r15+, r14
|
||||
mov.l @r15+, k4 ! original stack pointer
|
||||
ldc.l @r15+, spc
|
||||
lds.l @r15+, pr
|
||||
mov.l @r15+, k2 ! original PR
|
||||
mov.l @r15+, k3 ! original SR
|
||||
ldc.l @r15+, gbr
|
||||
lds.l @r15+, mach
|
||||
lds.l @r15+, macl
|
||||
rts
|
||||
add #4, r15 ! Skip syscall number
|
||||
|
||||
restore_all:
|
||||
mov.l 7f, r8
|
||||
bsr restore_regs
|
||||
nop
|
||||
|
||||
lds k2, pr ! restore pr
|
||||
!
|
||||
#ifdef CONFIG_SH_DSP
|
||||
mov.l @r15+, k0 ! DSP mode marker
|
||||
|
@ -294,7 +293,7 @@ skip_restore:
|
|||
mov #0xf0, k1
|
||||
extu.b k1, k1
|
||||
not k1, k1
|
||||
and k1, k2 ! Mask orignal SR value
|
||||
and k1, k2 ! Mask original SR value
|
||||
!
|
||||
mov k3, k0 ! Calculate IMASK-bits
|
||||
shlr2 k0
|
||||
|
@ -313,7 +312,6 @@ skip_restore:
|
|||
mov #0, k1
|
||||
mov.b k1, @k0
|
||||
#endif
|
||||
mov.l @r15+, k2 ! restore EXPEVT
|
||||
mov k4, r15
|
||||
rte
|
||||
nop
|
||||
|
@ -335,82 +333,56 @@ skip_restore:
|
|||
.balign 4096,0,4096
|
||||
ENTRY(vbr_base)
|
||||
.long 0
|
||||
!
|
||||
! 0x100: General exception vector
|
||||
!
|
||||
.balign 256,0,256
|
||||
general_exception:
|
||||
mov.l 1f, k2
|
||||
mov.l 2f, k3
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SHX3
|
||||
mov.l @k2, k2
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SHX3
|
||||
bra handle_exception
|
||||
sts pr, k3 ! save original pr value in k3
|
||||
#else
|
||||
mov.l 1f, k4
|
||||
mov.l @k4, k4
|
||||
|
||||
! Is EXPEVT larger than 0x800?
|
||||
mov #0x8, k0
|
||||
shll8 k0
|
||||
cmp/hs k0, k2
|
||||
cmp/hs k0, k4
|
||||
bf 0f
|
||||
|
||||
! then add 0x580 (k2 is 0xd80 or 0xda0)
|
||||
mov #0x58, k0
|
||||
shll2 k0
|
||||
shll2 k0
|
||||
add k0, k2
|
||||
add k0, k4
|
||||
0:
|
||||
bra handle_exception
|
||||
! Setup stack and save DSP context (k0 contains original r15 on return)
|
||||
bsr prepare_stack_save_dsp
|
||||
nop
|
||||
#else
|
||||
bra handle_exception
|
||||
mov.l @k2, k2
|
||||
|
||||
! Save registers / Switch to bank 0
|
||||
mov k4, k2 ! keep vector in k2
|
||||
mov.l 1f, k4 ! SR bits to clear in k4
|
||||
bsr save_regs ! needs original pr value in k3
|
||||
nop
|
||||
|
||||
bra handle_exception_special
|
||||
nop
|
||||
|
||||
.align 2
|
||||
1: .long EXPEVT
|
||||
#endif
|
||||
.align 2
|
||||
1: .long EXPEVT
|
||||
2: .long ret_from_exception
|
||||
!
|
||||
!
|
||||
|
||||
.balign 1024,0,1024
|
||||
tlb_miss:
|
||||
mov.l 1f, k2
|
||||
mov.l 4f, k3
|
||||
bra handle_exception
|
||||
mov.l @k2, k2
|
||||
!
|
||||
.balign 512,0,512
|
||||
interrupt:
|
||||
mov.l 3f, k3
|
||||
#if defined(CONFIG_KGDB)
|
||||
mov.l 2f, k2
|
||||
! Debounce (filter nested NMI)
|
||||
mov.l @k2, k0
|
||||
mov.l 5f, k1
|
||||
cmp/eq k1, k0
|
||||
bf 0f
|
||||
mov.l 6f, k1
|
||||
tas.b @k1
|
||||
bt 0f
|
||||
rte
|
||||
nop
|
||||
.align 2
|
||||
2: .long INTEVT
|
||||
5: .long NMI_VEC
|
||||
6: .long in_nmi
|
||||
0:
|
||||
#endif /* defined(CONFIG_KGDB) */
|
||||
bra handle_exception
|
||||
mov #-1, k2 ! interrupt exception marker
|
||||
|
||||
.align 2
|
||||
1: .long EXPEVT
|
||||
3: .long ret_from_irq
|
||||
4: .long ret_from_exception
|
||||
|
||||
!
|
||||
!
|
||||
.align 2
|
||||
ENTRY(handle_exception)
|
||||
! Using k0, k1 for scratch registers (r0_bank1, r1_bank),
|
||||
! save all registers onto stack.
|
||||
!
|
||||
! prepare_stack_save_dsp()
|
||||
! - roll back gRB
|
||||
! - switch to kernel stack
|
||||
! - save DSP
|
||||
! k0 returns original sp (after roll back)
|
||||
! k1 trashed
|
||||
! k2 trashed
|
||||
|
||||
prepare_stack_save_dsp:
|
||||
#ifdef CONFIG_GUSA
|
||||
! Check for roll back gRB (User and Kernel)
|
||||
mov r15, k0
|
||||
|
@ -430,7 +402,7 @@ ENTRY(handle_exception)
|
|||
2: mov k1, r15 ! SP = r1
|
||||
1:
|
||||
#endif
|
||||
|
||||
! Switch to kernel stack if needed
|
||||
stc ssr, k0 ! Is it from kernel space?
|
||||
shll k0 ! Check MD bit (bit30) by shifting it into...
|
||||
shll k0 ! ...the T bit
|
||||
|
@ -443,18 +415,17 @@ ENTRY(handle_exception)
|
|||
add current, k1
|
||||
mov k1, r15 ! change to kernel stack
|
||||
!
|
||||
1: mov.l 2f, k1
|
||||
!
|
||||
1:
|
||||
#ifdef CONFIG_SH_DSP
|
||||
mov.l r2, @-r15 ! Save r2, we need another reg
|
||||
stc sr, k4
|
||||
mov.l 1f, r2
|
||||
tst r2, k4 ! Check if in DSP mode
|
||||
mov.l @r15+, r2 ! Restore r2 now
|
||||
! Save DSP context if needed
|
||||
stc sr, k1
|
||||
mov #0x10, k2
|
||||
shll8 k2 ! DSP=1 (0x00001000)
|
||||
tst k2, k1 ! Check if in DSP mode (passed in k2)
|
||||
bt/s skip_save
|
||||
mov #0, k4 ! Set marker for no stack frame
|
||||
mov #0, k1 ! Set marker for no stack frame
|
||||
|
||||
mov r2, k4 ! Backup r2 (in k4) for later
|
||||
mov k2, k1 ! Save has-frame marker
|
||||
|
||||
! Save DSP registers on stack
|
||||
stc.l mod, @-r15
|
||||
|
@ -473,35 +444,74 @@ ENTRY(handle_exception)
|
|||
! as we're not at all interested in supporting ancient toolchains at
|
||||
! this point. -- PFM.
|
||||
|
||||
mov r15, r2
|
||||
mov r15, k2
|
||||
.word 0xf653 ! movs.l a1, @-r2
|
||||
.word 0xf6f3 ! movs.l a0g, @-r2
|
||||
.word 0xf6d3 ! movs.l a1g, @-r2
|
||||
.word 0xf6c3 ! movs.l m0, @-r2
|
||||
.word 0xf6e3 ! movs.l m1, @-r2
|
||||
mov r2, r15
|
||||
mov k2, r15
|
||||
|
||||
mov k4, r2 ! Restore r2
|
||||
mov.l 1f, k4 ! Force DSP stack frame
|
||||
skip_save:
|
||||
mov.l k4, @-r15 ! Push DSP mode marker onto stack
|
||||
mov.l k1, @-r15 ! Push DSP mode marker onto stack
|
||||
#endif
|
||||
! Save the user registers on the stack.
|
||||
mov.l k2, @-r15 ! EXPEVT
|
||||
rts
|
||||
nop
|
||||
!
|
||||
! 0x400: Instruction and Data TLB miss exception vector
|
||||
!
|
||||
.balign 1024,0,1024
|
||||
tlb_miss:
|
||||
sts pr, k3 ! save original pr value in k3
|
||||
|
||||
mov #-1, k4
|
||||
mov.l k4, @-r15 ! set TRA (default: -1)
|
||||
!
|
||||
handle_exception:
|
||||
mova exception_data, k0
|
||||
|
||||
! Setup stack and save DSP context (k0 contains original r15 on return)
|
||||
bsr prepare_stack_save_dsp
|
||||
PREF(k0)
|
||||
|
||||
! Save registers / Switch to bank 0
|
||||
mov.l 5f, k2 ! vector register address
|
||||
mov.l 1f, k4 ! SR bits to clear in k4
|
||||
bsr save_regs ! needs original pr value in k3
|
||||
mov.l @k2, k2 ! read out vector and keep in k2
|
||||
|
||||
handle_exception_special:
|
||||
! Setup return address and jump to exception handler
|
||||
mov.l 7f, r9 ! fetch return address
|
||||
stc r2_bank, r0 ! k2 (vector)
|
||||
mov.l 6f, r10
|
||||
shlr2 r0
|
||||
shlr r0
|
||||
mov.l @(r0, r10), r10
|
||||
jmp @r10
|
||||
lds r9, pr ! put return address in pr
|
||||
|
||||
.align L1_CACHE_SHIFT
|
||||
|
||||
! save_regs()
|
||||
! - save default tra, macl, mach, gbr, ssr, pr* and spc on the stack
|
||||
! - save r15*, r14, r13, r12, r11, r10, r9, r8 on the stack
|
||||
! - switch bank
|
||||
! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
|
||||
! k0 contains original stack pointer*
|
||||
! k1 trashed
|
||||
! k3 passes original pr*
|
||||
! k4 passes SR bitmask
|
||||
! BL=1 on entry, on exit BL=0.
|
||||
|
||||
ENTRY(save_regs)
|
||||
mov #-1, r1
|
||||
mov.l k1, @-r15 ! set TRA (default: -1)
|
||||
sts.l macl, @-r15
|
||||
sts.l mach, @-r15
|
||||
stc.l gbr, @-r15
|
||||
stc.l ssr, @-r15
|
||||
sts.l pr, @-r15
|
||||
mov.l k3, @-r15 ! original pr in k3
|
||||
stc.l spc, @-r15
|
||||
!
|
||||
lds k3, pr ! Set the return address to pr
|
||||
!
|
||||
mov.l k0, @-r15 ! save orignal stack
|
||||
|
||||
mov.l k0, @-r15 ! original stack pointer in k0
|
||||
mov.l r14, @-r15
|
||||
mov.l r13, @-r15
|
||||
mov.l r12, @-r15
|
||||
|
@ -509,13 +519,23 @@ skip_save:
|
|||
mov.l r10, @-r15
|
||||
mov.l r9, @-r15
|
||||
mov.l r8, @-r15
|
||||
!
|
||||
stc sr, r8 ! Back to normal register bank, and
|
||||
or k1, r8 ! Block all interrupts
|
||||
mov.l 3f, k1
|
||||
and k1, r8 ! ...
|
||||
ldc r8, sr ! ...changed here.
|
||||
!
|
||||
|
||||
mov.l 0f, k3 ! SR bits to set in k3
|
||||
|
||||
! fall-through
|
||||
|
||||
! save_low_regs()
|
||||
! - modify SR for bank switch
|
||||
! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
|
||||
! k3 passes bits to set in SR
|
||||
! k4 passes bits to clear in SR
|
||||
|
||||
ENTRY(save_low_regs)
|
||||
stc sr, r8
|
||||
or k3, r8
|
||||
and k4, r8
|
||||
ldc r8, sr
|
||||
|
||||
mov.l r7, @-r15
|
||||
mov.l r6, @-r15
|
||||
mov.l r5, @-r15
|
||||
|
@ -523,52 +543,63 @@ skip_save:
|
|||
mov.l r3, @-r15
|
||||
mov.l r2, @-r15
|
||||
mov.l r1, @-r15
|
||||
rts
|
||||
mov.l r0, @-r15
|
||||
|
||||
/*
|
||||
* This gets a bit tricky.. in the INTEVT case we don't want to use
|
||||
* the VBR offset as a destination in the jump call table, since all
|
||||
* of the destinations are the same. In this case, (interrupt) sets
|
||||
* a marker in r2 (now r2_bank since SR.RB changed), which we check
|
||||
* to determine the exception type. For all other exceptions, we
|
||||
* forcibly read EXPEVT from memory and fix up the jump address, in
|
||||
* the interrupt exception case we jump to do_IRQ() and defer the
|
||||
* INTEVT read until there. As a bonus, we can also clean up the SR.RB
|
||||
* checks that do_IRQ() was doing..
|
||||
*/
|
||||
stc r2_bank, r8
|
||||
cmp/pz r8
|
||||
bf interrupt_exception
|
||||
shlr2 r8
|
||||
shlr r8
|
||||
mov.l 4f, r9
|
||||
add r8, r9
|
||||
mov.l @r9, r9
|
||||
jmp @r9
|
||||
!
|
||||
! 0x600: Interrupt / NMI vector
|
||||
!
|
||||
.balign 512,0,512
|
||||
ENTRY(handle_interrupt)
|
||||
#if defined(CONFIG_KGDB)
|
||||
mov.l 2f, k2
|
||||
! Debounce (filter nested NMI)
|
||||
mov.l @k2, k0
|
||||
mov.l 9f, k1
|
||||
cmp/eq k1, k0
|
||||
bf 11f
|
||||
mov.l 10f, k1
|
||||
tas.b @k1
|
||||
bt 11f
|
||||
rte
|
||||
nop
|
||||
rts
|
||||
nop
|
||||
|
||||
.align 2
|
||||
1: .long 0x00001000 ! DSP=1
|
||||
2: .long 0x000080f0 ! FD=1, IMASK=15
|
||||
3: .long 0xcfffffff ! RB=0, BL=0
|
||||
4: .long exception_handling_table
|
||||
9: .long NMI_VEC
|
||||
10: .long in_nmi
|
||||
11:
|
||||
#endif /* defined(CONFIG_KGDB) */
|
||||
sts pr, k3 ! save original pr value in k3
|
||||
mova exception_data, k0
|
||||
|
||||
interrupt_exception:
|
||||
mov.l 1f, r9
|
||||
! Setup stack and save DSP context (k0 contains original r15 on return)
|
||||
bsr prepare_stack_save_dsp
|
||||
PREF(k0)
|
||||
|
||||
! Save registers / Switch to bank 0
|
||||
mov.l 1f, k4 ! SR bits to clear in k4
|
||||
bsr save_regs ! needs original pr value in k3
|
||||
mov #-1, k2 ! default vector kept in k2
|
||||
|
||||
! Setup return address and jump to do_IRQ
|
||||
mov.l 4f, r9 ! fetch return address
|
||||
lds r9, pr ! put return address in pr
|
||||
mov.l 2f, r4
|
||||
mov.l @r4, r4
|
||||
mov.l 3f, r9
|
||||
mov.l @r4, r4 ! pass INTEVT vector as arg0
|
||||
jmp @r9
|
||||
mov r15, r5
|
||||
rts
|
||||
nop
|
||||
mov r15, r5 ! pass saved registers as arg1
|
||||
|
||||
.align 2
|
||||
1: .long do_IRQ
|
||||
2: .long INTEVT
|
||||
|
||||
.align 2
|
||||
ENTRY(exception_none)
|
||||
rts
|
||||
nop
|
||||
|
||||
.align L1_CACHE_SHIFT
|
||||
exception_data:
|
||||
0: .long 0x000080f0 ! FD=1, IMASK=15
|
||||
1: .long 0xcfffffff ! RB=0, BL=0
|
||||
2: .long INTEVT
|
||||
3: .long do_IRQ
|
||||
4: .long ret_from_irq
|
||||
5: .long EXPEVT
|
||||
6: .long exception_handling_table
|
||||
7: .long ret_from_exception
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SH7705 Setup
|
||||
*
|
||||
* Copyright (C) 2006, 2007 Paul Mundt
|
||||
* Copyright (C) 2006 - 2009 Paul Mundt
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
|
@ -21,51 +21,36 @@ enum {
|
|||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
|
||||
PINT07, PINT815,
|
||||
DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
ADC_ADI,
|
||||
USB_USI0, USB_USI1,
|
||||
TPU0, TPU1, TPU2, TPU3,
|
||||
TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
|
||||
RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
WDT,
|
||||
REF_RCMI,
|
||||
|
||||
/* interrupt groups */
|
||||
RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
|
||||
DMAC, SCIF0, SCIF2, ADC_ADI, USB,
|
||||
|
||||
TPU0, TPU1, TPU2, TPU3,
|
||||
TMU0, TMU1, TMU2,
|
||||
|
||||
RTC, WDT, REF_RCMI,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
/* IRQ0->5 are handled in setup-sh3.c */
|
||||
INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
|
||||
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
|
||||
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
|
||||
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
|
||||
INTC_VECT(SCIF0_TXI, 0x8e0),
|
||||
INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
|
||||
INTC_VECT(SCIF2_TXI, 0x960),
|
||||
INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
|
||||
INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
|
||||
INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
|
||||
INTC_VECT(SCIF0, 0x8e0),
|
||||
INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
|
||||
INTC_VECT(SCIF2, 0x960),
|
||||
INTC_VECT(ADC_ADI, 0x980),
|
||||
INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40),
|
||||
INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
|
||||
INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
|
||||
INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
|
||||
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
||||
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
|
||||
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
|
||||
INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(WDT, 0x560),
|
||||
INTC_VECT(REF_RCMI, 0x580),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
|
||||
INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
|
||||
INTC_GROUP(USB, USB_USI0, USB_USI1),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
|
||||
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
|
||||
|
@ -78,7 +63,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups,
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
|
@ -86,12 +71,12 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xa4410000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 56, 57, 59 },
|
||||
.irqs = { 56, 56, 56 },
|
||||
}, {
|
||||
.mapbase = 0xa4400000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 52, 53, 55 },
|
||||
.irqs = { 52, 52, 52 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
@ -115,14 +100,6 @@ static struct resource rtc_resources[] = {
|
|||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_rtc_platform_info rtc_info = {
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* SH3 Setup code for SH7706, SH7707, SH7708, SH7709
|
||||
*
|
||||
* Copyright (C) 2007 Magnus Damm
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* Based on setup-sh7709.c
|
||||
*
|
||||
|
@ -24,46 +25,37 @@ enum {
|
|||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
|
||||
PINT07, PINT815,
|
||||
DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
|
||||
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
|
||||
SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
|
||||
ADC_ADI,
|
||||
DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
|
||||
LCDC, PCC0, PCC1,
|
||||
TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
|
||||
RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
WDT,
|
||||
REF_RCMI, REF_ROVI,
|
||||
|
||||
/* interrupt groups */
|
||||
RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
|
||||
TMU0, TMU1, TMU2,
|
||||
RTC, WDT, REF,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
||||
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500),
|
||||
INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540),
|
||||
INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
|
||||
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
|
||||
INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
|
||||
INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
|
||||
INTC_VECT(WDT, 0x560),
|
||||
INTC_VECT(REF_RCMI, 0x580),
|
||||
INTC_VECT(REF_ROVI, 0x5a0),
|
||||
INTC_VECT(REF, 0x580),
|
||||
INTC_VECT(REF, 0x5a0),
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
/* IRQ0->5 are handled in setup-sh3.c */
|
||||
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
|
||||
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
|
||||
INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
|
||||
INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
|
||||
INTC_VECT(ADC_ADI, 0x980),
|
||||
INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
|
||||
INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960),
|
||||
INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
|
||||
INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
|
||||
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
|
||||
INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
|
||||
INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
|
||||
INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
|
||||
INTC_VECT(LCDC, 0x9a0),
|
||||
|
@ -71,16 +63,6 @@ static struct intc_vect vectors[] __initdata = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
|
||||
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
|
||||
INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
|
||||
INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
|
||||
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
|
||||
|
@ -101,7 +83,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
|
@ -111,14 +93,6 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
@ -136,7 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xfffffe80,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCI,
|
||||
.irqs = { 23, 24, 25, 0 },
|
||||
.irqs = { 23, 23, 23, 0 },
|
||||
},
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
|
@ -145,7 +119,7 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xa4000150,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 56, 57, 59, 58 },
|
||||
.irqs = { 56, 56, 56, 56 },
|
||||
},
|
||||
#endif
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
|
@ -154,7 +128,7 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xa4000140,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_IRDA,
|
||||
.irqs = { 52, 53, 55, 54 },
|
||||
.irqs = { 52, 52, 52, 52 },
|
||||
},
|
||||
#endif
|
||||
{
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SH3 Setup code for SH7710, SH7712
|
||||
*
|
||||
* Copyright (C) 2006, 2007 Paul Mundt
|
||||
* Copyright (C) 2006 - 2009 Paul Mundt
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
|
@ -20,59 +20,40 @@ enum {
|
|||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
|
||||
DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
|
||||
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
|
||||
DMAC_DEI4, DMAC_DEI5,
|
||||
IPSEC,
|
||||
DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
|
||||
EDMAC0, EDMAC1, EDMAC2,
|
||||
SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
|
||||
SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
|
||||
TMU0, TMU1, TMU2,
|
||||
RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
WDT,
|
||||
REF,
|
||||
SIOF0, SIOF1,
|
||||
|
||||
/* interrupt groups */
|
||||
RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
|
||||
TMU0, TMU1, TMU2,
|
||||
RTC, WDT, REF,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
/* IRQ0->5 are handled in setup-sh3.c */
|
||||
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
|
||||
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
|
||||
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
|
||||
INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
|
||||
INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
|
||||
INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
|
||||
INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
|
||||
INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
|
||||
INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
|
||||
INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
|
||||
INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
|
||||
INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
|
||||
INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
|
||||
INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7710
|
||||
INTC_VECT(IPSEC, 0xbe0),
|
||||
#endif
|
||||
INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
|
||||
INTC_VECT(EDMAC2, 0xc40),
|
||||
INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
|
||||
INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
|
||||
INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
|
||||
INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
|
||||
INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
|
||||
INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
|
||||
INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
|
||||
INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
|
||||
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
||||
INTC_VECT(TMU2, 0x440),
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
|
||||
INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(WDT, 0x560),
|
||||
INTC_VECT(REF, 0x580),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
|
||||
INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
|
||||
INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
|
||||
INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
|
||||
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
|
||||
|
@ -85,7 +66,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
|
@ -98,14 +79,6 @@ static struct resource rtc_resources[] = {
|
|||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_rtc_platform_info rtc_info = {
|
||||
|
@ -127,12 +100,12 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xa4400000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 52, 53, 55, 54 },
|
||||
.irqs = { 52, 52, 52, 52 },
|
||||
}, {
|
||||
.mapbase = 0xa4410000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 56, 57, 59, 58 },
|
||||
.irqs = { 56, 56, 56, 56 },
|
||||
}, {
|
||||
|
||||
.flags = 0,
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* SH7720 Setup
|
||||
*
|
||||
* Copyright (C) 2007 Markus Brunner, Mark Jonas
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
|
||||
*
|
||||
|
@ -26,17 +27,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
@ -150,62 +141,49 @@ enum {
|
|||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
|
||||
TMU0, TMU1, TMU2, RTC,
|
||||
WDT, REF_RCMI, SIM,
|
||||
IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
|
||||
DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL,
|
||||
ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT,
|
||||
DMAC1, LCDC, SSL,
|
||||
ADC, DMAC2, USBFI, CMT,
|
||||
SCIF0, SCIF1,
|
||||
PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC,
|
||||
SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC,
|
||||
PINT07, PINT815, TPU, IIC,
|
||||
SIOF0, SIOF1, MMC, PCC,
|
||||
USBHI, AFEIF,
|
||||
H_UDI,
|
||||
/* interrupt groups */
|
||||
TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
/* IRQ0->5 are handled in setup-sh3.c */
|
||||
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
||||
INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480),
|
||||
INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500),
|
||||
INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540),
|
||||
INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
|
||||
INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
|
||||
INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
|
||||
INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
|
||||
/* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
|
||||
INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800),
|
||||
INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
|
||||
INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
|
||||
INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
|
||||
INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
|
||||
INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7720)
|
||||
INTC_VECT(SSL, 0x980),
|
||||
#endif
|
||||
INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40),
|
||||
INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
|
||||
INTC_VECT(USBHI, 0xa60),
|
||||
INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
|
||||
INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
|
||||
INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
|
||||
INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
|
||||
INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
|
||||
INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80),
|
||||
INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0),
|
||||
INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00),
|
||||
INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0),
|
||||
INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0),
|
||||
INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
|
||||
INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
|
||||
INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
|
||||
INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
|
||||
INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
|
||||
INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
|
||||
INTC_VECT(AFEIF, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU, TMU0, TMU1, TMU2),
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
|
||||
INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
|
||||
INTC_GROUP(USBFI, USBFI0, USBFI1),
|
||||
INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
|
||||
INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
|
||||
INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
|
||||
{ 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
|
||||
|
@ -219,7 +197,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
{ 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
|
|
147
arch/sh/kernel/cpu/sh3/swsusp.S
Normal file
147
arch/sh/kernel/cpu/sh3/swsusp.S
Normal file
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh3/swsusp.S
|
||||
*
|
||||
* Copyright (C) 2009 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/sys.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
#define k0 r0
|
||||
#define k1 r1
|
||||
#define k2 r2
|
||||
#define k3 r3
|
||||
#define k4 r4
|
||||
|
||||
! swsusp_arch_resume()
|
||||
! - copy restore_pblist pages
|
||||
! - restore registers from swsusp_arch_regs_cpu0
|
||||
|
||||
ENTRY(swsusp_arch_resume)
|
||||
mov.l 1f, r15
|
||||
mov.l 2f, r4
|
||||
mov.l @r4, r4
|
||||
|
||||
swsusp_copy_loop:
|
||||
mov r4, r0
|
||||
cmp/eq #0, r0
|
||||
bt swsusp_restore_regs
|
||||
|
||||
mov.l @(PBE_ADDRESS, r4), r2
|
||||
mov.l @(PBE_ORIG_ADDRESS, r4), r5
|
||||
|
||||
mov #(PAGE_SIZE >> 10), r3
|
||||
shll8 r3
|
||||
shlr2 r3 /* PAGE_SIZE / 16 */
|
||||
swsusp_copy_page:
|
||||
dt r3
|
||||
mov.l @r2+,r1 /* 16n+0 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
mov.l @r2+,r1 /* 16n+4 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
mov.l @r2+,r1 /* 16n+8 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
mov.l @r2+,r1 /* 16n+12 */
|
||||
mov.l r1,@r5
|
||||
bf/s swsusp_copy_page
|
||||
add #4,r5
|
||||
|
||||
bra swsusp_copy_loop
|
||||
mov.l @(PBE_NEXT, r4), r4
|
||||
|
||||
swsusp_restore_regs:
|
||||
! BL=0: R7->R0 is bank0
|
||||
mov.l 3f, r8
|
||||
mov.l 4f, r5
|
||||
jsr @r5
|
||||
nop
|
||||
|
||||
! BL=1: R7->R0 is bank1
|
||||
lds k2, pr
|
||||
ldc k3, ssr
|
||||
|
||||
mov.l @r15+, r0
|
||||
mov.l @r15+, r1
|
||||
mov.l @r15+, r2
|
||||
mov.l @r15+, r3
|
||||
mov.l @r15+, r4
|
||||
mov.l @r15+, r5
|
||||
mov.l @r15+, r6
|
||||
mov.l @r15+, r7
|
||||
|
||||
rte
|
||||
nop
|
||||
! BL=0: R7->R0 is bank0
|
||||
|
||||
.align 2
|
||||
1: .long swsusp_arch_regs_cpu0
|
||||
2: .long restore_pblist
|
||||
3: .long 0x20000000 ! RB=1
|
||||
4: .long restore_regs
|
||||
|
||||
! swsusp_arch_suspend()
|
||||
! - prepare pc for resume, return from function without swsusp_save on resume
|
||||
! - save registers in swsusp_arch_regs_cpu0
|
||||
! - call swsusp_save write suspend image
|
||||
|
||||
ENTRY(swsusp_arch_suspend)
|
||||
sts pr, r0 ! save pr in r0
|
||||
mov r15, r2 ! save sp in r2
|
||||
mov r8, r5 ! save r8 in r5
|
||||
stc sr, r1
|
||||
ldc r1, ssr ! save sr in ssr
|
||||
mov.l 1f, r1
|
||||
ldc r1, spc ! setup pc value for resuming
|
||||
mov.l 5f, r15 ! use swsusp_arch_regs_cpu0 as stack
|
||||
mov.l 6f, r3
|
||||
add r3, r15 ! save from top of structure
|
||||
|
||||
! BL=0: R7->R0 is bank0
|
||||
mov.l 2f, r3 ! get new SR value for bank1
|
||||
mov #0, r4
|
||||
mov.l 7f, r1
|
||||
jsr @r1 ! switch to bank1 and save bank1 r7->r0
|
||||
not r4, r4
|
||||
|
||||
! BL=1: R7->R0 is bank1
|
||||
stc r2_bank, k0 ! fetch old sp from r2_bank0
|
||||
mov.l 3f, k4 ! SR bits to clear in k4
|
||||
mov.l 8f, k1
|
||||
jsr @k1 ! switch to bank0 and save all regs
|
||||
stc r0_bank, k3 ! fetch old pr from r0_bank0
|
||||
|
||||
! BL=0: R7->R0 is bank0
|
||||
mov r2, r15 ! restore old sp
|
||||
mov r5, r8 ! restore old r8
|
||||
stc ssr, r1
|
||||
ldc r1, sr ! restore old sr
|
||||
lds r0, pr ! restore old pr
|
||||
mov.l 4f, r0
|
||||
jmp @r0
|
||||
nop
|
||||
|
||||
swsusp_call_save:
|
||||
mov r2, r15 ! restore old sp
|
||||
mov r5, r8 ! restore old r8
|
||||
lds r0, pr ! restore old pr
|
||||
rts
|
||||
mov #0, r0
|
||||
|
||||
.align 2
|
||||
1: .long swsusp_call_save
|
||||
2: .long 0x20000000 ! RB=1
|
||||
3: .long 0xdfffffff ! RB=0
|
||||
4: .long swsusp_save
|
||||
5: .long swsusp_arch_regs_cpu0
|
||||
6: .long SWSUSP_ARCH_REGS_SIZE
|
||||
7: .long save_low_regs
|
||||
8: .long save_regs
|
|
@ -5,6 +5,7 @@
|
|||
obj-y := probe.o common.o
|
||||
common-y += $(addprefix ../sh3/, entry.o ex.o)
|
||||
|
||||
obj-$(CONFIG_HIBERNATION) += $(addprefix ../sh3/, swsusp.o)
|
||||
obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o
|
||||
obj-$(CONFIG_SH_STORE_QUEUES) += sq.o
|
||||
|
||||
|
|
|
@ -129,6 +129,13 @@ int __init detect_cpu_and_cache_system(void)
|
|||
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
|
||||
CPU_HAS_LLSC;
|
||||
break;
|
||||
case 0x4004:
|
||||
boot_cpu_data.type = CPU_SH7786;
|
||||
boot_cpu_data.icache.ways = 4;
|
||||
boot_cpu_data.dcache.ways = 4;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
|
||||
CPU_HAS_LLSC | CPU_HAS_PTEAEX;
|
||||
break;
|
||||
case 0x3008:
|
||||
boot_cpu_data.icache.ways = 4;
|
||||
boot_cpu_data.dcache.ways = 4;
|
||||
|
|
|
@ -21,17 +21,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
@ -50,13 +40,13 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xffe00000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCI,
|
||||
.irqs = { 23, 24, 25, 0 },
|
||||
.irqs = { 23, 23, 23, 0 },
|
||||
}, {
|
||||
#endif
|
||||
.mapbase = 0xffe80000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
.irqs = { 40, 40, 40, 40 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
@ -87,43 +77,27 @@ enum {
|
|||
|
||||
/* interrupt sources */
|
||||
IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
|
||||
HUDI, GPIOI,
|
||||
DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
|
||||
DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
|
||||
DMAC_DMAE,
|
||||
HUDI, GPIOI, DMAC,
|
||||
PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
|
||||
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
|
||||
TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
|
||||
RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
|
||||
SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
|
||||
WDT,
|
||||
REF_RCMI, REF_ROVI,
|
||||
TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
|
||||
|
||||
/* interrupt groups */
|
||||
DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
|
||||
PCIC1,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
|
||||
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
||||
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
|
||||
INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
|
||||
INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
|
||||
INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
|
||||
INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
|
||||
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
|
||||
INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
|
||||
INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
|
||||
INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
|
||||
INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
|
||||
INTC_VECT(WDT, 0x560),
|
||||
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
|
||||
INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
|
||||
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
|
||||
INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
|
@ -136,7 +110,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
|
|||
PCIC1, PCIC0_PCISERR } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
|
||||
/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
|
||||
|
@ -145,39 +119,28 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
|
|||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7091)
|
||||
static struct intc_vect vectors_dma4[] __initdata = {
|
||||
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
|
||||
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
|
||||
INTC_VECT(DMAC_DMAE, 0x6c0),
|
||||
};
|
||||
|
||||
static struct intc_group groups_dma4[] __initdata = {
|
||||
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
|
||||
DMAC_DMTE3, DMAC_DMAE),
|
||||
INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
|
||||
INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
|
||||
INTC_VECT(DMAC, 0x6c0),
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
|
||||
vectors_dma4, groups_dma4,
|
||||
vectors_dma4, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
#endif
|
||||
|
||||
/* SH7750R and SH7751R both have 8-channel DMA controllers */
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
|
||||
static struct intc_vect vectors_dma8[] __initdata = {
|
||||
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
|
||||
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
|
||||
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
|
||||
INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
|
||||
INTC_VECT(DMAC_DMAE, 0x6c0),
|
||||
};
|
||||
|
||||
static struct intc_group groups_dma8[] __initdata = {
|
||||
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
|
||||
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
|
||||
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
|
||||
INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
|
||||
INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
|
||||
INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
|
||||
INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
|
||||
INTC_VECT(DMAC, 0x6c0),
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
|
||||
vectors_dma8, groups_dma8,
|
||||
vectors_dma8, NULL,
|
||||
NULL, prio_registers, NULL);
|
||||
#endif
|
||||
|
||||
|
|
|
@ -7,6 +7,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
|
|||
obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
|
||||
|
@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
|
|||
clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
|
||||
|
@ -31,6 +33,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
|
|||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
|
||||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
|
||||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
|
||||
pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
|
||||
|
||||
obj-y += $(clock-y)
|
||||
obj-$(CONFIG_SMP) += $(smp-y)
|
||||
|
|
148
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
Normal file
148
arch/sh/kernel/cpu/sh4a/clock-sh7786.c
Normal file
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
|
||||
*
|
||||
* SH7786 support for the clock framework
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on SH7785
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int ifc_divisors[] = { 1, 2, 4, 1 };
|
||||
static int sfc_divisors[] = { 1, 1, 4, 1 };
|
||||
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
|
||||
24, 32, 1, 1, 1, 1, 1, 1 };
|
||||
static int mfc_divisors[] = { 1, 1, 4, 1 };
|
||||
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
|
||||
24, 32, 1, 48, 1, 1, 1, 1 };
|
||||
|
||||
static void master_clk_init(struct clk *clk)
|
||||
{
|
||||
clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7786_master_clk_ops = {
|
||||
.init = master_clk_init,
|
||||
};
|
||||
|
||||
static void module_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = (ctrl_inl(FRQMR1) & 0x000f);
|
||||
clk->rate = clk->parent->rate / pfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7786_module_clk_ops = {
|
||||
.recalc = module_clk_recalc,
|
||||
};
|
||||
|
||||
static void bus_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
|
||||
clk->rate = clk->parent->rate / bfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7786_bus_clk_ops = {
|
||||
.recalc = bus_clk_recalc,
|
||||
};
|
||||
|
||||
static void cpu_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
|
||||
clk->rate = clk->parent->rate / ifc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7786_cpu_clk_ops = {
|
||||
.recalc = cpu_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk_ops *sh7786_clk_ops[] = {
|
||||
&sh7786_master_clk_ops,
|
||||
&sh7786_module_clk_ops,
|
||||
&sh7786_bus_clk_ops,
|
||||
&sh7786_cpu_clk_ops,
|
||||
};
|
||||
|
||||
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
|
||||
{
|
||||
if (idx < ARRAY_SIZE(sh7786_clk_ops))
|
||||
*ops = sh7786_clk_ops[idx];
|
||||
}
|
||||
|
||||
static void shyway_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
|
||||
clk->rate = clk->parent->rate / sfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7786_shyway_clk_ops = {
|
||||
.recalc = shyway_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk sh7786_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ALWAYS_ENABLED,
|
||||
.ops = &sh7786_shyway_clk_ops,
|
||||
};
|
||||
|
||||
static void ddr_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
|
||||
clk->rate = clk->parent->rate / mfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops sh7786_ddr_clk_ops = {
|
||||
.recalc = ddr_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk sh7786_ddr_clk = {
|
||||
.name = "ddr_clk",
|
||||
.flags = CLK_ALWAYS_ENABLED,
|
||||
.ops = &sh7786_ddr_clk_ops,
|
||||
};
|
||||
|
||||
/*
|
||||
* Additional SH7786-specific on-chip clocks that aren't already part of the
|
||||
* clock framework
|
||||
*/
|
||||
static struct clk *sh7786_onchip_clocks[] = {
|
||||
&sh7786_shyway_clk,
|
||||
&sh7786_ddr_clk,
|
||||
};
|
||||
|
||||
static int __init sh7786_clk_init(void)
|
||||
{
|
||||
struct clk *clk = clk_get(NULL, "master_clk");
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
|
||||
struct clk *clkp = sh7786_onchip_clocks[i];
|
||||
|
||||
clkp->parent = clk;
|
||||
clk_register(clkp);
|
||||
clk_enable(clkp);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that we have the rest of the clocks registered, we need to
|
||||
* force the parent clock to propagate so that these clocks will
|
||||
* automatically figure out their rate. We cheat by handing the
|
||||
* parent clock its current rate and forcing child propagation.
|
||||
*/
|
||||
clk_set_rate(clk, clk_get_rate(clk));
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(sh7786_clk_init);
|
950
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
Normal file
950
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
Normal file
|
@ -0,0 +1,950 @@
|
|||
/*
|
||||
* SH7786 Pinmux
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on SH7785 pinmux
|
||||
*
|
||||
* Copyright (C) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <cpu/sh7786.h>
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
||||
PINMUX_DATA_BEGIN,
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
|
||||
PE7_DATA, PE6_DATA,
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
|
||||
PG7_DATA, PG6_DATA, PG5_DATA,
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA,
|
||||
PINMUX_DATA_END,
|
||||
|
||||
PINMUX_INPUT_BEGIN,
|
||||
PA7_IN, PA6_IN, PA5_IN, PA4_IN,
|
||||
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
|
||||
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
|
||||
PB3_IN, PB2_IN, PB1_IN, PB0_IN,
|
||||
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
|
||||
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
|
||||
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
|
||||
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
|
||||
PE7_IN, PE6_IN,
|
||||
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
|
||||
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
|
||||
PG7_IN, PG6_IN, PG5_IN,
|
||||
PH7_IN, PH6_IN, PH5_IN, PH4_IN,
|
||||
PH3_IN, PH2_IN, PH1_IN, PH0_IN,
|
||||
PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
|
||||
PJ3_IN, PJ2_IN, PJ1_IN,
|
||||
PINMUX_INPUT_END,
|
||||
|
||||
PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
|
||||
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
|
||||
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
|
||||
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
|
||||
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
|
||||
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
|
||||
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
|
||||
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
|
||||
PE7_IN_PU, PE6_IN_PU,
|
||||
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
|
||||
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
|
||||
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
|
||||
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
|
||||
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
|
||||
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
|
||||
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
|
||||
PINMUX_INPUT_PULLUP_END,
|
||||
|
||||
PINMUX_OUTPUT_BEGIN,
|
||||
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
|
||||
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
|
||||
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
|
||||
PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
|
||||
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
|
||||
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
|
||||
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
|
||||
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
|
||||
PE7_OUT, PE6_OUT,
|
||||
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
|
||||
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
|
||||
PG7_OUT, PG6_OUT, PG5_OUT,
|
||||
PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
|
||||
PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
|
||||
PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
|
||||
PJ3_OUT, PJ2_OUT, PJ1_OUT,
|
||||
PINMUX_OUTPUT_END,
|
||||
|
||||
PINMUX_FUNCTION_BEGIN,
|
||||
PA7_FN, PA6_FN, PA5_FN, PA4_FN,
|
||||
PA3_FN, PA2_FN, PA1_FN, PA0_FN,
|
||||
PB7_FN, PB6_FN, PB5_FN, PB4_FN,
|
||||
PB3_FN, PB2_FN, PB1_FN, PB0_FN,
|
||||
PC7_FN, PC6_FN, PC5_FN, PC4_FN,
|
||||
PC3_FN, PC2_FN, PC1_FN, PC0_FN,
|
||||
PD7_FN, PD6_FN, PD5_FN, PD4_FN,
|
||||
PD3_FN, PD2_FN, PD1_FN, PD0_FN,
|
||||
PE7_FN, PE6_FN,
|
||||
PF7_FN, PF6_FN, PF5_FN, PF4_FN,
|
||||
PF3_FN, PF2_FN, PF1_FN, PF0_FN,
|
||||
PG7_FN, PG6_FN, PG5_FN,
|
||||
PH7_FN, PH6_FN, PH5_FN, PH4_FN,
|
||||
PH3_FN, PH2_FN, PH1_FN, PH0_FN,
|
||||
PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
|
||||
PJ3_FN, PJ2_FN, PJ1_FN,
|
||||
P1MSEL14_0, P1MSEL14_1,
|
||||
P1MSEL13_0, P1MSEL13_1,
|
||||
P1MSEL12_0, P1MSEL12_1,
|
||||
P1MSEL11_0, P1MSEL11_1,
|
||||
P1MSEL10_0, P1MSEL10_1,
|
||||
P1MSEL9_0, P1MSEL9_1,
|
||||
P1MSEL8_0, P1MSEL8_1,
|
||||
P1MSEL7_0, P1MSEL7_1,
|
||||
P1MSEL6_0, P1MSEL6_1,
|
||||
P1MSEL5_0, P1MSEL5_1,
|
||||
P1MSEL4_0, P1MSEL4_1,
|
||||
P1MSEL3_0, P1MSEL3_1,
|
||||
P1MSEL2_0, P1MSEL2_1,
|
||||
P1MSEL1_0, P1MSEL1_1,
|
||||
P1MSEL0_0, P1MSEL0_1,
|
||||
|
||||
P2MSEL15_0, P2MSEL15_1,
|
||||
P2MSEL14_0, P2MSEL14_1,
|
||||
P2MSEL13_0, P2MSEL13_1,
|
||||
P2MSEL12_0, P2MSEL12_1,
|
||||
P2MSEL11_0, P2MSEL11_1,
|
||||
P2MSEL10_0, P2MSEL10_1,
|
||||
P2MSEL9_0, P2MSEL9_1,
|
||||
P2MSEL8_0, P2MSEL8_1,
|
||||
P2MSEL7_0, P2MSEL7_1,
|
||||
P2MSEL6_0, P2MSEL6_1,
|
||||
P2MSEL5_0, P2MSEL5_1,
|
||||
P2MSEL4_0, P2MSEL4_1,
|
||||
P2MSEL3_0, P2MSEL3_1,
|
||||
P2MSEL2_0, P2MSEL2_1,
|
||||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1,
|
||||
PINMUX_FUNCTION_END,
|
||||
|
||||
PINMUX_MARK_BEGIN,
|
||||
CDE_MARK,
|
||||
ETH_MAGIC_MARK,
|
||||
DISP_MARK,
|
||||
ETH_LINK_MARK,
|
||||
DR5_MARK,
|
||||
ETH_TX_ER_MARK,
|
||||
DR4_MARK,
|
||||
ETH_TX_EN_MARK,
|
||||
DR3_MARK,
|
||||
ETH_TXD3_MARK,
|
||||
DR2_MARK,
|
||||
ETH_TXD2_MARK,
|
||||
DR1_MARK,
|
||||
ETH_TXD1_MARK,
|
||||
DR0_MARK,
|
||||
ETH_TXD0_MARK,
|
||||
|
||||
VSYNC_MARK,
|
||||
HSPI_CLK_MARK,
|
||||
ODDF_MARK,
|
||||
HSPI_CS_MARK,
|
||||
DG5_MARK,
|
||||
ETH_MDIO_MARK,
|
||||
DG4_MARK,
|
||||
ETH_RX_CLK_MARK,
|
||||
DG3_MARK,
|
||||
ETH_MDC_MARK,
|
||||
DG2_MARK,
|
||||
ETH_COL_MARK,
|
||||
DG1_MARK,
|
||||
ETH_TX_CLK_MARK,
|
||||
DG0_MARK,
|
||||
ETH_CRS_MARK,
|
||||
|
||||
DCLKIN_MARK,
|
||||
HSPI_RX_MARK,
|
||||
HSYNC_MARK,
|
||||
HSPI_TX_MARK,
|
||||
DB5_MARK,
|
||||
ETH_RXD3_MARK,
|
||||
DB4_MARK,
|
||||
ETH_RXD2_MARK,
|
||||
DB3_MARK,
|
||||
ETH_RXD1_MARK,
|
||||
DB2_MARK,
|
||||
ETH_RXD0_MARK,
|
||||
DB1_MARK,
|
||||
ETH_RX_DV_MARK,
|
||||
DB0_MARK,
|
||||
ETH_RX_ER_MARK,
|
||||
|
||||
DCLKOUT_MARK,
|
||||
SCIF1_SLK_MARK,
|
||||
SCIF1_RXD_MARK,
|
||||
SCIF1_TXD_MARK,
|
||||
DACK1_MARK,
|
||||
BACK_MARK,
|
||||
FALE_MARK,
|
||||
DACK0_MARK,
|
||||
FCLE_MARK,
|
||||
DREQ1_MARK,
|
||||
BREQ_MARK,
|
||||
USB_OVC1_MARK,
|
||||
DREQ0_MARK,
|
||||
USB_OVC0_MARK,
|
||||
|
||||
USB_PENC1_MARK,
|
||||
USB_PENC0_MARK,
|
||||
|
||||
HAC1_SDOUT_MARK,
|
||||
SSI1_SDATA_MARK,
|
||||
SDIF1CMD_MARK,
|
||||
HAC1_SDIN_MARK,
|
||||
SSI1_SCK_MARK,
|
||||
SDIF1CD_MARK,
|
||||
HAC1_SYNC_MARK,
|
||||
SSI1_WS_MARK,
|
||||
SDIF1WP_MARK,
|
||||
HAC1_BITCLK_MARK,
|
||||
SSI1_CLK_MARK,
|
||||
SDIF1CLK_MARK,
|
||||
HAC0_SDOUT_MARK,
|
||||
SSI0_SDATA_MARK,
|
||||
SDIF1D3_MARK,
|
||||
HAC0_SDIN_MARK,
|
||||
SSI0_SCK_MARK,
|
||||
SDIF1D2_MARK,
|
||||
HAC0_SYNC_MARK,
|
||||
SSI0_WS_MARK,
|
||||
SDIF1D1_MARK,
|
||||
HAC0_BITCLK_MARK,
|
||||
SSI0_CLK_MARK,
|
||||
SDIF1D0_MARK,
|
||||
|
||||
SCIF3_SCK_MARK,
|
||||
SSI2_SDATA_MARK,
|
||||
SCIF3_RXD_MARK,
|
||||
TCLK_MARK,
|
||||
SSI2_SCK_MARK,
|
||||
SCIF3_TXD_MARK,
|
||||
HAC_RES_MARK,
|
||||
SSI2_WS_MARK,
|
||||
|
||||
DACK3_MARK,
|
||||
SDIF0CMD_MARK,
|
||||
DACK2_MARK,
|
||||
SDIF0CD_MARK,
|
||||
DREQ3_MARK,
|
||||
SDIF0WP_MARK,
|
||||
SCIF0_CTS_MARK,
|
||||
DREQ2_MARK,
|
||||
SDIF0CLK_MARK,
|
||||
SCIF0_RTS_MARK,
|
||||
IRL7_MARK,
|
||||
SDIF0D3_MARK,
|
||||
SCIF0_SCK_MARK,
|
||||
IRL6_MARK,
|
||||
SDIF0D2_MARK,
|
||||
SCIF0_RXD_MARK,
|
||||
IRL5_MARK,
|
||||
SDIF0D1_MARK,
|
||||
SCIF0_TXD_MARK,
|
||||
IRL4_MARK,
|
||||
SDIF0D0_MARK,
|
||||
|
||||
SCIF5_SCK_MARK,
|
||||
FRB_MARK,
|
||||
SCIF5_RXD_MARK,
|
||||
IOIS16_MARK,
|
||||
SCIF5_TXD_MARK,
|
||||
CE2B_MARK,
|
||||
DRAK3_MARK,
|
||||
CE2A_MARK,
|
||||
SCIF4_SCK_MARK,
|
||||
DRAK2_MARK,
|
||||
SSI3_WS_MARK,
|
||||
SCIF4_RXD_MARK,
|
||||
DRAK1_MARK,
|
||||
SSI3_SDATA_MARK,
|
||||
FSTATUS_MARK,
|
||||
SCIF4_TXD_MARK,
|
||||
DRAK0_MARK,
|
||||
SSI3_SCK_MARK,
|
||||
FSE_MARK,
|
||||
PINMUX_MARK_END,
|
||||
};
|
||||
|
||||
static pinmux_enum_t pinmux_data[] = {
|
||||
|
||||
/* PA GPIO */
|
||||
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
|
||||
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
|
||||
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
|
||||
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
|
||||
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
|
||||
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
|
||||
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
|
||||
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
|
||||
|
||||
/* PB GPIO */
|
||||
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
|
||||
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
|
||||
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
|
||||
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
|
||||
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
|
||||
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
|
||||
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
|
||||
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
|
||||
|
||||
/* PC GPIO */
|
||||
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
|
||||
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
|
||||
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
|
||||
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
|
||||
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
|
||||
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
|
||||
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
|
||||
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
|
||||
|
||||
/* PD GPIO */
|
||||
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
|
||||
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
|
||||
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
|
||||
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
|
||||
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
|
||||
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
|
||||
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
|
||||
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
|
||||
|
||||
/* PE GPIO */
|
||||
PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
|
||||
PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
|
||||
|
||||
/* PF GPIO */
|
||||
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
|
||||
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
|
||||
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
|
||||
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
|
||||
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
|
||||
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
|
||||
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
|
||||
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
|
||||
|
||||
/* PG GPIO */
|
||||
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
|
||||
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
|
||||
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
|
||||
|
||||
/* PH GPIO */
|
||||
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
|
||||
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
|
||||
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
|
||||
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
|
||||
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
|
||||
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
|
||||
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
|
||||
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
|
||||
|
||||
/* PJ GPIO */
|
||||
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
|
||||
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
|
||||
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
|
||||
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
|
||||
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
|
||||
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
|
||||
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
|
||||
|
||||
/* PA FN */
|
||||
PINMUX_MARK_BEGIN,
|
||||
PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
|
||||
PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
|
||||
PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
|
||||
PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
|
||||
PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
|
||||
PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
|
||||
PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
|
||||
PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
|
||||
PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
|
||||
PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
|
||||
PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
|
||||
PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
|
||||
PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
|
||||
PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
|
||||
PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
|
||||
PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
|
||||
|
||||
/* PB FN */
|
||||
PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
|
||||
PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
|
||||
PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
|
||||
PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
|
||||
PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
|
||||
PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
|
||||
PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
|
||||
PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
|
||||
PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
|
||||
PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
|
||||
PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
|
||||
PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
|
||||
PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
|
||||
PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
|
||||
PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
|
||||
PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
|
||||
|
||||
/* PC FN */
|
||||
PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
|
||||
PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
|
||||
PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
|
||||
PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
|
||||
PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
|
||||
PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
|
||||
PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
|
||||
PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
|
||||
|
||||
PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
|
||||
PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
|
||||
PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
|
||||
PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
|
||||
PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
|
||||
PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
|
||||
PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
|
||||
PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
|
||||
|
||||
/* PD FN */
|
||||
PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
|
||||
PINMUX_DATA(SCIF1_SLK_MARK, PD6_FN),
|
||||
PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
|
||||
PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
|
||||
PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
|
||||
PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
|
||||
PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
|
||||
PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
|
||||
PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
|
||||
PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
|
||||
PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
|
||||
PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
|
||||
PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
|
||||
PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
|
||||
|
||||
/* PE FN */
|
||||
PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
|
||||
PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
|
||||
|
||||
/* PF FN */
|
||||
PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
|
||||
PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
|
||||
PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
|
||||
PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
|
||||
PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
|
||||
PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
|
||||
PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
|
||||
PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
|
||||
PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
|
||||
PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
|
||||
PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
|
||||
PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
|
||||
PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
|
||||
PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
|
||||
PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
|
||||
PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
|
||||
PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
|
||||
PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
|
||||
PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
|
||||
PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
|
||||
PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
|
||||
PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
|
||||
PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
|
||||
PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
|
||||
|
||||
/* PG FN */
|
||||
PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
|
||||
PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
|
||||
PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
|
||||
PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
|
||||
PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
|
||||
PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
|
||||
PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
|
||||
PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
|
||||
|
||||
/* PH FN */
|
||||
PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
|
||||
PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
|
||||
PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
|
||||
PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
|
||||
PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
|
||||
PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
|
||||
PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
|
||||
PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
|
||||
PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
|
||||
PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
|
||||
PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
|
||||
PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
|
||||
PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
|
||||
PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
|
||||
PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
|
||||
PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
|
||||
PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
|
||||
PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
|
||||
PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
|
||||
PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
|
||||
PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
|
||||
|
||||
/* PJ FN */
|
||||
PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
|
||||
PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
|
||||
PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
|
||||
PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
|
||||
PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
|
||||
PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
|
||||
PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
|
||||
PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
|
||||
PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
|
||||
PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
|
||||
PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
|
||||
PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
|
||||
PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
|
||||
PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
|
||||
PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
|
||||
PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
|
||||
PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
|
||||
PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
|
||||
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
|
||||
};
|
||||
|
||||
static struct pinmux_gpio pinmux_gpios[] = {
|
||||
/* PA */
|
||||
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
|
||||
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
|
||||
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
|
||||
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
|
||||
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
|
||||
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
|
||||
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
|
||||
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
|
||||
|
||||
/* PB */
|
||||
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
|
||||
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
|
||||
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
|
||||
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
|
||||
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
|
||||
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
|
||||
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
|
||||
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
|
||||
|
||||
/* PC */
|
||||
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
|
||||
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
|
||||
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
|
||||
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
|
||||
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
|
||||
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
|
||||
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
|
||||
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
|
||||
|
||||
/* PD */
|
||||
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
|
||||
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
|
||||
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
|
||||
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
|
||||
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
|
||||
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
|
||||
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
|
||||
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
|
||||
|
||||
/* PE */
|
||||
PINMUX_GPIO(GPIO_PE5, PE7_DATA),
|
||||
PINMUX_GPIO(GPIO_PE4, PE6_DATA),
|
||||
|
||||
/* PF */
|
||||
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
|
||||
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
|
||||
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
|
||||
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
|
||||
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
|
||||
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
|
||||
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
|
||||
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
|
||||
|
||||
/* PG */
|
||||
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
|
||||
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
|
||||
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
|
||||
|
||||
/* PH */
|
||||
PINMUX_GPIO(GPIO_PH7, PH7_DATA),
|
||||
PINMUX_GPIO(GPIO_PH6, PH6_DATA),
|
||||
PINMUX_GPIO(GPIO_PH5, PH5_DATA),
|
||||
PINMUX_GPIO(GPIO_PH4, PH4_DATA),
|
||||
PINMUX_GPIO(GPIO_PH3, PH3_DATA),
|
||||
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
|
||||
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
|
||||
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
|
||||
|
||||
/* PJ */
|
||||
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
|
||||
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
|
||||
|
||||
/* FN */
|
||||
PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_SLK, SCIF1_SLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
|
||||
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
|
||||
};
|
||||
|
||||
static struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
|
||||
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
|
||||
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
|
||||
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
|
||||
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
|
||||
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
|
||||
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
|
||||
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
|
||||
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
|
||||
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
|
||||
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
|
||||
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
|
||||
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
|
||||
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
|
||||
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
|
||||
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
|
||||
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
|
||||
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
|
||||
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
|
||||
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
|
||||
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
|
||||
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
|
||||
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
|
||||
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
|
||||
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
|
||||
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
|
||||
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
|
||||
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
|
||||
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
|
||||
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
|
||||
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
|
||||
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
|
||||
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
|
||||
PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
|
||||
PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
|
||||
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
|
||||
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
|
||||
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
|
||||
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
|
||||
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
|
||||
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
|
||||
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
|
||||
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
|
||||
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
|
||||
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
|
||||
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
|
||||
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
|
||||
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
|
||||
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
|
||||
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
|
||||
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
|
||||
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
|
||||
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
|
||||
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
|
||||
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
|
||||
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
|
||||
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
|
||||
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
|
||||
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
|
||||
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
|
||||
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
|
||||
0, 0, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
|
||||
0, 0,
|
||||
P1MSEL14_0, P1MSEL14_1,
|
||||
P1MSEL13_0, P1MSEL13_1,
|
||||
P1MSEL12_0, P1MSEL12_1,
|
||||
P1MSEL11_0, P1MSEL11_1,
|
||||
P1MSEL10_0, P1MSEL10_1,
|
||||
P1MSEL9_0, P1MSEL9_1,
|
||||
P1MSEL8_0, P1MSEL8_1,
|
||||
P1MSEL7_0, P1MSEL7_1,
|
||||
P1MSEL6_0, P1MSEL6_1,
|
||||
P1MSEL5_0, P1MSEL5_1,
|
||||
P1MSEL4_0, P1MSEL4_1,
|
||||
P1MSEL3_0, P1MSEL3_1,
|
||||
P1MSEL2_0, P1MSEL2_1,
|
||||
P1MSEL1_0, P1MSEL1_1,
|
||||
P1MSEL0_0, P1MSEL0_1 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
|
||||
P2MSEL15_0, P2MSEL15_1,
|
||||
P2MSEL14_0, P2MSEL14_1,
|
||||
P2MSEL13_0, P2MSEL13_1,
|
||||
P2MSEL12_0, P2MSEL12_1,
|
||||
P2MSEL11_0, P2MSEL11_1,
|
||||
P2MSEL10_0, P2MSEL10_1,
|
||||
P2MSEL9_0, P2MSEL9_1,
|
||||
P2MSEL8_0, P2MSEL8_1,
|
||||
P2MSEL7_0, P2MSEL7_1,
|
||||
P2MSEL6_0, P2MSEL6_1,
|
||||
P2MSEL5_0, P2MSEL5_1,
|
||||
P2MSEL4_0, P2MSEL4_1,
|
||||
P2MSEL3_0, P2MSEL3_1,
|
||||
P2MSEL2_0, P2MSEL2_1,
|
||||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1 }
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
static struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
|
||||
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
|
||||
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
|
||||
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
|
||||
PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
|
||||
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
|
||||
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
|
||||
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
|
||||
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
|
||||
PE7_DATA, PE6_DATA,
|
||||
0, 0, 0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
|
||||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
|
||||
PG7_DATA, PG6_DATA, PG5_DATA, 0,
|
||||
0, 0, 0, 0 }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
|
||||
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
|
||||
},
|
||||
{ PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
|
||||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct pinmux_info sh7786_pinmux_info = {
|
||||
.name = "sh7786_pfc",
|
||||
.reserved_id = PINMUX_RESERVED,
|
||||
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
|
||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
|
||||
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
.first_gpio = GPIO_PA7,
|
||||
.last_gpio = GPIO_FN_FSE,
|
||||
|
||||
.gpios = pinmux_gpios,
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.data_regs = pinmux_data_regs,
|
||||
|
||||
.gpio_data = pinmux_data,
|
||||
.gpio_data_size = ARRAY_SIZE(pinmux_data),
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return register_pinmux(&sh7786_pinmux_info);
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/uio_driver.h>
|
||||
#include <linux/sh_cmt.h>
|
||||
#include <asm/clock.h>
|
||||
|
||||
static struct resource iic0_resources[] = {
|
||||
|
@ -140,6 +141,38 @@ static struct platform_device jpu_device = {
|
|||
.num_resources = ARRAY_SIZE(jpu_resources),
|
||||
};
|
||||
|
||||
static struct sh_cmt_config cmt_platform_data = {
|
||||
.name = "CMT",
|
||||
.channel_offset = 0x60,
|
||||
.timer_bit = 5,
|
||||
.clk = "cmt0",
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT",
|
||||
.start = 0x044a0060,
|
||||
.end = 0x044a006b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 104,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffe00000,
|
||||
|
@ -175,6 +208,7 @@ static struct platform_device sci_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *sh7343_devices[] __initdata = {
|
||||
&cmt_device,
|
||||
&iic0_device,
|
||||
&iic1_device,
|
||||
&sci_device,
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/uio_driver.h>
|
||||
#include <linux/sh_cmt.h>
|
||||
#include <asm/clock.h>
|
||||
|
||||
static struct resource iic_resources[] = {
|
||||
|
@ -147,6 +148,38 @@ static struct platform_device veu1_device = {
|
|||
.num_resources = ARRAY_SIZE(veu1_resources),
|
||||
};
|
||||
|
||||
static struct sh_cmt_config cmt_platform_data = {
|
||||
.name = "CMT",
|
||||
.channel_offset = 0x60,
|
||||
.timer_bit = 5,
|
||||
.clk = "cmt0",
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT",
|
||||
.start = 0x044a0060,
|
||||
.end = 0x044a006b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 104,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffe00000,
|
||||
|
@ -167,6 +200,7 @@ static struct platform_device sci_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *sh7366_devices[] __initdata = {
|
||||
&cmt_device,
|
||||
&iic_device,
|
||||
&sci_device,
|
||||
&usb_host_device,
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/serial_sci.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/uio_driver.h>
|
||||
#include <linux/sh_cmt.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
|
@ -176,6 +177,38 @@ static struct platform_device jpu_device = {
|
|||
.num_resources = ARRAY_SIZE(jpu_resources),
|
||||
};
|
||||
|
||||
static struct sh_cmt_config cmt_platform_data = {
|
||||
.name = "CMT",
|
||||
.channel_offset = 0x60,
|
||||
.timer_bit = 5,
|
||||
.clk = "cmt0",
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT",
|
||||
.start = 0x044a0060,
|
||||
.end = 0x044a006b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 104,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffe00000,
|
||||
|
@ -209,6 +242,7 @@ static struct platform_device sci_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *sh7722_devices[] __initdata = {
|
||||
&cmt_device,
|
||||
&rtc_device,
|
||||
&usbf_device,
|
||||
&iic_device,
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/uio_driver.h>
|
||||
#include <linux/sh_cmt.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
|
@ -100,6 +101,38 @@ static struct platform_device veu1_device = {
|
|||
.num_resources = ARRAY_SIZE(veu1_resources),
|
||||
};
|
||||
|
||||
static struct sh_cmt_config cmt_platform_data = {
|
||||
.name = "CMT",
|
||||
.channel_offset = 0x60,
|
||||
.timer_bit = 5,
|
||||
.clk = "cmt0",
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT",
|
||||
.start = 0x044a0060,
|
||||
.end = 0x044a006b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 104,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffe00000,
|
||||
|
@ -221,6 +254,7 @@ static struct platform_device iic_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *sh7723_devices[] __initdata = {
|
||||
&cmt_device,
|
||||
&sci_device,
|
||||
&rtc_device,
|
||||
&iic_device,
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* Copyright (C) 2006 Paul Mundt
|
||||
* Copyright (C) 2007 Yoshihiro Shimoda
|
||||
* Copyright (C) 2008 Nobuhiro Iwamatsu
|
||||
* Copyright (C) 2008, 2009 Nobuhiro Iwamatsu
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
@ -22,17 +22,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
@ -50,17 +40,17 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xffe00000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
.irqs = { 40, 40, 40, 40 },
|
||||
}, {
|
||||
.mapbase = 0xffe08000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 76, 77, 79, 78 },
|
||||
.irqs = { 76, 76, 76, 76 },
|
||||
}, {
|
||||
.mapbase = 0xffe10000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 104, 105, 107, 106 },
|
||||
.irqs = { 104, 104, 104, 104 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
@ -148,93 +138,65 @@ enum {
|
|||
IRL_HHLL, IRL_HHLH, IRL_HHHL,
|
||||
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI, LCDC,
|
||||
DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
|
||||
DMAC0_DMINT4, DMAC0_DMINT5,
|
||||
IIC0, IIC1,
|
||||
CMT,
|
||||
GEINT0, GEINT1, GEINT2,
|
||||
HAC,
|
||||
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
|
||||
PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
|
||||
STIF0, STIF1,
|
||||
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
|
||||
SIOF0, SIOF1, SIOF2,
|
||||
USBH, USBFI0, USBFI1,
|
||||
TPU, PCC,
|
||||
MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
|
||||
SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
|
||||
RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
|
||||
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
|
||||
STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
|
||||
USBH, USBF, TPU, PCC, MMCIF, SIM,
|
||||
TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
|
||||
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
|
||||
GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
|
||||
SCIF2, GPIO,
|
||||
|
||||
/* interrupt groups */
|
||||
|
||||
TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5,
|
||||
SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
|
||||
TMU012, TMU345,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
|
||||
INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
|
||||
INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
|
||||
INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
|
||||
INTC_VECT(LCDC, 0x620),
|
||||
INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
|
||||
INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
|
||||
INTC_VECT(DMAC0_DMAE, 0x6c0),
|
||||
INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
|
||||
INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
|
||||
INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
|
||||
INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
|
||||
INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
|
||||
INTC_VECT(DMAC, 0x6c0),
|
||||
INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
|
||||
INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
|
||||
INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
|
||||
INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
|
||||
INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920),
|
||||
INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960),
|
||||
INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
|
||||
INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
|
||||
INTC_VECT(HAC, 0x980),
|
||||
INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
|
||||
INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
|
||||
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
|
||||
INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
|
||||
INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
|
||||
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
|
||||
INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
|
||||
INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
|
||||
INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
|
||||
INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
|
||||
INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
|
||||
INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
|
||||
INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
|
||||
INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
|
||||
INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80),
|
||||
INTC_VECT(USBFI1, 0xca0),
|
||||
INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
|
||||
INTC_VECT(USBF, 0xca0),
|
||||
INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
|
||||
INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
|
||||
INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
|
||||
INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0),
|
||||
INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0),
|
||||
INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
|
||||
INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
|
||||
INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
|
||||
INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
|
||||
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
|
||||
INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
|
||||
INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
|
||||
INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
|
||||
INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20),
|
||||
INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60),
|
||||
INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0),
|
||||
INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0),
|
||||
INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
|
||||
INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
|
||||
INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
|
||||
INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
|
||||
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
|
||||
INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
|
||||
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
|
||||
INTC_GROUP(USBF, USBFI0, USBFI1),
|
||||
INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
|
||||
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
|
||||
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
|
||||
INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
|
|
|
@ -20,17 +20,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 21,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 22,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 20,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
@ -48,12 +38,12 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xffe00000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
.irqs = { 40, 40, 40, 40 },
|
||||
}, {
|
||||
.mapbase = 0xffe10000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 76, 77, 79, 78 },
|
||||
.irqs = { 76, 76, 76, 76 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
@ -90,82 +80,55 @@ enum {
|
|||
IRL_HHLL, IRL_HHLH, IRL_HHHL,
|
||||
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
RTC_ATI, RTC_PRI, RTC_CUI,
|
||||
WDT,
|
||||
TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI,
|
||||
DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
|
||||
DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
|
||||
CMT, HAC,
|
||||
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
|
||||
PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
|
||||
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
|
||||
SIOF, HSPI,
|
||||
MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
|
||||
DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
|
||||
TMU3, TMU4, TMU5,
|
||||
SSI,
|
||||
FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
|
||||
GPIOI0, GPIOI1, GPIOI2, GPIOI3,
|
||||
RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
|
||||
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
|
||||
SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
|
||||
|
||||
/* interrupt groups */
|
||||
|
||||
RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1,
|
||||
PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
|
||||
TMU012, TMU345,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
|
||||
INTC_VECT(RTC_CUI, 0x4c0),
|
||||
INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
|
||||
INTC_VECT(RTC, 0x4c0),
|
||||
INTC_VECT(WDT, 0x560),
|
||||
INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
|
||||
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
|
||||
INTC_VECT(HUDI, 0x600),
|
||||
INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
|
||||
INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
|
||||
INTC_VECT(DMAC0_DMAE, 0x6c0),
|
||||
INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
|
||||
INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
|
||||
INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
|
||||
INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0),
|
||||
INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
|
||||
INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
|
||||
INTC_VECT(DMAC0, 0x6c0),
|
||||
INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
|
||||
INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
|
||||
INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
|
||||
INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
|
||||
INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
|
||||
INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
|
||||
INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
|
||||
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
|
||||
INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
|
||||
INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
|
||||
INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
|
||||
INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
|
||||
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
|
||||
INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
|
||||
INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
|
||||
INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
|
||||
INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
|
||||
INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
|
||||
INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
|
||||
INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
|
||||
INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0),
|
||||
INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0),
|
||||
INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
|
||||
INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
|
||||
INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
|
||||
INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
|
||||
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
|
||||
INTC_VECT(TMU5, 0xe40),
|
||||
INTC_VECT(SSI, 0xe80),
|
||||
INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
|
||||
INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
|
||||
INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
|
||||
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
|
||||
INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
|
||||
INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
|
||||
INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
|
||||
INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
|
||||
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
|
||||
DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
|
||||
INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
|
||||
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
|
||||
INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
|
||||
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
|
||||
INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
|
||||
FLCTL_FLTRQ0, FLCTL_FLTRQ1),
|
||||
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
|
|
|
@ -20,18 +20,13 @@ static struct plat_sci_port sci_platform_data[] = {
|
|||
.mapbase = 0xffea0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
.irqs = { 40, 40, 40, 40 },
|
||||
}, {
|
||||
.mapbase = 0xffeb0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 44, 45, 47, 46 },
|
||||
},
|
||||
|
||||
/*
|
||||
* The rest of these all have multiplexed IRQs
|
||||
*/
|
||||
{
|
||||
.irqs = { 44, 44, 44, 44 },
|
||||
}, {
|
||||
.mapbase = 0xffec0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
|
@ -91,33 +86,19 @@ enum {
|
|||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
|
||||
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
WDT,
|
||||
TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI,
|
||||
DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
|
||||
DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
|
||||
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
|
||||
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
|
||||
DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
|
||||
DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
|
||||
HSPI,
|
||||
WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
|
||||
HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
|
||||
SCIF2, SCIF3, SCIF4, SCIF5,
|
||||
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
|
||||
PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
|
||||
SIOF,
|
||||
MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
|
||||
DU,
|
||||
GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
|
||||
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
|
||||
SIOF, MMCIF, DU, GDTA,
|
||||
TMU3, TMU4, TMU5,
|
||||
SSI0, SSI1,
|
||||
HAC0, HAC1,
|
||||
FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
|
||||
GPIOI0, GPIOI1, GPIOI2, GPIOI3,
|
||||
FLCTL, GPIO,
|
||||
|
||||
/* interrupt groups */
|
||||
|
||||
TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
|
||||
PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
|
||||
TMU012, TMU345
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
|
@ -125,57 +106,45 @@ static struct intc_vect vectors[] __initdata = {
|
|||
INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
|
||||
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
|
||||
INTC_VECT(HUDI, 0x600),
|
||||
INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
|
||||
INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
|
||||
INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
|
||||
INTC_VECT(DMAC0_DMAE, 0x6e0),
|
||||
INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
|
||||
INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
|
||||
INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
|
||||
INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
|
||||
INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
|
||||
INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
|
||||
INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
|
||||
INTC_VECT(DMAC1_DMAE, 0x940),
|
||||
INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
|
||||
INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
|
||||
INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
|
||||
INTC_VECT(DMAC0, 0x6e0),
|
||||
INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
|
||||
INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
|
||||
INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
|
||||
INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
|
||||
INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
|
||||
INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
|
||||
INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
|
||||
INTC_VECT(DMAC1, 0x940),
|
||||
INTC_VECT(HSPI, 0x960),
|
||||
INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
|
||||
INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
|
||||
INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
|
||||
INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
|
||||
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
|
||||
INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
|
||||
INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
|
||||
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
|
||||
INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
|
||||
INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
|
||||
INTC_VECT(SIOF, 0xc00),
|
||||
INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
|
||||
INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
|
||||
INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
|
||||
INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
|
||||
INTC_VECT(DU, 0xd80),
|
||||
INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
|
||||
INTC_VECT(GDTA_GAERI, 0xde0),
|
||||
INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
|
||||
INTC_VECT(GDTA, 0xde0),
|
||||
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
|
||||
INTC_VECT(TMU5, 0xe40),
|
||||
INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
|
||||
INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
|
||||
INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
|
||||
INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
|
||||
INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
|
||||
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
|
||||
INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
|
||||
INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
|
||||
INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
|
||||
INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
|
||||
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
|
||||
INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
|
||||
DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
|
||||
INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
|
||||
INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
|
||||
INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
|
||||
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
|
||||
INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
|
||||
FLCTL_FLTRQ0, FLCTL_FLTRQ1),
|
||||
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
|
|
490
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
Normal file
490
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
Normal file
|
@ -0,0 +1,490 @@
|
|||
/*
|
||||
* SH7786 Setup
|
||||
*
|
||||
* Copyright (C) 2009 Renesas Solutions Corp.
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Based on SH7785 Setup
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffea0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
},
|
||||
/*
|
||||
* The rest of these all have multiplexed IRQs
|
||||
*/
|
||||
{
|
||||
.mapbase = 0xffeb0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 44, 44, 44, 44 },
|
||||
}, {
|
||||
.mapbase = 0xffec0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 50, 50, 50, 50 },
|
||||
}, {
|
||||
.mapbase = 0xffed0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 51, 51, 51, 51 },
|
||||
}, {
|
||||
.mapbase = 0xffee0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 52, 52, 52, 52 },
|
||||
}, {
|
||||
.mapbase = 0xffef0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 53, 53, 53, 53 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource usb_ohci_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffe70400,
|
||||
.end = 0xffe704ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 77,
|
||||
.end = 77,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
|
||||
static struct platform_device usb_ohci_device = {
|
||||
.name = "sh_ohci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &usb_ohci_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(usb_ohci_resources),
|
||||
.resource = usb_ohci_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7786_devices[] __initdata = {
|
||||
&sci_device,
|
||||
&usb_ohci_device,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Please call this function if your platform board
|
||||
* use external clock for USB
|
||||
* */
|
||||
#define USBCTL0 0xffe70858
|
||||
#define CLOCK_MODE_MASK 0xffffff7f
|
||||
#define EXT_CLOCK_MODE 0x00000080
|
||||
void __init sh7786_usb_use_exclock(void)
|
||||
{
|
||||
u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
|
||||
__raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
|
||||
}
|
||||
|
||||
#define USBINITREG1 0xffe70094
|
||||
#define USBINITREG2 0xffe7009c
|
||||
#define USBINITVAL1 0x00ff0040
|
||||
#define USBINITVAL2 0x00000001
|
||||
|
||||
#define USBPCTL1 0xffe70804
|
||||
#define USBST 0xffe70808
|
||||
#define PHY_ENB 0x00000001
|
||||
#define PLL_ENB 0x00000002
|
||||
#define PHY_RST 0x00000004
|
||||
#define ACT_PLL_STATUS 0xc0000000
|
||||
static void __init sh7786_usb_setup(void)
|
||||
{
|
||||
int i = 1000000;
|
||||
|
||||
/*
|
||||
* USB initial settings
|
||||
*
|
||||
* The following settings are necessary
|
||||
* for using the USB modules.
|
||||
*
|
||||
* see "USB Inital Settings" for detail
|
||||
*/
|
||||
__raw_writel(USBINITVAL1, USBINITREG1);
|
||||
__raw_writel(USBINITVAL2, USBINITREG2);
|
||||
|
||||
/*
|
||||
* Set the PHY and PLL enable bit
|
||||
*/
|
||||
__raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
|
||||
while (i-- &&
|
||||
((__raw_readl(USBST) & ACT_PLL_STATUS) != ACT_PLL_STATUS))
|
||||
cpu_relax();
|
||||
|
||||
if (i) {
|
||||
/* Set the PHY RST bit */
|
||||
__raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
|
||||
printk(KERN_INFO "sh7786 usb setup done\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int __init sh7786_devices_setup(void)
|
||||
{
|
||||
sh7786_usb_setup();
|
||||
return platform_add_devices(sh7786_devices,
|
||||
ARRAY_SIZE(sh7786_devices));
|
||||
}
|
||||
device_initcall(sh7786_devices_setup);
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
|
||||
IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
|
||||
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
|
||||
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
|
||||
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
|
||||
|
||||
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
|
||||
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
|
||||
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
|
||||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
|
||||
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
WDT,
|
||||
TMU0_0, TMU0_1, TMU0_2, TMU0_3,
|
||||
TMU1_0, TMU1_1, TMU1_2,
|
||||
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
|
||||
HUDI1, HUDI0,
|
||||
DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
|
||||
HPB_0, HPB_1, HPB_2,
|
||||
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
|
||||
SCIF1,
|
||||
TMU2, TMU3,
|
||||
SCIF2, SCIF3, SCIF4, SCIF5,
|
||||
Eth_0, Eth_1,
|
||||
PCIeC0_0, PCIeC0_1, PCIeC0_2,
|
||||
PCIeC1_0, PCIeC1_1, PCIeC1_2,
|
||||
USB,
|
||||
I2C0, I2C1,
|
||||
DU,
|
||||
SSI0, SSI1, SSI2, SSI3,
|
||||
PCIeC2_0, PCIeC2_1, PCIeC2_2,
|
||||
HAC0, HAC1,
|
||||
FLCTL,
|
||||
HSPI,
|
||||
GPIO0, GPIO1,
|
||||
Thermal,
|
||||
INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
|
||||
|
||||
/* interrupt groups */
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_VECT(WDT, 0x3e0),
|
||||
INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
|
||||
INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
|
||||
INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
|
||||
INTC_VECT(TMU1_2, 0x4c0),
|
||||
INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
|
||||
INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
|
||||
INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
|
||||
INTC_VECT(DMAC0_6, 0x5c0),
|
||||
INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
|
||||
INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
|
||||
INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
|
||||
INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
|
||||
INTC_VECT(HPB_2, 0x6e0),
|
||||
INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
|
||||
INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
|
||||
INTC_VECT(SCIF1, 0x780),
|
||||
INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
|
||||
INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
|
||||
INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
|
||||
INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
|
||||
INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
|
||||
INTC_VECT(PCIeC0_2, 0xb20),
|
||||
INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
|
||||
INTC_VECT(PCIeC1_2, 0xb80),
|
||||
INTC_VECT(USB, 0xba0),
|
||||
INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
|
||||
INTC_VECT(DU, 0xd00),
|
||||
INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
|
||||
INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
|
||||
INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
|
||||
INTC_VECT(PCIeC2_2, 0xde0),
|
||||
INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
|
||||
INTC_VECT(FLCTL, 0xe40),
|
||||
INTC_VECT(HSPI, 0xe80),
|
||||
INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
|
||||
INTC_VECT(Thermal, 0xee0),
|
||||
};
|
||||
|
||||
/* FIXME: Main CPU support only now */
|
||||
#if 1 /* Main CPU */
|
||||
#define CnINTMSK0 0xfe410030
|
||||
#define CnINTMSK1 0xfe410040
|
||||
#define CnINTMSKCLR0 0xfe410050
|
||||
#define CnINTMSKCLR1 0xfe410060
|
||||
#define CnINT2MSKR0 0xfe410a20
|
||||
#define CnINT2MSKR1 0xfe410a24
|
||||
#define CnINT2MSKR2 0xfe410a28
|
||||
#define CnINT2MSKR3 0xfe410a2c
|
||||
#define CnINT2MSKCR0 0xfe410a30
|
||||
#define CnINT2MSKCR1 0xfe410a34
|
||||
#define CnINT2MSKCR2 0xfe410a38
|
||||
#define CnINT2MSKCR3 0xfe410a3c
|
||||
#else /* Sub CPU */
|
||||
#define CnINTMSK0 0xfe410034
|
||||
#define CnINTMSK1 0xfe410044
|
||||
#define CnINTMSKCLR0 0xfe410054
|
||||
#define CnINTMSKCLR1 0xfe410064
|
||||
#define CnINT2MSKR0 0xfe410b20
|
||||
#define CnINT2MSKR1 0xfe410b24
|
||||
#define CnINT2MSKR2 0xfe410b28
|
||||
#define CnINT2MSKR3 0xfe410b2c
|
||||
#define CnINT2MSKCR0 0xfe410b30
|
||||
#define CnINT2MSKCR1 0xfe410b34
|
||||
#define CnINT2MSKCR2 0xfe410b38
|
||||
#define CnINT2MSKCR3 0xfe410b3c
|
||||
#endif
|
||||
|
||||
#define INTMSK2 0xfe410068
|
||||
#define INTMSKCLR2 0xfe41006c
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ CnINTMSK0, CnINTMSKCLR0, 32,
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ INTMSK2, INTMSKCLR2, 32,
|
||||
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
|
||||
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
|
||||
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
|
||||
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
|
||||
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
|
||||
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
|
||||
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
|
||||
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
|
||||
{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
|
||||
{ CnINT2MSKR1, CnINT2MSKCR1, 32,
|
||||
{ TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
|
||||
DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
|
||||
HUDI1, HUDI0,
|
||||
DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
|
||||
HPB_0, HPB_1, HPB_2,
|
||||
SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
|
||||
SCIF1,
|
||||
TMU2, TMU3, 0, } },
|
||||
{ CnINT2MSKR2, CnINT2MSKCR2, 32,
|
||||
{ 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
|
||||
Eth_0, Eth_1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PCIeC0_0, PCIeC0_1, PCIeC0_2,
|
||||
PCIeC1_0, PCIeC1_1, PCIeC1_2,
|
||||
USB, 0, 0 } },
|
||||
{ CnINT2MSKR3, CnINT2MSKCR3, 32,
|
||||
{ 0, 0, 0, 0, 0, 0,
|
||||
I2C0, I2C1,
|
||||
DU, SSI0, SSI1, SSI2, SSI3,
|
||||
PCIeC2_0, PCIeC2_1, PCIeC2_2,
|
||||
HAC0, HAC1,
|
||||
FLCTL, 0,
|
||||
HSPI, GPIO0, GPIO1, Thermal,
|
||||
0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
|
||||
{ 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
|
||||
TMU0_2, TMU0_3 } },
|
||||
{ 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
|
||||
TMU1_2, 0 } },
|
||||
{ 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
|
||||
DMAC0_2, DMAC0_3 } },
|
||||
{ 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
|
||||
DMAC0_6, HUDI1 } },
|
||||
{ 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
|
||||
DMAC1_1, DMAC1_2 } },
|
||||
{ 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
|
||||
HPB_1, HPB_2 } },
|
||||
{ 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
|
||||
SCIF0_2, SCIF0_3 } },
|
||||
{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
|
||||
{ 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
|
||||
{ 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
|
||||
Eth_0, Eth_1 } },
|
||||
{ 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
|
||||
{ 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
|
||||
PCIeC1_0, PCIeC1_1 } },
|
||||
{ 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
|
||||
{ 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
|
||||
{ 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
|
||||
{ 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
|
||||
PCIeC2_1, PCIeC2_2 } },
|
||||
{ 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
|
||||
{ 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
|
||||
GPIO1, Thermal } },
|
||||
{ 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
/* Support for external interrupt pins in IRQ mode */
|
||||
|
||||
static struct intc_vect vectors_irq0123[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
|
||||
INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irq4567[] __initdata = {
|
||||
INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
|
||||
INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_sense_reg sense_registers[] __initdata = {
|
||||
{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg ack_registers[] __initdata = {
|
||||
{ 0xfe410024, 0, 32, /* INTREQ */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
|
||||
vectors_irq0123, NULL, mask_registers,
|
||||
prio_registers, sense_registers, ack_registers);
|
||||
|
||||
static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
|
||||
vectors_irq4567, NULL, mask_registers,
|
||||
prio_registers, sense_registers, ack_registers);
|
||||
|
||||
/* External interrupt pins in IRL mode */
|
||||
|
||||
static struct intc_vect vectors_irl0123[] __initdata = {
|
||||
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
|
||||
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
|
||||
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
|
||||
INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
|
||||
INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
|
||||
INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
|
||||
INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
|
||||
INTC_VECT(IRL0_HHHL, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_vect vectors_irl4567[] __initdata = {
|
||||
INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
|
||||
INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
|
||||
INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
|
||||
INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
|
||||
INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
|
||||
INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
|
||||
INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
|
||||
INTC_VECT(IRL4_HHHL, 0xac0),
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
|
||||
NULL, mask_registers, NULL, NULL);
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
|
||||
NULL, mask_registers, NULL, NULL);
|
||||
|
||||
#define INTC_ICR0 0xfe410000
|
||||
#define INTC_INTMSK0 CnINTMSK0
|
||||
#define INTC_INTMSK1 CnINTMSK1
|
||||
#define INTC_INTMSK2 INTMSK2
|
||||
#define INTC_INTMSKCLR1 CnINTMSKCLR1
|
||||
#define INTC_INTMSKCLR2 INTMSKCLR2
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
/* disable IRQ3-0 + IRQ7-4 */
|
||||
ctrl_outl(0xff000000, INTC_INTMSK0);
|
||||
|
||||
/* disable IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(0xc0000000, INTC_INTMSK1);
|
||||
ctrl_outl(0xfffefffe, INTC_INTMSK2);
|
||||
|
||||
/* select IRL mode for IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
|
||||
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
void __init plat_irq_setup_pins(int mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case IRQ_MODE_IRQ7654:
|
||||
/* select IRQ mode for IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
|
||||
register_intc_controller(&intc_desc_irq4567);
|
||||
break;
|
||||
case IRQ_MODE_IRQ3210:
|
||||
/* select IRQ mode for IRL3-0 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
|
||||
register_intc_controller(&intc_desc_irq0123);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654:
|
||||
/* enable IRL7-4 but don't provide any masking */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210:
|
||||
/* enable IRL0-3 but don't provide any masking */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654_MASK:
|
||||
/* enable IRL7-4 and mask using cpu intc controller */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_desc_irl4567);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210_MASK:
|
||||
/* enable IRL0-3 and mask using cpu intc controller */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_desc_irl0123);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
}
|
6
arch/sh/kernel/cpu/shmobile/Makefile
Normal file
6
arch/sh/kernel/cpu/shmobile/Makefile
Normal file
|
@ -0,0 +1,6 @@
|
|||
#
|
||||
# Makefile for the Linux/SuperH SH-Mobile backends.
|
||||
#
|
||||
|
||||
# Power Management & Sleep mode
|
||||
obj-$(CONFIG_PM) += pm.o sleep.o
|
92
arch/sh/kernel/cpu/shmobile/pm.c
Normal file
92
arch/sh/kernel/cpu/shmobile/pm.c
Normal file
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh4a/pm-sh_mobile.c
|
||||
*
|
||||
* Power management support code for SuperH Mobile
|
||||
*
|
||||
* Copyright (C) 2009 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
/*
|
||||
* Sleep modes available on SuperH Mobile:
|
||||
*
|
||||
* Sleep mode is just plain "sleep" instruction
|
||||
* Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
|
||||
* Standby Self-Refresh mode is above plus stopped clocks
|
||||
*/
|
||||
#define SUSP_MODE_SLEEP (SUSP_SH_SLEEP)
|
||||
#define SUSP_MODE_SLEEP_SF (SUSP_SH_SLEEP | SUSP_SH_SF)
|
||||
#define SUSP_MODE_STANDBY_SF (SUSP_SH_STANDBY | SUSP_SH_SF)
|
||||
|
||||
/*
|
||||
* The following modes are not there yet:
|
||||
*
|
||||
* R-standby mode is unsupported, but will be added in the future
|
||||
* U-standby mode is low priority since it needs bootloader hacks
|
||||
*
|
||||
* All modes should be tied in with cpuidle. But before that can
|
||||
* happen we need to keep track of enabled hardware blocks so we
|
||||
* can avoid entering sleep modes that stop clocks to hardware
|
||||
* blocks that are in use even though the cpu core is idle.
|
||||
*/
|
||||
|
||||
extern const unsigned char sh_mobile_standby[];
|
||||
extern const unsigned int sh_mobile_standby_size;
|
||||
|
||||
static void sh_mobile_call_standby(unsigned long mode)
|
||||
{
|
||||
extern void *vbr_base;
|
||||
void *onchip_mem = (void *)0xe5200000; /* ILRAM */
|
||||
void (*standby_onchip_mem)(unsigned long) = onchip_mem;
|
||||
|
||||
/* Note: Wake up from sleep may generate exceptions!
|
||||
* Setup VBR to point to on-chip ram if self-refresh is
|
||||
* going to be used.
|
||||
*/
|
||||
if (mode & SUSP_SH_SF)
|
||||
asm volatile("ldc %0, vbr" : : "r" (onchip_mem) : "memory");
|
||||
|
||||
/* Copy the assembly snippet to the otherwise ununsed ILRAM */
|
||||
memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
|
||||
wmb();
|
||||
ctrl_barrier();
|
||||
|
||||
/* Let assembly snippet in on-chip memory handle the rest */
|
||||
standby_onchip_mem(mode);
|
||||
|
||||
/* Put VBR back in System RAM again */
|
||||
if (mode & SUSP_SH_SF)
|
||||
asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
|
||||
}
|
||||
|
||||
static int sh_pm_enter(suspend_state_t state)
|
||||
{
|
||||
local_irq_disable();
|
||||
set_bl_bit();
|
||||
sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
|
||||
local_irq_disable();
|
||||
clear_bl_bit();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops sh_pm_ops = {
|
||||
.enter = sh_pm_enter,
|
||||
.valid = suspend_valid_only_mem,
|
||||
};
|
||||
|
||||
static int __init sh_pm_init(void)
|
||||
{
|
||||
suspend_set_ops(&sh_pm_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
late_initcall(sh_pm_init);
|
125
arch/sh/kernel/cpu/shmobile/sleep.S
Normal file
125
arch/sh/kernel/cpu/shmobile/sleep.S
Normal file
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh4a/sleep-sh_mobile.S
|
||||
*
|
||||
* Sleep mode and Standby modes support for SuperH Mobile
|
||||
*
|
||||
* Copyright (C) 2009 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/sys.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
/* manage self-refresh and enter standby mode.
|
||||
* this code will be copied to on-chip memory and executed from there.
|
||||
*/
|
||||
|
||||
.balign 4096,0,4096
|
||||
ENTRY(sh_mobile_standby)
|
||||
mov r4, r0
|
||||
|
||||
tst #SUSP_SH_SF, r0
|
||||
bt skip_set_sf
|
||||
|
||||
/* SDRAM: disable power down and put in self-refresh mode */
|
||||
mov.l 1f, r4
|
||||
mov.l 2f, r1
|
||||
mov.l @r4, r2
|
||||
or r1, r2
|
||||
mov.l 3f, r3
|
||||
and r3, r2
|
||||
mov.l r2, @r4
|
||||
|
||||
skip_set_sf:
|
||||
tst #SUSP_SH_SLEEP, r0
|
||||
bt test_standby
|
||||
|
||||
/* set mode to "sleep mode" */
|
||||
bra do_sleep
|
||||
mov #0x00, r1
|
||||
|
||||
test_standby:
|
||||
tst #SUSP_SH_STANDBY, r0
|
||||
bt test_rstandby
|
||||
|
||||
/* set mode to "software standby mode" */
|
||||
bra do_sleep
|
||||
mov #0x80, r1
|
||||
|
||||
test_rstandby:
|
||||
tst #SUSP_SH_RSTANDBY, r0
|
||||
bt test_ustandby
|
||||
|
||||
/* set mode to "r-standby mode" */
|
||||
bra do_sleep
|
||||
mov #0x20, r1
|
||||
|
||||
test_ustandby:
|
||||
tst #SUSP_SH_USTANDBY, r0
|
||||
bt done_sleep
|
||||
|
||||
/* set mode to "u-standby mode" */
|
||||
mov #0x10, r1
|
||||
|
||||
/* fall-through */
|
||||
|
||||
do_sleep:
|
||||
/* setup and enter selected standby mode */
|
||||
mov.l 5f, r4
|
||||
mov.l r1, @r4
|
||||
sleep
|
||||
|
||||
done_sleep:
|
||||
/* reset standby mode to sleep mode */
|
||||
mov.l 5f, r4
|
||||
mov #0x00, r1
|
||||
mov.l r1, @r4
|
||||
|
||||
tst #SUSP_SH_SF, r0
|
||||
bt skip_restore_sf
|
||||
|
||||
/* SDRAM: set auto-refresh mode */
|
||||
mov.l 1f, r4
|
||||
mov.l @r4, r2
|
||||
mov.l 4f, r3
|
||||
and r3, r2
|
||||
mov.l r2, @r4
|
||||
mov.l 6f, r4
|
||||
mov.l 7f, r1
|
||||
mov.l 8f, r2
|
||||
mov.l @r4, r3
|
||||
mov #-1, r4
|
||||
add r4, r3
|
||||
or r2, r3
|
||||
mov.l r3, @r1
|
||||
skip_restore_sf:
|
||||
rts
|
||||
nop
|
||||
|
||||
.balign 4
|
||||
1: .long 0xfe400008 /* SDCR0 */
|
||||
2: .long 0x00000400
|
||||
3: .long 0xffff7fff
|
||||
4: .long 0xfffffbff
|
||||
5: .long 0xa4150020 /* STBCR */
|
||||
6: .long 0xfe40001c /* RTCOR */
|
||||
7: .long 0xfe400018 /* RTCNT */
|
||||
8: .long 0xa55a0000
|
||||
|
||||
/* interrupt vector @ 0x600 */
|
||||
.balign 0x400,0,0x400
|
||||
.long 0xdeadbeef
|
||||
.balign 0x200,0,0x200
|
||||
/* sh7722 will end up here in sleep mode */
|
||||
rte
|
||||
nop
|
||||
sh_mobile_standby_end:
|
||||
|
||||
ENTRY(sh_mobile_standby_size)
|
||||
.long sh_mobile_standby_end - sh_mobile_standby
|
|
@ -19,22 +19,6 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
static struct pinmux_info *registered_gpio;
|
||||
|
||||
static struct pinmux_info *gpio_controller(unsigned gpio)
|
||||
{
|
||||
if (!registered_gpio)
|
||||
return NULL;
|
||||
|
||||
if (gpio < registered_gpio->first_gpio)
|
||||
return NULL;
|
||||
|
||||
if (gpio > registered_gpio->last_gpio)
|
||||
return NULL;
|
||||
|
||||
return registered_gpio;
|
||||
}
|
||||
|
||||
static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
|
||||
{
|
||||
if (enum_id < r->begin)
|
||||
|
@ -46,9 +30,64 @@ static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int read_write_reg(unsigned long reg, unsigned long reg_width,
|
||||
unsigned long field_width, unsigned long in_pos,
|
||||
unsigned long value, int do_write)
|
||||
static unsigned long gpio_read_raw_reg(unsigned long reg,
|
||||
unsigned long reg_width)
|
||||
{
|
||||
switch (reg_width) {
|
||||
case 8:
|
||||
return ctrl_inb(reg);
|
||||
case 16:
|
||||
return ctrl_inw(reg);
|
||||
case 32:
|
||||
return ctrl_inl(reg);
|
||||
}
|
||||
|
||||
BUG();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gpio_write_raw_reg(unsigned long reg,
|
||||
unsigned long reg_width,
|
||||
unsigned long data)
|
||||
{
|
||||
switch (reg_width) {
|
||||
case 8:
|
||||
ctrl_outb(data, reg);
|
||||
return;
|
||||
case 16:
|
||||
ctrl_outw(data, reg);
|
||||
return;
|
||||
case 32:
|
||||
ctrl_outl(data, reg);
|
||||
return;
|
||||
}
|
||||
|
||||
BUG();
|
||||
}
|
||||
|
||||
static void gpio_write_bit(struct pinmux_data_reg *dr,
|
||||
unsigned long in_pos, unsigned long value)
|
||||
{
|
||||
unsigned long pos;
|
||||
|
||||
pos = dr->reg_width - (in_pos + 1);
|
||||
|
||||
#ifdef DEBUG
|
||||
pr_info("write_bit addr = %lx, value = %ld, pos = %ld, "
|
||||
"r_width = %ld\n",
|
||||
dr->reg, !!value, pos, dr->reg_width);
|
||||
#endif
|
||||
|
||||
if (value)
|
||||
set_bit(pos, &dr->reg_shadow);
|
||||
else
|
||||
clear_bit(pos, &dr->reg_shadow);
|
||||
|
||||
gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
|
||||
}
|
||||
|
||||
static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
|
||||
unsigned long field_width, unsigned long in_pos)
|
||||
{
|
||||
unsigned long data, mask, pos;
|
||||
|
||||
|
@ -57,52 +96,53 @@ static int read_write_reg(unsigned long reg, unsigned long reg_width,
|
|||
pos = reg_width - ((in_pos + 1) * field_width);
|
||||
|
||||
#ifdef DEBUG
|
||||
pr_info("%s, addr = %lx, value = %ld, pos = %ld, "
|
||||
pr_info("read_reg: addr = %lx, pos = %ld, "
|
||||
"r_width = %ld, f_width = %ld\n",
|
||||
do_write ? "write" : "read", reg, value, pos,
|
||||
reg_width, field_width);
|
||||
reg, pos, reg_width, field_width);
|
||||
#endif
|
||||
|
||||
switch (reg_width) {
|
||||
case 8:
|
||||
data = ctrl_inb(reg);
|
||||
break;
|
||||
case 16:
|
||||
data = ctrl_inw(reg);
|
||||
break;
|
||||
case 32:
|
||||
data = ctrl_inl(reg);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!do_write)
|
||||
data = gpio_read_raw_reg(reg, reg_width);
|
||||
return (data >> pos) & mask;
|
||||
|
||||
data &= ~(mask << pos);
|
||||
data |= value << pos;
|
||||
|
||||
switch (reg_width) {
|
||||
case 8:
|
||||
ctrl_outb(data, reg);
|
||||
break;
|
||||
case 16:
|
||||
ctrl_outw(data, reg);
|
||||
break;
|
||||
case 32:
|
||||
ctrl_outl(data, reg);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
|
||||
struct pinmux_data_reg **drp, int *bitp)
|
||||
static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
|
||||
unsigned long field_width, unsigned long in_pos,
|
||||
unsigned long value)
|
||||
{
|
||||
pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
|
||||
unsigned long mask, pos;
|
||||
|
||||
mask = (1 << field_width) - 1;
|
||||
pos = reg_width - ((in_pos + 1) * field_width);
|
||||
|
||||
#ifdef DEBUG
|
||||
pr_info("write_reg addr = %lx, value = %ld, pos = %ld, "
|
||||
"r_width = %ld, f_width = %ld\n",
|
||||
reg, value, pos, reg_width, field_width);
|
||||
#endif
|
||||
|
||||
mask = ~(mask << pos);
|
||||
value = value << pos;
|
||||
|
||||
switch (reg_width) {
|
||||
case 8:
|
||||
ctrl_outb((ctrl_inb(reg) & mask) | value, reg);
|
||||
break;
|
||||
case 16:
|
||||
ctrl_outw((ctrl_inw(reg) & mask) | value, reg);
|
||||
break;
|
||||
case 32:
|
||||
ctrl_outl((ctrl_inl(reg) & mask) | value, reg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
|
||||
{
|
||||
struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
|
||||
struct pinmux_data_reg *data_reg;
|
||||
int k, n;
|
||||
|
||||
if (!enum_in_range(enum_id, &gpioc->data))
|
||||
if (!enum_in_range(gpiop->enum_id, &gpioc->data))
|
||||
return -1;
|
||||
|
||||
k = 0;
|
||||
|
@ -113,19 +153,58 @@ static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
|
|||
break;
|
||||
|
||||
for (n = 0; n < data_reg->reg_width; n++) {
|
||||
if (data_reg->enum_ids[n] == enum_id) {
|
||||
*drp = data_reg;
|
||||
*bitp = n;
|
||||
if (data_reg->enum_ids[n] == gpiop->enum_id) {
|
||||
gpiop->flags &= ~PINMUX_FLAG_DREG;
|
||||
gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
|
||||
gpiop->flags &= ~PINMUX_FLAG_DBIT;
|
||||
gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
|
||||
return 0;
|
||||
|
||||
}
|
||||
}
|
||||
k++;
|
||||
}
|
||||
|
||||
BUG();
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void setup_data_regs(struct pinmux_info *gpioc)
|
||||
{
|
||||
struct pinmux_data_reg *drp;
|
||||
int k;
|
||||
|
||||
for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
|
||||
setup_data_reg(gpioc, k);
|
||||
|
||||
k = 0;
|
||||
while (1) {
|
||||
drp = gpioc->data_regs + k;
|
||||
|
||||
if (!drp->reg_width)
|
||||
break;
|
||||
|
||||
drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
|
||||
k++;
|
||||
}
|
||||
}
|
||||
|
||||
static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
|
||||
struct pinmux_data_reg **drp, int *bitp)
|
||||
{
|
||||
struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
|
||||
int k, n;
|
||||
|
||||
if (!enum_in_range(gpiop->enum_id, &gpioc->data))
|
||||
return -1;
|
||||
|
||||
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
|
||||
n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
|
||||
*drp = gpioc->data_regs + k;
|
||||
*bitp = n;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
|
||||
struct pinmux_cfg_reg **crp, int *indexp,
|
||||
unsigned long **cntp)
|
||||
|
@ -187,7 +266,7 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
|
|||
return -1;
|
||||
}
|
||||
|
||||
static int write_config_reg(struct pinmux_info *gpioc,
|
||||
static void write_config_reg(struct pinmux_info *gpioc,
|
||||
struct pinmux_cfg_reg *crp,
|
||||
int index)
|
||||
{
|
||||
|
@ -197,8 +276,7 @@ static int write_config_reg(struct pinmux_info *gpioc,
|
|||
pos = index / ncomb;
|
||||
value = index % ncomb;
|
||||
|
||||
return read_write_reg(crp->reg, crp->reg_width,
|
||||
crp->field_width, pos, value, 1);
|
||||
gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
|
||||
}
|
||||
|
||||
static int check_config_reg(struct pinmux_info *gpioc,
|
||||
|
@ -211,8 +289,8 @@ static int check_config_reg(struct pinmux_info *gpioc,
|
|||
pos = index / ncomb;
|
||||
value = index % ncomb;
|
||||
|
||||
if (read_write_reg(crp->reg, crp->reg_width,
|
||||
crp->field_width, pos, 0, 0) == value)
|
||||
if (gpio_read_reg(crp->reg, crp->reg_width,
|
||||
crp->field_width, pos) == value)
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
|
@ -220,7 +298,7 @@ static int check_config_reg(struct pinmux_info *gpioc,
|
|||
|
||||
enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
|
||||
|
||||
int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
||||
static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
||||
int pinmux_type, int cfg_mode)
|
||||
{
|
||||
struct pinmux_cfg_reg *cr = NULL;
|
||||
|
@ -287,8 +365,7 @@ int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
|||
break;
|
||||
|
||||
case GPIO_CFG_REQ:
|
||||
if (write_config_reg(gpioc, cr, index) != 0)
|
||||
goto out_err;
|
||||
write_config_reg(gpioc, cr, index);
|
||||
*cntp = *cntp + 1;
|
||||
break;
|
||||
|
||||
|
@ -305,9 +382,14 @@ int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
|||
|
||||
static DEFINE_SPINLOCK(gpio_lock);
|
||||
|
||||
int __gpio_request(unsigned gpio)
|
||||
static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
|
||||
{
|
||||
struct pinmux_info *gpioc = gpio_controller(gpio);
|
||||
return container_of(chip, struct pinmux_info, chip);
|
||||
}
|
||||
|
||||
static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
||||
struct pinmux_data_reg *dummy;
|
||||
unsigned long flags;
|
||||
int i, ret, pinmux_type;
|
||||
|
@ -319,29 +401,30 @@ int __gpio_request(unsigned gpio)
|
|||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
|
||||
if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
|
||||
goto err_unlock;
|
||||
|
||||
/* setup pin function here if no data is associated with pin */
|
||||
|
||||
if (get_data_reg(gpioc, gpio, &dummy, &i) != 0)
|
||||
if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
|
||||
pinmux_type = PINMUX_TYPE_FUNCTION;
|
||||
else
|
||||
pinmux_type = PINMUX_TYPE_GPIO;
|
||||
|
||||
if (pinmux_type == PINMUX_TYPE_FUNCTION) {
|
||||
if (pinmux_config_gpio(gpioc, gpio,
|
||||
if (pinmux_config_gpio(gpioc, offset,
|
||||
pinmux_type,
|
||||
GPIO_CFG_DRYRUN) != 0)
|
||||
goto err_unlock;
|
||||
|
||||
if (pinmux_config_gpio(gpioc, gpio,
|
||||
if (pinmux_config_gpio(gpioc, offset,
|
||||
pinmux_type,
|
||||
GPIO_CFG_REQ) != 0)
|
||||
BUG();
|
||||
}
|
||||
|
||||
gpioc->gpios[gpio].flags = pinmux_type;
|
||||
gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
|
||||
gpioc->gpios[offset].flags |= pinmux_type;
|
||||
|
||||
ret = 0;
|
||||
err_unlock:
|
||||
|
@ -349,11 +432,10 @@ int __gpio_request(unsigned gpio)
|
|||
err_out:
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(__gpio_request);
|
||||
|
||||
void gpio_free(unsigned gpio)
|
||||
static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct pinmux_info *gpioc = gpio_controller(gpio);
|
||||
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
||||
unsigned long flags;
|
||||
int pinmux_type;
|
||||
|
||||
|
@ -362,20 +444,23 @@ void gpio_free(unsigned gpio)
|
|||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
|
||||
pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
|
||||
gpioc->gpios[gpio].flags = PINMUX_TYPE_NONE;
|
||||
pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
|
||||
pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
|
||||
gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
|
||||
gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
|
||||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_free);
|
||||
|
||||
static int pinmux_direction(struct pinmux_info *gpioc,
|
||||
unsigned gpio, int new_pinmux_type)
|
||||
{
|
||||
int ret, pinmux_type;
|
||||
int pinmux_type;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!gpioc)
|
||||
goto err_out;
|
||||
|
||||
ret = -EINVAL;
|
||||
pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
|
||||
|
||||
switch (pinmux_type) {
|
||||
|
@ -401,102 +486,99 @@ static int pinmux_direction(struct pinmux_info *gpioc,
|
|||
GPIO_CFG_REQ) != 0)
|
||||
BUG();
|
||||
|
||||
gpioc->gpios[gpio].flags = new_pinmux_type;
|
||||
gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
|
||||
gpioc->gpios[gpio].flags |= new_pinmux_type;
|
||||
|
||||
ret = 0;
|
||||
err_out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gpio_direction_input(unsigned gpio)
|
||||
static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct pinmux_info *gpioc = gpio_controller(gpio);
|
||||
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
||||
unsigned long flags;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!gpioc)
|
||||
goto err_out;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT);
|
||||
ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
err_out:
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_direction_input);
|
||||
|
||||
static int __gpio_get_set_value(struct pinmux_info *gpioc,
|
||||
unsigned gpio, int value,
|
||||
int do_write)
|
||||
static void sh_gpio_set_value(struct pinmux_info *gpioc,
|
||||
unsigned gpio, int value)
|
||||
{
|
||||
struct pinmux_data_reg *dr = NULL;
|
||||
int bit = 0;
|
||||
|
||||
if (get_data_reg(gpioc, gpio, &dr, &bit) != 0)
|
||||
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
|
||||
BUG();
|
||||
else
|
||||
value = read_write_reg(dr->reg, dr->reg_width,
|
||||
1, bit, !!value, do_write);
|
||||
|
||||
return value;
|
||||
gpio_write_bit(dr, bit, value);
|
||||
}
|
||||
|
||||
int gpio_direction_output(unsigned gpio, int value)
|
||||
static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
struct pinmux_info *gpioc = gpio_controller(gpio);
|
||||
struct pinmux_info *gpioc = chip_to_pinmux(chip);
|
||||
unsigned long flags;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!gpioc)
|
||||
goto err_out;
|
||||
int ret;
|
||||
|
||||
sh_gpio_set_value(gpioc, offset, value);
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
__gpio_get_set_value(gpioc, gpio, value, 1);
|
||||
ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
|
||||
ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
err_out:
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_direction_output);
|
||||
|
||||
int gpio_get_value(unsigned gpio)
|
||||
static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
|
||||
{
|
||||
struct pinmux_info *gpioc = gpio_controller(gpio);
|
||||
unsigned long flags;
|
||||
int value = 0;
|
||||
struct pinmux_data_reg *dr = NULL;
|
||||
int bit = 0;
|
||||
|
||||
if (!gpioc)
|
||||
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) {
|
||||
BUG();
|
||||
else {
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
value = __gpio_get_set_value(gpioc, gpio, 0, 0);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return value;
|
||||
return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_get_value);
|
||||
|
||||
void gpio_set_value(unsigned gpio, int value)
|
||||
static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct pinmux_info *gpioc = gpio_controller(gpio);
|
||||
unsigned long flags;
|
||||
|
||||
if (!gpioc)
|
||||
BUG();
|
||||
else {
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
__gpio_get_set_value(gpioc, gpio, value, 1);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
}
|
||||
return sh_gpio_get_value(chip_to_pinmux(chip), offset);
|
||||
}
|
||||
|
||||
static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_set_value);
|
||||
|
||||
int register_pinmux(struct pinmux_info *pip)
|
||||
{
|
||||
registered_gpio = pip;
|
||||
pr_info("pinmux: %s handling gpio %d -> %d\n",
|
||||
struct gpio_chip *chip = &pip->chip;
|
||||
|
||||
pr_info("sh pinmux: %s handling gpio %d -> %d\n",
|
||||
pip->name, pip->first_gpio, pip->last_gpio);
|
||||
|
||||
return 0;
|
||||
setup_data_regs(pip);
|
||||
|
||||
chip->request = sh_gpio_request;
|
||||
chip->free = sh_gpio_free;
|
||||
chip->direction_input = sh_gpio_direction_input;
|
||||
chip->get = sh_gpio_get;
|
||||
chip->direction_output = sh_gpio_direction_output;
|
||||
chip->set = sh_gpio_set;
|
||||
|
||||
WARN_ON(pip->first_gpio != 0); /* needs testing */
|
||||
|
||||
chip->label = pip->name;
|
||||
chip->owner = THIS_MODULE;
|
||||
chip->base = pip->first_gpio;
|
||||
chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
|
||||
|
||||
return gpiochip_add(chip);
|
||||
}
|
||||
|
|
|
@ -106,7 +106,7 @@ asmlinkage int do_IRQ(unsigned int irq, struct pt_regs *regs)
|
|||
}
|
||||
#endif
|
||||
|
||||
irq = irq_demux(evt2irq(irq));
|
||||
irq = irq_demux(intc_evt2irq(irq));
|
||||
|
||||
#ifdef CONFIG_IRQSTACKS
|
||||
curctx = (union irq_ctx *)current_thread_info();
|
||||
|
|
|
@ -14,21 +14,22 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/numa.h>
|
||||
#include <linux/ftrace.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
typedef NORET_TYPE void (*relocate_new_kernel_t)(
|
||||
unsigned long indirection_page,
|
||||
typedef void (*relocate_new_kernel_t)(unsigned long indirection_page,
|
||||
unsigned long reboot_code_buffer,
|
||||
unsigned long start_address,
|
||||
unsigned long vbr_reg) ATTRIB_NORET;
|
||||
unsigned long start_address);
|
||||
|
||||
extern const unsigned char relocate_new_kernel[];
|
||||
extern const unsigned int relocate_new_kernel_size;
|
||||
extern void *gdb_vbr_vector;
|
||||
extern void *vbr_base;
|
||||
|
||||
void machine_shutdown(void)
|
||||
{
|
||||
|
@ -45,6 +46,12 @@ void machine_crash_shutdown(struct pt_regs *regs)
|
|||
*/
|
||||
int machine_kexec_prepare(struct kimage *image)
|
||||
{
|
||||
/* older versions of kexec-tools are passing
|
||||
* the zImage entry point as a virtual address.
|
||||
*/
|
||||
if (image->start != PHYSADDR(image->start))
|
||||
return -EINVAL; /* upgrade your kexec-tools */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -73,17 +80,33 @@ static void kexec_info(struct kimage *image)
|
|||
*/
|
||||
void machine_kexec(struct kimage *image)
|
||||
{
|
||||
|
||||
unsigned long page_list;
|
||||
unsigned long reboot_code_buffer;
|
||||
unsigned long vbr_reg;
|
||||
relocate_new_kernel_t rnk;
|
||||
unsigned long entry;
|
||||
unsigned long *ptr;
|
||||
int save_ftrace_enabled;
|
||||
|
||||
#if defined(CONFIG_SH_STANDARD_BIOS)
|
||||
vbr_reg = ((unsigned long )gdb_vbr_vector) - 0x100;
|
||||
#else
|
||||
vbr_reg = 0x80000000; // dummy
|
||||
/*
|
||||
* Nicked from the mips version of machine_kexec():
|
||||
* The generic kexec code builds a page list with physical
|
||||
* addresses. Use phys_to_virt() to convert them to virtual.
|
||||
*/
|
||||
for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
|
||||
ptr = (entry & IND_INDIRECTION) ?
|
||||
phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
|
||||
if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
|
||||
*ptr & IND_DESTINATION)
|
||||
*ptr = (unsigned long) phys_to_virt(*ptr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KEXEC_JUMP
|
||||
if (image->preserve_context)
|
||||
save_processor_state();
|
||||
#endif
|
||||
|
||||
save_ftrace_enabled = __ftrace_enabled_save();
|
||||
|
||||
/* Interrupts aren't acceptable while we reboot */
|
||||
local_irq_disable();
|
||||
|
||||
|
@ -100,9 +123,34 @@ void machine_kexec(struct kimage *image)
|
|||
kexec_info(image);
|
||||
flush_cache_all();
|
||||
|
||||
#if defined(CONFIG_SH_STANDARD_BIOS)
|
||||
asm volatile("ldc %0, vbr" :
|
||||
: "r" (((unsigned long) gdb_vbr_vector) - 0x100)
|
||||
: "memory");
|
||||
#endif
|
||||
|
||||
/* now call it */
|
||||
rnk = (relocate_new_kernel_t) reboot_code_buffer;
|
||||
(*rnk)(page_list, reboot_code_buffer, P2SEGADDR(image->start), vbr_reg);
|
||||
(*rnk)(page_list, reboot_code_buffer,
|
||||
(unsigned long)phys_to_virt(image->start));
|
||||
|
||||
#ifdef CONFIG_KEXEC_JUMP
|
||||
asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
|
||||
|
||||
if (image->preserve_context)
|
||||
restore_processor_state();
|
||||
|
||||
/* Convert page list back to physical addresses, what a mess. */
|
||||
for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE);
|
||||
ptr = (*ptr & IND_INDIRECTION) ?
|
||||
phys_to_virt(*ptr & PAGE_MASK) : ptr + 1) {
|
||||
if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
|
||||
*ptr & IND_DESTINATION)
|
||||
*ptr = virt_to_phys(*ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
__ftrace_enabled_restore(save_ftrace_enabled);
|
||||
}
|
||||
|
||||
void arch_crash_save_vmcoreinfo(void)
|
||||
|
|
|
@ -4,6 +4,8 @@
|
|||
*
|
||||
* LANDISK/sh4 is supported. Maybe, SH archtecture works well.
|
||||
*
|
||||
* 2009-03-18 Magnus Damm - Added Kexec Jump support
|
||||
*
|
||||
* This source code is licensed under the GNU General Public License,
|
||||
* Version 2. See the file COPYING for more details.
|
||||
*/
|
||||
|
@ -16,23 +18,141 @@ relocate_new_kernel:
|
|||
/* r4 = indirection_page */
|
||||
/* r5 = reboot_code_buffer */
|
||||
/* r6 = start_address */
|
||||
/* r7 = vbr_reg */
|
||||
|
||||
mov.l 10f,r8 /* PAGE_SIZE */
|
||||
mov.l 11f,r9 /* P2SEG */
|
||||
mov.l 10f, r0 /* PAGE_SIZE */
|
||||
add r5, r0 /* setup new stack at end of control page */
|
||||
|
||||
/* stack setting */
|
||||
add r8,r5
|
||||
mov r5,r15
|
||||
/* save r15->r8 to new stack */
|
||||
mov.l r15, @-r0
|
||||
mov r0, r15
|
||||
mov.l r14, @-r15
|
||||
mov.l r13, @-r15
|
||||
mov.l r12, @-r15
|
||||
mov.l r11, @-r15
|
||||
mov.l r10, @-r15
|
||||
mov.l r9, @-r15
|
||||
mov.l r8, @-r15
|
||||
|
||||
/* save other random registers */
|
||||
sts.l macl, @-r15
|
||||
sts.l mach, @-r15
|
||||
stc.l gbr, @-r15
|
||||
stc.l ssr, @-r15
|
||||
stc.l sr, @-r15
|
||||
sts.l pr, @-r15
|
||||
stc.l spc, @-r15
|
||||
|
||||
/* switch to bank1 and save r7->r0 */
|
||||
mov.l 12f, r9
|
||||
stc sr, r8
|
||||
or r9, r8
|
||||
ldc r8, sr
|
||||
mov.l r7, @-r15
|
||||
mov.l r6, @-r15
|
||||
mov.l r5, @-r15
|
||||
mov.l r4, @-r15
|
||||
mov.l r3, @-r15
|
||||
mov.l r2, @-r15
|
||||
mov.l r1, @-r15
|
||||
mov.l r0, @-r15
|
||||
|
||||
/* switch to bank0 and save r7->r0 */
|
||||
mov.l 12f, r9
|
||||
not r9, r9
|
||||
stc sr, r8
|
||||
and r9, r8
|
||||
ldc r8, sr
|
||||
mov.l r7, @-r15
|
||||
mov.l r6, @-r15
|
||||
mov.l r5, @-r15
|
||||
mov.l r4, @-r15
|
||||
mov.l r3, @-r15
|
||||
mov.l r2, @-r15
|
||||
mov.l r1, @-r15
|
||||
mov.l r0, @-r15
|
||||
|
||||
mov.l r4, @-r15 /* save indirection page again */
|
||||
|
||||
bsr swap_pages /* swap pages before jumping to new kernel */
|
||||
nop
|
||||
|
||||
mova 11f, r0
|
||||
mov.l r15, @r0 /* save pointer to stack */
|
||||
|
||||
jsr @r6 /* hand over control to new kernel */
|
||||
nop
|
||||
|
||||
mov.l 11f, r15 /* get pointer to stack */
|
||||
mov.l @r15+, r4 /* restore r4 to get indirection page */
|
||||
|
||||
bsr swap_pages /* swap pages back to previous state */
|
||||
nop
|
||||
|
||||
/* make sure bank0 is active and restore r0->r7 */
|
||||
mov.l 12f, r9
|
||||
not r9, r9
|
||||
stc sr, r8
|
||||
and r9, r8
|
||||
ldc r8, sr
|
||||
mov.l @r15+, r0
|
||||
mov.l @r15+, r1
|
||||
mov.l @r15+, r2
|
||||
mov.l @r15+, r3
|
||||
mov.l @r15+, r4
|
||||
mov.l @r15+, r5
|
||||
mov.l @r15+, r6
|
||||
mov.l @r15+, r7
|
||||
|
||||
/* switch to bank1 and restore r0->r7 */
|
||||
mov.l 12f, r9
|
||||
stc sr, r8
|
||||
or r9, r8
|
||||
ldc r8, sr
|
||||
mov.l @r15+, r0
|
||||
mov.l @r15+, r1
|
||||
mov.l @r15+, r2
|
||||
mov.l @r15+, r3
|
||||
mov.l @r15+, r4
|
||||
mov.l @r15+, r5
|
||||
mov.l @r15+, r6
|
||||
mov.l @r15+, r7
|
||||
|
||||
/* switch back to bank0 */
|
||||
mov.l 12f, r9
|
||||
not r9, r9
|
||||
stc sr, r8
|
||||
and r9, r8
|
||||
ldc r8, sr
|
||||
|
||||
/* restore other random registers */
|
||||
ldc.l @r15+, spc
|
||||
lds.l @r15+, pr
|
||||
ldc.l @r15+, sr
|
||||
ldc.l @r15+, ssr
|
||||
ldc.l @r15+, gbr
|
||||
lds.l @r15+, mach
|
||||
lds.l @r15+, macl
|
||||
|
||||
/* restore r8->r15 */
|
||||
mov.l @r15+, r8
|
||||
mov.l @r15+, r9
|
||||
mov.l @r15+, r10
|
||||
mov.l @r15+, r11
|
||||
mov.l @r15+, r12
|
||||
mov.l @r15+, r13
|
||||
mov.l @r15+, r14
|
||||
mov.l @r15+, r15
|
||||
rts
|
||||
nop
|
||||
|
||||
swap_pages:
|
||||
bra 1f
|
||||
mov r4,r0 /* cmd = indirection_page */
|
||||
0:
|
||||
mov.l @r4+,r0 /* cmd = *ind++ */
|
||||
|
||||
1: /* addr = (cmd | P2SEG) & 0xfffffff0 */
|
||||
1: /* addr = cmd & 0xfffffff0 */
|
||||
mov r0,r2
|
||||
or r9,r2
|
||||
mov #-16,r1
|
||||
and r1,r2
|
||||
|
||||
|
@ -48,49 +168,62 @@ relocate_new_kernel:
|
|||
bra 0b
|
||||
mov r2,r4
|
||||
|
||||
3: /* else if(cmd & IND_DONE) goto 6 */
|
||||
3: /* else if(cmd & IND_DONE) return */
|
||||
tst #4,r0
|
||||
bt 4f
|
||||
bra 6f
|
||||
rts
|
||||
nop
|
||||
|
||||
4: /* else if(cmd & IND_SOURCE) memcpy(dst,addr,PAGE_SIZE) */
|
||||
tst #8,r0
|
||||
bt 0b
|
||||
|
||||
mov r8,r3
|
||||
mov.l 10f,r3 /* PAGE_SIZE */
|
||||
shlr2 r3
|
||||
shlr2 r3
|
||||
5:
|
||||
dt r3
|
||||
mov.l @r2+,r1 /* 16n+0 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
mov.l @r2+,r1 /* 16n+4 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
mov.l @r2+,r1 /* 16n+8 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
mov.l @r2+,r1 /* 16n+12 */
|
||||
mov.l r1,@r5
|
||||
add #4,r5
|
||||
|
||||
/* regular kexec just overwrites the destination page
|
||||
* with the contents of the source page.
|
||||
* for the kexec jump case we need to swap the contents
|
||||
* of the pages.
|
||||
* to keep it simple swap the contents for both cases.
|
||||
*/
|
||||
mov.l @(0, r2), r8
|
||||
mov.l @(0, r5), r1
|
||||
mov.l r8, @(0, r5)
|
||||
mov.l r1, @(0, r2)
|
||||
|
||||
mov.l @(4, r2), r8
|
||||
mov.l @(4, r5), r1
|
||||
mov.l r8, @(4, r5)
|
||||
mov.l r1, @(4, r2)
|
||||
|
||||
mov.l @(8, r2), r8
|
||||
mov.l @(8, r5), r1
|
||||
mov.l r8, @(8, r5)
|
||||
mov.l r1, @(8, r2)
|
||||
|
||||
mov.l @(12, r2), r8
|
||||
mov.l @(12, r5), r1
|
||||
mov.l r8, @(12, r5)
|
||||
mov.l r1, @(12, r2)
|
||||
|
||||
add #16,r5
|
||||
add #16,r2
|
||||
bf 5b
|
||||
|
||||
bra 0b
|
||||
nop
|
||||
6:
|
||||
#ifdef CONFIG_SH_STANDARD_BIOS
|
||||
ldc r7, vbr
|
||||
#endif
|
||||
jmp @r6
|
||||
nop
|
||||
|
||||
.align 2
|
||||
10:
|
||||
.long PAGE_SIZE
|
||||
11:
|
||||
.long P2SEG
|
||||
.long 0
|
||||
12:
|
||||
.long 0x20000000 ! RB=1
|
||||
|
||||
relocate_new_kernel_end:
|
||||
|
||||
|
|
|
@ -432,6 +432,7 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
|
||||
[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
|
||||
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
|
||||
[CPU_SH7786] = "SH7786",
|
||||
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
|
||||
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
|
||||
|
@ -448,7 +449,7 @@ EXPORT_SYMBOL(get_cpu_subtype);
|
|||
/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
|
||||
static const char *cpu_flags[] = {
|
||||
"none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
|
||||
"ptea", "llsc", "l2", "op32", NULL
|
||||
"ptea", "llsc", "l2", "op32", "pteaex", NULL
|
||||
};
|
||||
|
||||
static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
|
||||
|
|
38
arch/sh/kernel/swsusp.c
Normal file
38
arch/sh/kernel/swsusp.c
Normal file
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* swsusp.c - SuperH hibernation support
|
||||
*
|
||||
* Copyright (C) 2009 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/fpu.h>
|
||||
|
||||
struct swsusp_arch_regs swsusp_arch_regs_cpu0;
|
||||
|
||||
int pfn_is_nosave(unsigned long pfn)
|
||||
{
|
||||
unsigned long begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
|
||||
unsigned long end_pfn = PAGE_ALIGN(__pa(&__nosave_end)) >> PAGE_SHIFT;
|
||||
|
||||
return (pfn >= begin_pfn) && (pfn < end_pfn);
|
||||
}
|
||||
|
||||
void save_processor_state(void)
|
||||
{
|
||||
init_fpu(current);
|
||||
}
|
||||
|
||||
void restore_processor_state(void)
|
||||
{
|
||||
local_flush_tlb_all();
|
||||
}
|
|
@ -41,14 +41,6 @@ static int null_rtc_set_time(const time_t secs)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Null high precision timer functions for systems lacking one.
|
||||
*/
|
||||
static cycle_t null_hpt_read(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
|
||||
int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
|
||||
|
||||
|
@ -112,7 +104,6 @@ int do_settimeofday(struct timespec *tv)
|
|||
EXPORT_SYMBOL(do_settimeofday);
|
||||
#endif /* !CONFIG_GENERIC_TIME */
|
||||
|
||||
#ifndef CONFIG_GENERIC_CLOCKEVENTS
|
||||
/* last time the RTC clock got updated */
|
||||
static long last_rtc_update;
|
||||
|
||||
|
@ -156,7 +147,6 @@ void handle_timer_tick(void)
|
|||
update_process_times(user_mode(get_irq_regs()));
|
||||
#endif
|
||||
}
|
||||
#endif /* !CONFIG_GENERIC_CLOCKEVENTS */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
int timer_suspend(struct sys_device *dev, pm_message_t state)
|
||||
|
@ -189,7 +179,12 @@ static struct sysdev_class timer_sysclass = {
|
|||
|
||||
static int __init timer_init_sysfs(void)
|
||||
{
|
||||
int ret = sysdev_class_register(&timer_sysclass);
|
||||
int ret;
|
||||
|
||||
if (!sys_timer)
|
||||
return 0;
|
||||
|
||||
ret = sysdev_class_register(&timer_sysclass);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
|
@ -200,42 +195,21 @@ device_initcall(timer_init_sysfs);
|
|||
|
||||
void (*board_time_init)(void);
|
||||
|
||||
/*
|
||||
* Shamelessly based on the MIPS and Sparc64 work.
|
||||
*/
|
||||
static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
|
||||
unsigned long sh_hpt_frequency = 0;
|
||||
|
||||
#define NSEC_PER_CYC_SHIFT 10
|
||||
|
||||
static struct clocksource clocksource_sh = {
|
||||
struct clocksource clocksource_sh = {
|
||||
.name = "SuperH",
|
||||
.rating = 200,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.read = null_hpt_read,
|
||||
.shift = 16,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static void __init init_sh_clocksource(void)
|
||||
{
|
||||
if (!sh_hpt_frequency || clocksource_sh.read == null_hpt_read)
|
||||
return;
|
||||
|
||||
clocksource_sh.mult = clocksource_hz2mult(sh_hpt_frequency,
|
||||
clocksource_sh.shift);
|
||||
|
||||
timer_ticks_per_nsec_quotient =
|
||||
clocksource_hz2mult(sh_hpt_frequency, NSEC_PER_CYC_SHIFT);
|
||||
|
||||
clocksource_register(&clocksource_sh);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_TIME
|
||||
unsigned long long sched_clock(void)
|
||||
{
|
||||
unsigned long long ticks = clocksource_sh.read();
|
||||
return (ticks * timer_ticks_per_nsec_quotient) >> NSEC_PER_CYC_SHIFT;
|
||||
unsigned long long cycles;
|
||||
|
||||
/* jiffies based sched_clock if no clocksource is installed */
|
||||
if (!clocksource_sh.rating)
|
||||
return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ);
|
||||
|
||||
cycles = clocksource_sh.read();
|
||||
return cyc2ns(&clocksource_sh, cycles);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -259,17 +233,8 @@ void __init time_init(void)
|
|||
* initialized for us.
|
||||
*/
|
||||
sys_timer = get_sys_timer();
|
||||
if (unlikely(!sys_timer))
|
||||
panic("System timer missing.\n");
|
||||
|
||||
printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
|
||||
|
||||
|
||||
if (sys_timer->ops->read)
|
||||
clocksource_sh.read = sys_timer->ops->read;
|
||||
|
||||
init_sh_clocksource();
|
||||
|
||||
if (sh_hpt_frequency)
|
||||
printk("Using %lu.%03lu MHz high precision timer.\n",
|
||||
((sh_hpt_frequency + 500) / 1000) / 1000,
|
||||
((sh_hpt_frequency + 500) / 1000) % 1000);
|
||||
|
||||
}
|
||||
|
|
|
@ -35,7 +35,8 @@
|
|||
#define MTU2_TSR_1 0xfffe4385
|
||||
#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7201)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7201) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7203)
|
||||
#define MTU2_TGRA_1 0xfffe4388
|
||||
#else
|
||||
#define MTU2_TGRA_1 0xfffe438a
|
||||
|
|
|
@ -146,7 +146,14 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
|
|||
_tmu_clear_status(TMU0);
|
||||
_tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
|
||||
|
||||
switch (tmu0_clockevent.mode) {
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
evt->event_handler(evt);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
@ -237,6 +244,7 @@ static int tmu_timer_init(void)
|
|||
!defined(CONFIG_CPU_SUBTYPE_SH7721) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7786) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
|
||||
#endif
|
||||
|
@ -254,7 +262,14 @@ static int tmu_timer_init(void)
|
|||
|
||||
_tmu_start(TMU1);
|
||||
|
||||
sh_hpt_frequency = clk_get_rate(&tmu1_clk);
|
||||
clocksource_sh.rating = 200;
|
||||
clocksource_sh.mask = CLOCKSOURCE_MASK(32);
|
||||
clocksource_sh.read = tmu_timer_read;
|
||||
clocksource_sh.shift = 10;
|
||||
clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
|
||||
clocksource_sh.shift);
|
||||
clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
||||
clocksource_register(&clocksource_sh);
|
||||
|
||||
tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
|
||||
tmu0_clockevent.shift);
|
||||
|
@ -264,6 +279,7 @@ static int tmu_timer_init(void)
|
|||
clockevent_delta2ns(1, &tmu0_clockevent);
|
||||
|
||||
tmu0_clockevent.cpumask = cpumask_of(0);
|
||||
tmu0_clockevent.rating = 100;
|
||||
|
||||
clockevents_register_device(&tmu0_clockevent);
|
||||
|
||||
|
@ -274,7 +290,6 @@ static struct sys_timer_ops tmu_timer_ops = {
|
|||
.init = tmu_timer_init,
|
||||
.start = tmu_timer_start,
|
||||
.stop = tmu_timer_stop,
|
||||
.read = tmu_timer_read,
|
||||
};
|
||||
|
||||
struct sys_timer tmu_timer = {
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue