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MLK-14946-2: pinctrl: imx8qm/qxp: switch to use new format 

switch to use new format. Split mux out from pad config.
Change the high two bits in pad config to 0, because driver
will automatically set that two bits to 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
pull/10/head
Peng Fan 2017-05-18 18:06:58 +08:00 committed by Jason Liu
parent 7b30763676
commit 937666200c
5 changed files with 104 additions and 95 deletions
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118
arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
View File

@ -46,20 +46,20 @@
imx8qm-arm2 {
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC 0xc6000048
SC_P_ENET0_MDIO 0xc6000048
SC_P_ENET0_RGMII_TX_CTL 0xc6000048
SC_P_ENET0_RGMII_TXC 0xc6000048
SC_P_ENET0_RGMII_TXD0 0xc6000048
SC_P_ENET0_RGMII_TXD1 0xc6000048
SC_P_ENET0_RGMII_TXD2 0xc6000048
SC_P_ENET0_RGMII_TXD3 0xc6000048
SC_P_ENET0_RGMII_RXC 0xc6000048
SC_P_ENET0_RGMII_RX_CTL 0xc6000048
SC_P_ENET0_RGMII_RXD0 0xc6000048
SC_P_ENET0_RGMII_RXD1 0xc6000048
SC_P_ENET0_RGMII_RXD2 0xc6000048
SC_P_ENET0_RGMII_RXD3 0xc6000048
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
>;
};
@ -84,76 +84,76 @@
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX 0xc600004c
SC_P_UART0_TX 0xc600004c
SC_P_UART0_RTS_B 0xc600004c
SC_P_UART0_CTS_B 0xc600004c
SC_P_UART0_RX_DMA_UART0_RX 0x0600004c
SC_P_UART0_TX_DMA_UART0_TX 0x0600004c
SC_P_UART0_RTS_B_DMA_UART0_RTS_B 0x0600004c
SC_P_UART0_CTS_B_DMA_UART0_CTS_B 0x0600004c
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK 0xc6000021
SC_P_EMMC0_CMD 0xc0000021
SC_P_EMMC0_DATA0 0xc0000021
SC_P_EMMC0_DATA1 0xc0000021
SC_P_EMMC0_DATA2 0xc0000021
SC_P_EMMC0_DATA3 0xc0000021
SC_P_EMMC0_DATA4 0xc0000021
SC_P_EMMC0_DATA5 0xc0000021
SC_P_EMMC0_DATA6 0xc0000021
SC_P_EMMC0_DATA7 0xc0000021
SC_P_EMMC0_RESET_B 0xc0000021
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK 0xc6000021
SC_P_USDHC1_CMD 0xc0000021
SC_P_USDHC1_DATA0 0xc0000021
SC_P_USDHC1_DATA1 0xc0000021
SC_P_USDHC1_DATA2 0xc0000021
SC_P_USDHC1_DATA3 0xc0000021
SC_P_USDHC1_DATA6 0xd8000021
SC_P_USDHC1_DATA7 0xd8000021
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
>;
};
pinctrl_lpspi0: lpspi0grp {
fsl,pins = <
SC_P_SPI0_SCK 0xc600004c
SC_P_SPI0_SDO 0xc600004c
SC_P_SPI0_SDI 0xc600004c
SC_P_SPI0_CS0 0xc600004c
SC_P_SPI0_CS1 0xc600004c
SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c
SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c
SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c
SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c
SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0 0xc600004c
SC_P_QSPI0A_DATA1 0xc600004c
SC_P_QSPI0A_DATA2 0xc600004c
SC_P_QSPI0A_DATA3 0xc600004c
SC_P_QSPI0A_DQS 0xc600004c
SC_P_QSPI0A_SS0_B 0xc600004c
SC_P_QSPI0A_SS1_B 0xc600004c
SC_P_QSPI0A_SCLK 0xc600004c
SC_P_QSPI0B_SCLK 0xc600004c
SC_P_QSPI0B_DATA0 0xc600004c
SC_P_QSPI0B_DATA1 0xc600004c
SC_P_QSPI0B_DATA2 0xc600004c
SC_P_QSPI0B_DATA3 0xc600004c
SC_P_QSPI0B_DQS 0xc600004c
SC_P_QSPI0B_SS0_B 0xc600004c
SC_P_QSPI0B_SS1_B 0xc600004c
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
SC_P_SPDIF0_TX 0xd8000021
SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
>;
};
};

54
arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
View File

@ -48,58 +48,58 @@
pinctrl_lpi2c1: lpi1cgrp {
fsl,pins = <
SC_P_USB_SS3_TC0 0xc6000020
SC_P_USB_SS3_TC3 0xc6000020
SC_P_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000020
SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000020
>;
};
pinctrl_lpi2c3: lpi2cgrp {
fsl,pins = <
SC_P_SPI3_CS1 0xce000020
SC_P_MCLK_IN0 0xce000020
SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020
SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX 0xc600004c
SC_P_UART0_TX 0xc600004c
SC_P_UART0_RX_ADMA_UART0_RX 0x0600004c
SC_P_UART0_TX_ADMA_UART0_TX 0x0600004c
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK 0xc6000021
SC_P_EMMC0_CMD 0xc0000021
SC_P_EMMC0_DATA0 0xc0000021
SC_P_EMMC0_DATA1 0xc0000021
SC_P_EMMC0_DATA2 0xc0000021
SC_P_EMMC0_DATA3 0xc0000021
SC_P_EMMC0_DATA4 0xc0000021
SC_P_EMMC0_DATA5 0xc0000021
SC_P_EMMC0_DATA6 0xc0000021
SC_P_EMMC0_DATA7 0xc0000021
SC_P_EMMC0_RESET_B 0xc0000021
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_rst: usdhc2_rst_grp {
fsl,pins = <
SC_P_USDHC1_RESET_B 0xe6000048
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x06000048
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK 0xc6000021
SC_P_USDHC1_CMD 0xc6000021
SC_P_USDHC1_DATA0 0xc6000021
SC_P_USDHC1_DATA1 0xc6000021
SC_P_USDHC1_DATA2 0xc6000021
SC_P_USDHC1_DATA3 0xc6000021
SC_P_USDHC1_VSELECT 0xc6000021
SC_P_USDHC1_WP 0xe6000021
SC_P_USDHC1_CD_B 0xe6000021
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x06000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x06000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x06000021
SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x06000021
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
>;
};
};

6
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -118,8 +118,8 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
new_map[j].data.configs.configs =
(unsigned long *)&pin->pin_conf.pin_scu.all;
new_map[j].data.configs.num_configs = 1;
(unsigned long *)&pin->pin_conf.pin_scu;
new_map[j].data.configs.num_configs = 2;
j++;
} else if (!(pin->pin_conf.pin_memmap.config & IMX_NO_PAD_CTL)) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
@ -318,7 +318,7 @@ static const struct pinconf_ops imx_pinconf_ops = {
* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
* 1 u32 CONFIG, so 24 types in total for each pin.
*/
#define FSL_IMX8_PIN_SIZE 8
#define FSL_IMX8_PIN_SIZE 12
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20

3
drivers/pinctrl/freescale/pinctrl-imx.h
View File

@ -40,7 +40,8 @@ struct imx_pin_memmap {
};
struct imx_pin_scu {
unsigned int all;
unsigned long mux;
unsigned long config;
};
struct imx_pin {

18
drivers/pinctrl/freescale/pinctrl-scu.c
View File

@ -61,7 +61,12 @@ int imx_pinconf_backend_set(struct pinctrl_dev *pctldev, unsigned pin_id,
sc_ipc_t ipc = pinctrl_ipcHandle;
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
unsigned int val = configs[0];
/*
* Mux should be done in pmx set, but we do not have a good api
* to handle that in scfw, so config it in pad conf func
*/
unsigned int mux = configs[0];
unsigned int val = configs[1];
if (ipc == -1) {
printk("IPC handle not initialized!\n");
@ -74,8 +79,10 @@ int imx_pinconf_backend_set(struct pinctrl_dev *pctldev, unsigned pin_id,
if (info->flags & IMX8_ENABLE_PAD_CONFIG)
val |= BM_IMX8_GP_ENABLE;
if (info->flags & SHARE_MUX_CONF_REG)
if (info->flags & SHARE_MUX_CONF_REG) {
val |= (mux << 27) & (0x7 << 27);
err = sc_pad_set(ipc, pin_id, val);
}
if (err != SC_ERR_NONE)
return -EIO;
@ -91,10 +98,11 @@ int imx_pinctrl_parse_pin(struct imx_pinctrl_soc_info *info,
pin->pin = be32_to_cpu(*((*list_p)++));
*pin_id = pin->pin;
pin_scu->all = be32_to_cpu(*((*list_p)++));
pin_scu->mux = be32_to_cpu(*((*list_p)++));
pin_scu->config = be32_to_cpu(*((*list_p)++));
dev_dbg(info->dev, "%s: 0x%x",
info->pins[pin->pin].name, pin_scu->all);
dev_dbg(info->dev, "%s: 0x%lx 0x%lx",
info->pins[pin->pin].name, pin_scu->mux, pin_scu->config);
return 0;
}