Merge branch 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/clock
Shawn Guo <shawn.guo@linaro.org> writes: mxs common clk porting for v3.5. It depends on the following two branches. [1] git://git.linaro.org/people/mturquette/linux.git clk-next [2] http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-arm.git clkdev As the mxs device tree conversion will constantly touch clock files, to save the conflicts, the updated mxs/dt branch coming later will based on this pull-request. * 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs: remove now unused timer_clk argument from mxs_timer_init ARM: mxs: remove old clock support ARM: mxs: switch to common clk framework ARM: mxs: change the lookup name for fec phy clock ARM: mxs: request clock for timer clk: mxs: add clock support for imx28 clk: mxs: add clock support for imx23 clk: mxs: add mxs specific clocks Includes an update to Linux 3.4-rc6 Conflicts: drivers/clk/Makefile Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
93c6d8927f
19
Documentation/ABI/testing/sysfs-bus-hsi
Normal file
19
Documentation/ABI/testing/sysfs-bus-hsi
Normal file
|
@ -0,0 +1,19 @@
|
|||
What: /sys/bus/hsi
|
||||
Date: April 2012
|
||||
KernelVersion: 3.4
|
||||
Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
Description:
|
||||
High Speed Synchronous Serial Interface (HSI) is a
|
||||
serial interface mainly used for connecting application
|
||||
engines (APE) with cellular modem engines (CMT) in cellular
|
||||
handsets.
|
||||
The bus will be populated with devices (hsi_clients) representing
|
||||
the protocols available in the system. Bus drivers implement
|
||||
those protocols.
|
||||
|
||||
What: /sys/bus/hsi/devices/.../modalias
|
||||
Date: April 2012
|
||||
KernelVersion: 3.4
|
||||
Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
Description: Stores the same MODALIAS value emitted by uevent
|
||||
Format: hsi:<hsi_client device name>
|
|
@ -1,10 +1,10 @@
|
|||
* Calxeda SATA Controller
|
||||
* AHCI SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "calxeda,hb-ahci"
|
||||
- compatible : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
|
@ -14,4 +14,3 @@ Example:
|
|||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
};
|
||||
|
|
@ -3,6 +3,8 @@
|
|||
Required properties:
|
||||
- compatible : "fsl,sgtl5000".
|
||||
|
||||
- reg : the I2C address of the device
|
||||
|
||||
Example:
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
|
|
|
@ -147,7 +147,7 @@ tcp_adv_win_scale - INTEGER
|
|||
(if tcp_adv_win_scale > 0) or bytes-bytes/2^(-tcp_adv_win_scale),
|
||||
if it is <= 0.
|
||||
Possible values are [-31, 31], inclusive.
|
||||
Default: 2
|
||||
Default: 1
|
||||
|
||||
tcp_allowed_congestion_control - STRING
|
||||
Show/set the congestion control choices available to non-privileged
|
||||
|
@ -410,7 +410,7 @@ tcp_rmem - vector of 3 INTEGERs: min, default, max
|
|||
net.core.rmem_max. Calling setsockopt() with SO_RCVBUF disables
|
||||
automatic tuning of that socket's receive buffer size, in which
|
||||
case this value is ignored.
|
||||
Default: between 87380B and 4MB, depending on RAM size.
|
||||
Default: between 87380B and 6MB, depending on RAM size.
|
||||
|
||||
tcp_sack - BOOLEAN
|
||||
Enable select acknowledgments (SACKS).
|
||||
|
|
|
@ -9,7 +9,7 @@ architectures).
|
|||
|
||||
II. How does it work?
|
||||
|
||||
There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
|
||||
There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
|
||||
and PF_FREEZER_SKIP (the last one is auxiliary). The tasks that have
|
||||
PF_NOFREEZE unset (all user space processes and some kernel threads) are
|
||||
regarded as 'freezable' and treated in a special way before the system enters a
|
||||
|
@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
|
|||
we only consider hibernation, but the description also applies to suspend).
|
||||
|
||||
Namely, as the first step of the hibernation procedure the function
|
||||
freeze_processes() (defined in kernel/power/process.c) is called. It executes
|
||||
try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
|
||||
either wakes them up, if they are kernel threads, or sends fake signals to them,
|
||||
if they are user space processes. A task that has TIF_FREEZE set, should react
|
||||
to it by calling the function called __refrigerator() (defined in
|
||||
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
|
||||
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
|
||||
Then, we say that the task is 'frozen' and therefore the set of functions
|
||||
handling this mechanism is referred to as 'the freezer' (these functions are
|
||||
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
|
||||
User space processes are generally frozen before kernel threads.
|
||||
freeze_processes() (defined in kernel/power/process.c) is called. A system-wide
|
||||
variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
|
||||
whether the system is to undergo a freezing operation. And freeze_processes()
|
||||
sets this variable. After this, it executes try_to_freeze_tasks() that sends a
|
||||
fake signal to all user space processes, and wakes up all the kernel threads.
|
||||
All freezable tasks must react to that by calling try_to_freeze(), which
|
||||
results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
|
||||
the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
|
||||
it loop until PF_FROZEN is cleared for it. Then, we say that the task is
|
||||
'frozen' and therefore the set of functions handling this mechanism is referred
|
||||
to as 'the freezer' (these functions are defined in kernel/power/process.c,
|
||||
kernel/freezer.c & include/linux/freezer.h). User space processes are generally
|
||||
frozen before kernel threads.
|
||||
|
||||
__refrigerator() must not be called directly. Instead, use the
|
||||
try_to_freeze() function (defined in include/linux/freezer.h), that checks
|
||||
the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
|
||||
flag is set.
|
||||
if the task is to be frozen and makes the task enter __refrigerator().
|
||||
|
||||
For user space processes try_to_freeze() is called automatically from the
|
||||
signal-handling code, but the freezable kernel threads need to call it
|
||||
explicitly in suitable places or use the wait_event_freezable() or
|
||||
wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
|
||||
that combine interruptible sleep with checking if TIF_FREEZE is set and calling
|
||||
try_to_freeze(). The main loop of a freezable kernel thread may look like the
|
||||
following one:
|
||||
that combine interruptible sleep with checking if the task is to be frozen and
|
||||
calling try_to_freeze(). The main loop of a freezable kernel thread may look
|
||||
like the following one:
|
||||
|
||||
set_freezable();
|
||||
do {
|
||||
|
@ -53,7 +54,7 @@ following one:
|
|||
(from drivers/usb/core/hub.c::hub_thread()).
|
||||
|
||||
If a freezable kernel thread fails to call try_to_freeze() after the freezer has
|
||||
set TIF_FREEZE for it, the freezing of tasks will fail and the entire
|
||||
initiated a freezing operation, the freezing of tasks will fail and the entire
|
||||
hibernation operation will be cancelled. For this reason, freezable kernel
|
||||
threads must call try_to_freeze() somewhere or use one of the
|
||||
wait_event_freezable() and wait_event_freezable_timeout() macros.
|
||||
|
|
|
@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
|
|||
|
||||
The key service provides a number of features besides keys:
|
||||
|
||||
(*) The key service defines two special key types:
|
||||
(*) The key service defines three special key types:
|
||||
|
||||
(+) "keyring"
|
||||
|
||||
|
@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
|
|||
blobs of data. These can be created, updated and read by userspace,
|
||||
and aren't intended for use by kernel services.
|
||||
|
||||
(+) "logon"
|
||||
|
||||
Like a "user" key, a "logon" key has a payload that is an arbitrary
|
||||
blob of data. It is intended as a place to store secrets which are
|
||||
accessible to the kernel but not to userspace programs.
|
||||
|
||||
The description can be arbitrary, but must be prefixed with a non-zero
|
||||
length string that describes the key "subclass". The subclass is
|
||||
separated from the rest of the description by a ':'. "logon" keys can
|
||||
be created and updated from userspace, but the payload is only
|
||||
readable from kernel space.
|
||||
|
||||
(*) Each process subscribes to three keyrings: a thread-specific keyring, a
|
||||
process-specific keyring, and a session-specific keyring.
|
||||
|
||||
|
|
12
MAINTAINERS
12
MAINTAINERS
|
@ -1978,10 +1978,7 @@ S: Maintained
|
|||
F: drivers/net/ethernet/ti/cpmac.c
|
||||
|
||||
CPU FREQUENCY DRIVERS
|
||||
M: Dave Jones <davej@redhat.com>
|
||||
L: cpufreq@vger.kernel.org
|
||||
W: http://www.codemonkey.org.uk/projects/cpufreq/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git
|
||||
S: Maintained
|
||||
F: drivers/cpufreq/
|
||||
F: include/linux/cpufreq.h
|
||||
|
@ -3602,6 +3599,7 @@ S: Supported
|
|||
F: drivers/net/wireless/iwlegacy/
|
||||
|
||||
INTEL WIRELESS WIFI LINK (iwlwifi)
|
||||
M: Johannes Berg <johannes.berg@intel.com>
|
||||
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
|
||||
M: Intel Linux Wireless <ilw@linux.intel.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
|
@ -5901,11 +5899,11 @@ F: Documentation/scsi/st.txt
|
|||
F: drivers/scsi/st*
|
||||
|
||||
SCTP PROTOCOL
|
||||
M: Vlad Yasevich <vladislav.yasevich@hp.com>
|
||||
M: Vlad Yasevich <vyasevich@gmail.com>
|
||||
M: Sridhar Samudrala <sri@us.ibm.com>
|
||||
L: linux-sctp@vger.kernel.org
|
||||
W: http://lksctp.sourceforge.net
|
||||
S: Supported
|
||||
S: Maintained
|
||||
F: Documentation/networking/sctp.txt
|
||||
F: include/linux/sctp.h
|
||||
F: include/net/sctp/
|
||||
|
@ -7588,8 +7586,8 @@ F: Documentation/filesystems/xfs.txt
|
|||
F: fs/xfs/
|
||||
|
||||
XILINX AXI ETHERNET DRIVER
|
||||
M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
|
||||
M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
|
||||
M: Anirudha Sarangi <anirudh@xilinx.com>
|
||||
M: John Linn <John.Linn@xilinx.com>
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/xilinx/xilinx_axienet*
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 4
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK
|
|||
|
||||
config VGA_HOSE
|
||||
bool
|
||||
depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI
|
||||
depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
|
||||
default y
|
||||
help
|
||||
Support VGA on an arbitrary hose; needed for several platforms
|
||||
|
|
|
@ -1,14 +1,10 @@
|
|||
#ifndef _ALPHA_RTC_H
|
||||
#define _ALPHA_RTC_H
|
||||
|
||||
#if defined(CONFIG_ALPHA_GENERIC)
|
||||
#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \
|
||||
|| defined(CONFIG_ALPHA_GENERIC)
|
||||
# define get_rtc_time alpha_mv.rtc_get_time
|
||||
# define set_rtc_time alpha_mv.rtc_set_time
|
||||
#else
|
||||
# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP)
|
||||
# define get_rtc_time marvel_get_rtc_time
|
||||
# define set_rtc_time marvel_set_rtc_time
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#include <asm-generic/rtc.h>
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
#include <asm/core_tsunami.h>
|
||||
#undef __EXTERN_INLINE
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/sched.h>
|
||||
|
|
|
@ -317,7 +317,7 @@ marvel_init_irq(void)
|
|||
}
|
||||
|
||||
static int
|
||||
marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
struct pci_controller *hose = dev->sysdata;
|
||||
struct io7_port *io7_port = hose->sysdata;
|
||||
|
|
|
@ -468,6 +468,7 @@ config ARCH_MXS
|
|||
select ARCH_REQUIRE_GPIOLIB
|
||||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select COMMON_CLK
|
||||
select HAVE_CLK_PREPARE
|
||||
help
|
||||
Support for Freescale MXS-based family of processors
|
||||
|
@ -1186,6 +1187,15 @@ if !MMU
|
|||
source "arch/arm/Kconfig-nommu"
|
||||
endif
|
||||
|
||||
config ARM_ERRATA_326103
|
||||
bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
|
||||
depends on CPU_V6
|
||||
help
|
||||
Executing a SWP instruction to read-only memory does not set bit 11
|
||||
of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
|
||||
treat the access as a read, preventing a COW from occurring and
|
||||
causing the faulting task to livelock.
|
||||
|
||||
config ARM_ERRATA_411920
|
||||
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
|
||||
depends on CPU_V6 || CPU_V6K
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
intc: interrupt-controller@02080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02080000 0x1000 >,
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
@ -19,6 +19,6 @@
|
|||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <195>;
|
||||
interrupts = <0 195 0x0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -173,7 +173,7 @@
|
|||
mmc@5000 {
|
||||
compatible = "arm,primecell";
|
||||
reg = < 0x5000 0x1000>;
|
||||
interrupts = <22>;
|
||||
interrupts = <22 34>;
|
||||
};
|
||||
kmi@6000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
mmc@b000 {
|
||||
compatible = "arm,primecell";
|
||||
reg = <0xb000 0x1000>;
|
||||
interrupts = <23>;
|
||||
interrupts = <23 34>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_ARCH_S3C24XX=y
|
||||
# CONFIG_CPU_S3C2410 is not set
|
||||
CONFIG_CPU_S3C2440=y
|
||||
CONFIG_S3C_ADC=y
|
||||
CONFIG_S3C24XX_PWM=y
|
||||
CONFIG_MACH_MINI2440=y
|
||||
|
|
|
@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
|
|||
extern void vfp_sync_hwstate(struct thread_info *);
|
||||
extern void vfp_flush_hwstate(struct thread_info *);
|
||||
|
||||
struct user_vfp;
|
||||
struct user_vfp_exc;
|
||||
|
||||
extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
|
||||
struct user_vfp_exc __user *);
|
||||
extern int vfp_restore_user_hwstate(struct user_vfp __user *,
|
||||
struct user_vfp_exc __user *);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -7,6 +7,8 @@
|
|||
|
||||
.macro set_tls_v6k, tp, tmp1, tmp2
|
||||
mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
|
||||
mov \tmp1, #0
|
||||
mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
|
||||
.endm
|
||||
|
||||
.macro set_tls_v6, tp, tmp1, tmp2
|
||||
|
@ -15,6 +17,8 @@
|
|||
mov \tmp2, #0xffff0fff
|
||||
tst \tmp1, #HWCAP_TLS @ hardware TLS available?
|
||||
mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
|
||||
movne \tmp1, #0
|
||||
mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
|
||||
streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
|
||||
.endm
|
||||
|
||||
|
|
|
@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
|
|||
}
|
||||
|
||||
c = irq_data_get_irq_chip(d);
|
||||
if (c->irq_set_affinity)
|
||||
c->irq_set_affinity(d, affinity, true);
|
||||
else
|
||||
if (!c->irq_set_affinity)
|
||||
pr_debug("IRQ%u: unable to set affinity\n", d->irq);
|
||||
else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
|
||||
cpumask_copy(d->affinity, affinity);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
|
|||
|
||||
static int preserve_vfp_context(struct vfp_sigframe __user *frame)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *h = &thread->vfpstate.hard;
|
||||
const unsigned long magic = VFP_MAGIC;
|
||||
const unsigned long size = VFP_STORAGE_SIZE;
|
||||
int err = 0;
|
||||
|
||||
vfp_sync_hwstate(thread);
|
||||
__put_user_error(magic, &frame->magic, err);
|
||||
__put_user_error(size, &frame->size, err);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
|
||||
sizeof(h->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__put_user_error(h->fpscr, &frame->ufp.fpscr, err);
|
||||
if (err)
|
||||
return -EFAULT;
|
||||
|
||||
/*
|
||||
* Copy the exception registers.
|
||||
*/
|
||||
__put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
|
||||
__put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
|
||||
__put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
|
||||
}
|
||||
|
||||
static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *h = &thread->vfpstate.hard;
|
||||
unsigned long magic;
|
||||
unsigned long size;
|
||||
unsigned long fpexc;
|
||||
int err = 0;
|
||||
|
||||
__get_user_error(magic, &frame->magic, err);
|
||||
|
@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
|
|||
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
|
||||
sizeof(h->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__get_user_error(h->fpscr, &frame->ufp.fpscr, err);
|
||||
|
||||
/*
|
||||
* Sanitise and restore the exception registers.
|
||||
*/
|
||||
__get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
|
||||
/* Ensure the VFP is enabled. */
|
||||
fpexc |= FPEXC_EN;
|
||||
/* Ensure FPINST2 is invalid and the exception flag is cleared. */
|
||||
fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
|
||||
h->fpexc = fpexc;
|
||||
|
||||
__get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
|
||||
__get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -510,10 +510,6 @@ static void ipi_cpu_stop(unsigned int cpu)
|
|||
local_fiq_disable();
|
||||
local_irq_disable();
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
platform_cpu_kill(cpu);
|
||||
#endif
|
||||
|
||||
while (1)
|
||||
cpu_relax();
|
||||
}
|
||||
|
@ -576,17 +572,25 @@ void smp_send_reschedule(int cpu)
|
|||
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static void smp_kill_cpus(cpumask_t *mask)
|
||||
{
|
||||
unsigned int cpu;
|
||||
for_each_cpu(cpu, mask)
|
||||
platform_cpu_kill(cpu);
|
||||
}
|
||||
#else
|
||||
static void smp_kill_cpus(cpumask_t *mask) { }
|
||||
#endif
|
||||
|
||||
void smp_send_stop(void)
|
||||
{
|
||||
unsigned long timeout;
|
||||
struct cpumask mask;
|
||||
|
||||
if (num_online_cpus() > 1) {
|
||||
struct cpumask mask;
|
||||
cpumask_copy(&mask, cpu_online_mask);
|
||||
cpumask_clear_cpu(smp_processor_id(), &mask);
|
||||
|
||||
smp_cross_call(&mask, IPI_CPU_STOP);
|
||||
}
|
||||
cpumask_copy(&mask, cpu_online_mask);
|
||||
cpumask_clear_cpu(smp_processor_id(), &mask);
|
||||
smp_cross_call(&mask, IPI_CPU_STOP);
|
||||
|
||||
/* Wait up to one second for other CPUs to stop */
|
||||
timeout = USEC_PER_SEC;
|
||||
|
@ -595,6 +599,8 @@ void smp_send_stop(void)
|
|||
|
||||
if (num_online_cpus() > 1)
|
||||
pr_warning("SMP: failed to stop secondary CPUs\n");
|
||||
|
||||
smp_kill_cpus(&mask);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
|
|||
* The twd clock events must be reprogrammed to account for the new
|
||||
* frequency. The timer is local to a cpu, so cross-call to the
|
||||
* changing cpu.
|
||||
*
|
||||
* Only wait for it to finish, if the cpu is active to avoid
|
||||
* deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
|
||||
* booting of that cpu.
|
||||
*/
|
||||
if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
|
||||
smp_call_function_single(freqs->cpu, twd_update_frequency,
|
||||
NULL, cpu_active(freqs->cpu));
|
||||
NULL, 1);
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
|
|
@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos4_clk_dout_mmc0.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos4_clk_dout_mmc1.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos4_clk_dout_mmc2.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos4_clk_dout_mmc3.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
|
|||
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
|
||||
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
|
||||
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
|
||||
|
|
|
@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 20),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 14),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 15),
|
||||
|
@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos5_clk_dout_mmc0.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos5_clk_dout_mmc1.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos5_clk_dout_mmc2.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos5_clk_dout_mmc3.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
|
|||
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
|
||||
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
|
||||
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
|
||||
|
|
|
@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
|
|||
s3c_fimc_setname(2, "exynos4-fimc");
|
||||
s3c_fimc_setname(3, "exynos4-fimc");
|
||||
|
||||
s3c_sdhci_setname(0, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(1, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(2, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(3, "exynos4-sdhci");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
|
@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
|
|||
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
|
||||
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
|
||||
|
||||
s3c_sdhci_setname(0, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(1, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(2, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(3, "exynos4-sdhci");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
|
@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
|
|||
{
|
||||
int irq;
|
||||
|
||||
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
|
||||
#ifdef CONFIG_OF
|
||||
of_irq_init(exynos4_dt_irq_match);
|
||||
#endif
|
||||
|
||||
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
|
||||
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mmc/dw_mmc.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
|
|||
}
|
||||
|
||||
static struct resource exynos4_dwmci_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_DWMCI,
|
||||
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_DWMCI,
|
||||
.end = IRQ_DWMCI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
|
||||
};
|
||||
|
||||
static struct dw_mci_board exynos4_dwci_pdata = {
|
||||
|
|
|
@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
|
|||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_ERASE),
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
|
|
@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
|
|||
.max_width = 8,
|
||||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
|
@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
|
|||
msm_map_msm8x60_io();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct of_device_id msm_dt_gic_match[] __initdata = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static void __init msm8x60_init_irq(void)
|
||||
{
|
||||
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
||||
(void *)MSM_QGIC_CPU_BASE);
|
||||
if (!of_have_populated_dt())
|
||||
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
||||
(void *)MSM_QGIC_CPU_BASE);
|
||||
#ifdef CONFIG_OF
|
||||
else
|
||||
of_irq_init(msm_dt_gic_match);
|
||||
#endif
|
||||
|
||||
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
|
||||
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
|
||||
|
@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
|
|||
{}
|
||||
};
|
||||
|
||||
static struct of_device_id msm_dt_gic_match[] __initdata = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init msm8x60_dt_init(void)
|
||||
{
|
||||
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
|
||||
GIC_SPI_START);
|
||||
|
||||
if (of_machine_is_compatible("qcom,msm8660-surf")) {
|
||||
printk(KERN_INFO "Init surf UART registers\n");
|
||||
msm8x60_init_uart12dm();
|
||||
|
|
|
@ -1,12 +1,9 @@
|
|||
# Common support
|
||||
obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
|
||||
obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o
|
||||
|
||||
obj-$(CONFIG_MXS_OCOTP) += ocotp.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
|
||||
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
|
||||
|
||||
obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
|
||||
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
|
||||
obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
|
||||
|
|
|
@ -1,536 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#include <asm/clkdev.h>
|
||||
#include <asm/div64.h>
|
||||
|
||||
#include <mach/mx23.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/clock.h>
|
||||
|
||||
#include "regs-clkctrl-mx23.h"
|
||||
|
||||
#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
|
||||
#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
|
||||
|
||||
#define PARENT_RATE_SHIFT 8
|
||||
|
||||
static int _raw_clk_enable(struct clk *clk)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (clk->enable_reg) {
|
||||
reg = __raw_readl(clk->enable_reg);
|
||||
reg &= ~(1 << clk->enable_shift);
|
||||
__raw_writel(reg, clk->enable_reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void _raw_clk_disable(struct clk *clk)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (clk->enable_reg) {
|
||||
reg = __raw_readl(clk->enable_reg);
|
||||
reg |= 1 << clk->enable_shift;
|
||||
__raw_writel(reg, clk->enable_reg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* ref_xtal_clk
|
||||
*/
|
||||
static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 24000000;
|
||||
}
|
||||
|
||||
static struct clk ref_xtal_clk = {
|
||||
.get_rate = ref_xtal_clk_get_rate,
|
||||
};
|
||||
|
||||
/*
|
||||
* pll_clk
|
||||
*/
|
||||
static unsigned long pll_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 480000000;
|
||||
}
|
||||
|
||||
static int pll_clk_enable(struct clk *clk)
|
||||
{
|
||||
__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
|
||||
BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
|
||||
|
||||
/* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
|
||||
* and is incorrect (excessive). Per definition of the PLLCTRL0
|
||||
* POWER field, waiting at least 10us.
|
||||
*/
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pll_clk_disable(struct clk *clk)
|
||||
{
|
||||
__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
|
||||
BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
|
||||
}
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.get_rate = pll_clk_get_rate,
|
||||
.enable = pll_clk_enable,
|
||||
.disable = pll_clk_disable,
|
||||
.parent = &ref_xtal_clk,
|
||||
};
|
||||
|
||||
/*
|
||||
* ref_clk
|
||||
*/
|
||||
#define _CLK_GET_RATE_REF(name, sr, ss) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
unsigned long parent_rate; \
|
||||
u32 reg, div; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
|
||||
div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
\
|
||||
return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
|
||||
div, PARENT_RATE_SHIFT); \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
|
||||
_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
|
||||
_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
|
||||
_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
|
||||
|
||||
#define _DEFINE_CLOCK_REF(name, er, es) \
|
||||
static struct clk name = { \
|
||||
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
|
||||
.enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
|
||||
.get_rate = name##_get_rate, \
|
||||
.enable = _raw_clk_enable, \
|
||||
.disable = _raw_clk_disable, \
|
||||
.parent = &pll_clk, \
|
||||
}
|
||||
|
||||
_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
|
||||
_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
|
||||
_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
|
||||
_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
|
||||
|
||||
/*
|
||||
* General clocks
|
||||
*
|
||||
* clk_get_rate
|
||||
*/
|
||||
static unsigned long rtc_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
/* ref_xtal_clk is implemented as the only parent */
|
||||
return clk_get_rate(clk->parent) / 768;
|
||||
}
|
||||
|
||||
static unsigned long clk32k_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk->parent->get_rate(clk->parent) / 750;
|
||||
}
|
||||
|
||||
#define _CLK_GET_RATE(name, rs) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
u32 reg, div; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
|
||||
\
|
||||
if (clk->parent == &ref_xtal_clk) \
|
||||
div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
|
||||
BP_CLKCTRL_##rs##_DIV_XTAL; \
|
||||
else \
|
||||
div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
|
||||
BP_CLKCTRL_##rs##_DIV_##rs; \
|
||||
\
|
||||
if (!div) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
return clk_get_rate(clk->parent) / div; \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE(cpu_clk, CPU)
|
||||
_CLK_GET_RATE(emi_clk, EMI)
|
||||
|
||||
#define _CLK_GET_RATE1(name, rs) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
u32 reg, div; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
|
||||
div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
|
||||
\
|
||||
if (!div) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
return clk_get_rate(clk->parent) / div; \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE1(hbus_clk, HBUS)
|
||||
_CLK_GET_RATE1(xbus_clk, XBUS)
|
||||
_CLK_GET_RATE1(ssp_clk, SSP)
|
||||
_CLK_GET_RATE1(gpmi_clk, GPMI)
|
||||
_CLK_GET_RATE1(lcdif_clk, PIX)
|
||||
|
||||
#define _CLK_GET_RATE_STUB(name) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
return clk_get_rate(clk->parent); \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE_STUB(uart_clk)
|
||||
_CLK_GET_RATE_STUB(audio_clk)
|
||||
_CLK_GET_RATE_STUB(pwm_clk)
|
||||
|
||||
/*
|
||||
* clk_set_rate
|
||||
*/
|
||||
static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 reg, bm_busy, div_max, d, f, div, frac;
|
||||
unsigned long diff, parent_rate, calc_rate;
|
||||
|
||||
parent_rate = clk_get_rate(clk->parent);
|
||||
|
||||
if (clk->parent == &ref_xtal_clk) {
|
||||
div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
|
||||
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
|
||||
div = DIV_ROUND_UP(parent_rate, rate);
|
||||
if (div == 0 || div > div_max)
|
||||
return -EINVAL;
|
||||
} else {
|
||||
div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
|
||||
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
|
||||
rate >>= PARENT_RATE_SHIFT;
|
||||
parent_rate >>= PARENT_RATE_SHIFT;
|
||||
diff = parent_rate;
|
||||
div = frac = 1;
|
||||
for (d = 1; d <= div_max; d++) {
|
||||
f = parent_rate * 18 / d / rate;
|
||||
if ((parent_rate * 18 / d) % rate)
|
||||
f++;
|
||||
if (f < 18 || f > 35)
|
||||
continue;
|
||||
|
||||
calc_rate = parent_rate * 18 / f / d;
|
||||
if (calc_rate > rate)
|
||||
continue;
|
||||
|
||||
if (rate - calc_rate < diff) {
|
||||
frac = f;
|
||||
div = d;
|
||||
diff = rate - calc_rate;
|
||||
}
|
||||
|
||||
if (diff == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (diff == parent_rate)
|
||||
return -EINVAL;
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
||||
reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
|
||||
reg |= frac;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
||||
}
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
|
||||
reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
|
||||
reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
|
||||
|
||||
mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define _CLK_SET_RATE(name, dr) \
|
||||
static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
||||
{ \
|
||||
u32 reg, div_max, div; \
|
||||
unsigned long parent_rate; \
|
||||
\
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
|
||||
\
|
||||
div = DIV_ROUND_UP(parent_rate, rate); \
|
||||
if (div == 0 || div > div_max) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
|
||||
reg &= ~BM_CLKCTRL_##dr##_DIV; \
|
||||
reg |= div << BP_CLKCTRL_##dr##_DIV; \
|
||||
if (reg & (1 << clk->enable_shift)) { \
|
||||
pr_err("%s: clock is gated\n", __func__); \
|
||||
return -EINVAL; \
|
||||
} \
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
|
||||
\
|
||||
mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
_CLK_SET_RATE(xbus_clk, XBUS)
|
||||
_CLK_SET_RATE(ssp_clk, SSP)
|
||||
_CLK_SET_RATE(gpmi_clk, GPMI)
|
||||
_CLK_SET_RATE(lcdif_clk, PIX)
|
||||
|
||||
#define _CLK_SET_RATE_STUB(name) \
|
||||
static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
||||
{ \
|
||||
return -EINVAL; \
|
||||
}
|
||||
|
||||
_CLK_SET_RATE_STUB(emi_clk)
|
||||
_CLK_SET_RATE_STUB(uart_clk)
|
||||
_CLK_SET_RATE_STUB(audio_clk)
|
||||
_CLK_SET_RATE_STUB(pwm_clk)
|
||||
_CLK_SET_RATE_STUB(clk32k_clk)
|
||||
|
||||
/*
|
||||
* clk_set_parent
|
||||
*/
|
||||
#define _CLK_SET_PARENT(name, bit) \
|
||||
static int name##_set_parent(struct clk *clk, struct clk *parent) \
|
||||
{ \
|
||||
if (parent != clk->parent) { \
|
||||
__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
|
||||
clk->parent = parent; \
|
||||
} \
|
||||
\
|
||||
return 0; \
|
||||
}
|
||||
|
||||
_CLK_SET_PARENT(cpu_clk, CPU)
|
||||
_CLK_SET_PARENT(emi_clk, EMI)
|
||||
_CLK_SET_PARENT(ssp_clk, SSP)
|
||||
_CLK_SET_PARENT(gpmi_clk, GPMI)
|
||||
_CLK_SET_PARENT(lcdif_clk, PIX)
|
||||
|
||||
#define _CLK_SET_PARENT_STUB(name) \
|
||||
static int name##_set_parent(struct clk *clk, struct clk *parent) \
|
||||
{ \
|
||||
if (parent != clk->parent) \
|
||||
return -EINVAL; \
|
||||
else \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
_CLK_SET_PARENT_STUB(uart_clk)
|
||||
_CLK_SET_PARENT_STUB(audio_clk)
|
||||
_CLK_SET_PARENT_STUB(pwm_clk)
|
||||
_CLK_SET_PARENT_STUB(clk32k_clk)
|
||||
|
||||
/*
|
||||
* clk definition
|
||||
*/
|
||||
static struct clk cpu_clk = {
|
||||
.get_rate = cpu_clk_get_rate,
|
||||
.set_rate = cpu_clk_set_rate,
|
||||
.set_parent = cpu_clk_set_parent,
|
||||
.parent = &ref_cpu_clk,
|
||||
};
|
||||
|
||||
static struct clk hbus_clk = {
|
||||
.get_rate = hbus_clk_get_rate,
|
||||
.parent = &cpu_clk,
|
||||
};
|
||||
|
||||
static struct clk xbus_clk = {
|
||||
.get_rate = xbus_clk_get_rate,
|
||||
.set_rate = xbus_clk_set_rate,
|
||||
.parent = &ref_xtal_clk,
|
||||
};
|
||||
|
||||
static struct clk rtc_clk = {
|
||||
.get_rate = rtc_clk_get_rate,
|
||||
.parent = &ref_xtal_clk,
|
||||
};
|
||||
|
||||
/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
|
||||
static struct clk usb_clk = {
|
||||
.enable_reg = DIGCTRL_BASE_ADDR,
|
||||
.enable_shift = 2,
|
||||
.enable = _raw_clk_enable,
|
||||
.disable = _raw_clk_disable,
|
||||
.parent = &pll_clk,
|
||||
};
|
||||
|
||||
#define _DEFINE_CLOCK(name, er, es, p) \
|
||||
static struct clk name = { \
|
||||
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
|
||||
.enable_shift = BP_CLKCTRL_##er##_##es, \
|
||||
.get_rate = name##_get_rate, \
|
||||
.set_rate = name##_set_rate, \
|
||||
.set_parent = name##_set_parent, \
|
||||
.enable = _raw_clk_enable, \
|
||||
.disable = _raw_clk_disable, \
|
||||
.parent = p, \
|
||||
}
|
||||
|
||||
_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
|
||||
|
||||
#define _REGISTER_CLOCK(d, n, c) \
|
||||
{ \
|
||||
.dev_id = d, \
|
||||
.con_id = n, \
|
||||
.clk = &c, \
|
||||
},
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* for amba bus driver */
|
||||
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
|
||||
/* for amba-pl011 driver */
|
||||
_REGISTER_CLOCK("duart", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
|
||||
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
|
||||
_REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
|
||||
_REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
|
||||
_REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
|
||||
_REGISTER_CLOCK(NULL, "usb", usb_clk)
|
||||
_REGISTER_CLOCK(NULL, "audio", audio_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
|
||||
_REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
|
||||
};
|
||||
|
||||
static int clk_misc_init(void)
|
||||
{
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
||||
/* Fix up parent per register setting */
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
|
||||
cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
|
||||
&ref_xtal_clk : &ref_cpu_clk;
|
||||
emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
|
||||
&ref_xtal_clk : &ref_emi_clk;
|
||||
ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
|
||||
&ref_xtal_clk : &ref_io_clk;
|
||||
gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
|
||||
&ref_xtal_clk : &ref_io_clk;
|
||||
lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
|
||||
&ref_xtal_clk : &ref_pix_clk;
|
||||
|
||||
/* Use int div over frac when both are available */
|
||||
__raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
|
||||
__raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
|
||||
__raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
||||
reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
|
||||
reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
|
||||
reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
|
||||
reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
|
||||
|
||||
/*
|
||||
* Set safe hbus clock divider. A divider of 3 ensure that
|
||||
* the Vddd voltage required for the cpu clock is sufficiently
|
||||
* high for the hbus clock.
|
||||
*/
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
||||
reg &= BM_CLKCTRL_HBUS_DIV;
|
||||
reg |= 3 << BP_CLKCTRL_HBUS_DIV;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
||||
|
||||
ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
|
||||
|
||||
/* Gate off cpu clock in WFI for power saving */
|
||||
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
|
||||
|
||||
/*
|
||||
* 480 MHz seems too high to be ssp clock source directly,
|
||||
* so set frac to get a 288 MHz ref_io.
|
||||
*/
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
||||
reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
|
||||
reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __init mx23_clocks_init(void)
|
||||
{
|
||||
clk_misc_init();
|
||||
|
||||
/*
|
||||
* source ssp clock from ref_io than ref_xtal,
|
||||
* as ref_xtal only provides 24 MHz as maximum.
|
||||
*/
|
||||
clk_set_parent(&ssp_clk, &ref_io_clk);
|
||||
|
||||
clk_prepare_enable(&cpu_clk);
|
||||
clk_prepare_enable(&hbus_clk);
|
||||
clk_prepare_enable(&xbus_clk);
|
||||
clk_prepare_enable(&emi_clk);
|
||||
clk_prepare_enable(&uart_clk);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -1,803 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/clkdev.h>
|
||||
#include <asm/div64.h>
|
||||
|
||||
#include <mach/mx28.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/digctl.h>
|
||||
|
||||
#include "regs-clkctrl-mx28.h"
|
||||
|
||||
#define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
|
||||
#define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
|
||||
|
||||
#define PARENT_RATE_SHIFT 8
|
||||
|
||||
static struct clk pll2_clk;
|
||||
static struct clk cpu_clk;
|
||||
static struct clk emi_clk;
|
||||
static struct clk saif0_clk;
|
||||
static struct clk saif1_clk;
|
||||
static struct clk clk32k_clk;
|
||||
static DEFINE_SPINLOCK(clkmux_lock);
|
||||
|
||||
/*
|
||||
* HW_SAIF_CLKMUX_SEL:
|
||||
* DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
|
||||
* clock pins selected for SAIF1 input clocks.
|
||||
* CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
|
||||
* SAIF0 clock inputs selected for SAIF1 input clocks.
|
||||
* EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
|
||||
* clocks.
|
||||
* EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
|
||||
* clocks.
|
||||
*/
|
||||
int mxs_saif_clkmux_select(unsigned int clkmux)
|
||||
{
|
||||
if (clkmux > 0x3)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock(&clkmux_lock);
|
||||
__raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
|
||||
DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
|
||||
__raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
|
||||
DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
|
||||
spin_unlock(&clkmux_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _raw_clk_enable(struct clk *clk)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (clk->enable_reg) {
|
||||
reg = __raw_readl(clk->enable_reg);
|
||||
reg &= ~(1 << clk->enable_shift);
|
||||
__raw_writel(reg, clk->enable_reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void _raw_clk_disable(struct clk *clk)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (clk->enable_reg) {
|
||||
reg = __raw_readl(clk->enable_reg);
|
||||
reg |= 1 << clk->enable_shift;
|
||||
__raw_writel(reg, clk->enable_reg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* ref_xtal_clk
|
||||
*/
|
||||
static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 24000000;
|
||||
}
|
||||
|
||||
static struct clk ref_xtal_clk = {
|
||||
.get_rate = ref_xtal_clk_get_rate,
|
||||
};
|
||||
|
||||
/*
|
||||
* pll_clk
|
||||
*/
|
||||
static unsigned long pll0_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 480000000;
|
||||
}
|
||||
|
||||
static unsigned long pll1_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 480000000;
|
||||
}
|
||||
|
||||
static unsigned long pll2_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 50000000;
|
||||
}
|
||||
|
||||
#define _CLK_ENABLE_PLL(name, r, g) \
|
||||
static int name##_enable(struct clk *clk) \
|
||||
{ \
|
||||
__raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
|
||||
udelay(10); \
|
||||
\
|
||||
if (clk == &pll2_clk) \
|
||||
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
|
||||
else \
|
||||
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
|
||||
\
|
||||
return 0; \
|
||||
}
|
||||
|
||||
_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
|
||||
_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
|
||||
_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
|
||||
|
||||
#define _CLK_DISABLE_PLL(name, r, g) \
|
||||
static void name##_disable(struct clk *clk) \
|
||||
{ \
|
||||
__raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
|
||||
\
|
||||
if (clk == &pll2_clk) \
|
||||
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
|
||||
else \
|
||||
__raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
|
||||
\
|
||||
}
|
||||
|
||||
_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
|
||||
_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
|
||||
_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
|
||||
|
||||
#define _DEFINE_CLOCK_PLL(name) \
|
||||
static struct clk name = { \
|
||||
.get_rate = name##_get_rate, \
|
||||
.enable = name##_enable, \
|
||||
.disable = name##_disable, \
|
||||
.parent = &ref_xtal_clk, \
|
||||
}
|
||||
|
||||
_DEFINE_CLOCK_PLL(pll0_clk);
|
||||
_DEFINE_CLOCK_PLL(pll1_clk);
|
||||
_DEFINE_CLOCK_PLL(pll2_clk);
|
||||
|
||||
/*
|
||||
* ref_clk
|
||||
*/
|
||||
#define _CLK_GET_RATE_REF(name, sr, ss) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
unsigned long parent_rate; \
|
||||
u32 reg, div; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
|
||||
div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
\
|
||||
return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
|
||||
div, PARENT_RATE_SHIFT); \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
|
||||
_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
|
||||
_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
|
||||
_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
|
||||
_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
|
||||
_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
|
||||
|
||||
#define _DEFINE_CLOCK_REF(name, er, es) \
|
||||
static struct clk name = { \
|
||||
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
|
||||
.enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
|
||||
.get_rate = name##_get_rate, \
|
||||
.enable = _raw_clk_enable, \
|
||||
.disable = _raw_clk_disable, \
|
||||
.parent = &pll0_clk, \
|
||||
}
|
||||
|
||||
_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
|
||||
_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
|
||||
_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
|
||||
_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
|
||||
_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
|
||||
_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
|
||||
|
||||
/*
|
||||
* General clocks
|
||||
*
|
||||
* clk_get_rate
|
||||
*/
|
||||
static unsigned long lradc_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk_get_rate(clk->parent) / 16;
|
||||
}
|
||||
|
||||
static unsigned long rtc_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
/* ref_xtal_clk is implemented as the only parent */
|
||||
return clk_get_rate(clk->parent) / 768;
|
||||
}
|
||||
|
||||
static unsigned long clk32k_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk->parent->get_rate(clk->parent) / 750;
|
||||
}
|
||||
|
||||
static unsigned long spdif_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk_get_rate(clk->parent) / 4;
|
||||
}
|
||||
|
||||
#define _CLK_GET_RATE(name, rs) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
u32 reg, div; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
|
||||
\
|
||||
if (clk->parent == &ref_xtal_clk) \
|
||||
div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
|
||||
BP_CLKCTRL_##rs##_DIV_XTAL; \
|
||||
else \
|
||||
div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
|
||||
BP_CLKCTRL_##rs##_DIV_##rs; \
|
||||
\
|
||||
if (!div) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
return clk_get_rate(clk->parent) / div; \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE(cpu_clk, CPU)
|
||||
_CLK_GET_RATE(emi_clk, EMI)
|
||||
|
||||
#define _CLK_GET_RATE1(name, rs) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
u32 reg, div; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
|
||||
div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
|
||||
\
|
||||
if (!div) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
if (clk == &saif0_clk || clk == &saif1_clk) \
|
||||
return clk_get_rate(clk->parent) >> 16 * div; \
|
||||
else \
|
||||
return clk_get_rate(clk->parent) / div; \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE1(hbus_clk, HBUS)
|
||||
_CLK_GET_RATE1(xbus_clk, XBUS)
|
||||
_CLK_GET_RATE1(ssp0_clk, SSP0)
|
||||
_CLK_GET_RATE1(ssp1_clk, SSP1)
|
||||
_CLK_GET_RATE1(ssp2_clk, SSP2)
|
||||
_CLK_GET_RATE1(ssp3_clk, SSP3)
|
||||
_CLK_GET_RATE1(gpmi_clk, GPMI)
|
||||
_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
|
||||
_CLK_GET_RATE1(saif0_clk, SAIF0)
|
||||
_CLK_GET_RATE1(saif1_clk, SAIF1)
|
||||
|
||||
#define _CLK_GET_RATE_STUB(name) \
|
||||
static unsigned long name##_get_rate(struct clk *clk) \
|
||||
{ \
|
||||
return clk_get_rate(clk->parent); \
|
||||
}
|
||||
|
||||
_CLK_GET_RATE_STUB(uart_clk)
|
||||
_CLK_GET_RATE_STUB(pwm_clk)
|
||||
_CLK_GET_RATE_STUB(can0_clk)
|
||||
_CLK_GET_RATE_STUB(can1_clk)
|
||||
_CLK_GET_RATE_STUB(fec_clk)
|
||||
|
||||
/*
|
||||
* clk_set_rate
|
||||
*/
|
||||
/* fool compiler */
|
||||
#define BM_CLKCTRL_CPU_DIV 0
|
||||
#define BP_CLKCTRL_CPU_DIV 0
|
||||
#define BM_CLKCTRL_CPU_BUSY 0
|
||||
|
||||
#define _CLK_SET_RATE(name, dr, fr, fs) \
|
||||
static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
||||
{ \
|
||||
u32 reg, bm_busy, div_max, d, f, div, frac; \
|
||||
unsigned long diff, parent_rate, calc_rate; \
|
||||
\
|
||||
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
|
||||
bm_busy = BM_CLKCTRL_##dr##_BUSY; \
|
||||
\
|
||||
if (clk->parent == &ref_xtal_clk) { \
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
div = DIV_ROUND_UP(parent_rate, rate); \
|
||||
if (clk == &cpu_clk) { \
|
||||
div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
|
||||
BP_CLKCTRL_CPU_DIV_XTAL; \
|
||||
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
|
||||
} \
|
||||
if (div == 0 || div > div_max) \
|
||||
return -EINVAL; \
|
||||
} else { \
|
||||
/* \
|
||||
* hack alert: this block modifies clk->parent, too, \
|
||||
* so the base to use it the grand parent. \
|
||||
*/ \
|
||||
parent_rate = clk_get_rate(clk->parent->parent); \
|
||||
rate >>= PARENT_RATE_SHIFT; \
|
||||
parent_rate >>= PARENT_RATE_SHIFT; \
|
||||
diff = parent_rate; \
|
||||
div = frac = 1; \
|
||||
if (clk == &cpu_clk) { \
|
||||
div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
|
||||
BP_CLKCTRL_CPU_DIV_CPU; \
|
||||
bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
|
||||
} \
|
||||
for (d = 1; d <= div_max; d++) { \
|
||||
f = parent_rate * 18 / d / rate; \
|
||||
if ((parent_rate * 18 / d) % rate) \
|
||||
f++; \
|
||||
if (f < 18 || f > 35) \
|
||||
continue; \
|
||||
\
|
||||
calc_rate = parent_rate * 18 / f / d; \
|
||||
if (calc_rate > rate) \
|
||||
continue; \
|
||||
\
|
||||
if (rate - calc_rate < diff) { \
|
||||
frac = f; \
|
||||
div = d; \
|
||||
diff = rate - calc_rate; \
|
||||
} \
|
||||
\
|
||||
if (diff == 0) \
|
||||
break; \
|
||||
} \
|
||||
\
|
||||
if (diff == parent_rate) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
|
||||
reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
|
||||
reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
|
||||
} \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
|
||||
if (clk == &cpu_clk) { \
|
||||
reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
|
||||
reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
|
||||
} else { \
|
||||
reg &= ~BM_CLKCTRL_##dr##_DIV; \
|
||||
reg |= div << BP_CLKCTRL_##dr##_DIV; \
|
||||
if (reg & (1 << clk->enable_shift)) { \
|
||||
pr_err("%s: clock is gated\n", __func__); \
|
||||
return -EINVAL; \
|
||||
} \
|
||||
} \
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
|
||||
\
|
||||
return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy); \
|
||||
}
|
||||
|
||||
_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
|
||||
_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
|
||||
_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
|
||||
_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
|
||||
_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
|
||||
_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
|
||||
_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
|
||||
|
||||
#define _CLK_SET_RATE1(name, dr) \
|
||||
static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
||||
{ \
|
||||
u32 reg, div_max, div; \
|
||||
unsigned long parent_rate; \
|
||||
\
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
|
||||
\
|
||||
div = DIV_ROUND_UP(parent_rate, rate); \
|
||||
if (div == 0 || div > div_max) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
|
||||
reg &= ~BM_CLKCTRL_##dr##_DIV; \
|
||||
reg |= div << BP_CLKCTRL_##dr##_DIV; \
|
||||
if (reg & (1 << clk->enable_shift)) { \
|
||||
pr_err("%s: clock is gated\n", __func__); \
|
||||
return -EINVAL; \
|
||||
} \
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
|
||||
\
|
||||
return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
|
||||
}
|
||||
|
||||
_CLK_SET_RATE1(xbus_clk, XBUS)
|
||||
|
||||
/* saif clock uses 16 bits frac div */
|
||||
#define _CLK_SET_RATE_SAIF(name, rs) \
|
||||
static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
||||
{ \
|
||||
u16 div; \
|
||||
u32 reg; \
|
||||
u64 lrate; \
|
||||
unsigned long parent_rate; \
|
||||
\
|
||||
parent_rate = clk_get_rate(clk->parent); \
|
||||
if (rate > parent_rate) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
lrate = (u64)rate << 16; \
|
||||
do_div(lrate, parent_rate); \
|
||||
div = (u16)lrate; \
|
||||
\
|
||||
if (!div) \
|
||||
return -EINVAL; \
|
||||
\
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
|
||||
reg &= ~BM_CLKCTRL_##rs##_DIV; \
|
||||
reg |= div << BP_CLKCTRL_##rs##_DIV; \
|
||||
if (reg & (1 << clk->enable_shift)) { \
|
||||
pr_err("%s: clock is gated\n", __func__); \
|
||||
return -EINVAL; \
|
||||
} \
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
|
||||
\
|
||||
return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
|
||||
}
|
||||
|
||||
_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
|
||||
_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
|
||||
|
||||
#define _CLK_SET_RATE_STUB(name) \
|
||||
static int name##_set_rate(struct clk *clk, unsigned long rate) \
|
||||
{ \
|
||||
return -EINVAL; \
|
||||
}
|
||||
|
||||
_CLK_SET_RATE_STUB(emi_clk)
|
||||
_CLK_SET_RATE_STUB(uart_clk)
|
||||
_CLK_SET_RATE_STUB(pwm_clk)
|
||||
_CLK_SET_RATE_STUB(spdif_clk)
|
||||
_CLK_SET_RATE_STUB(clk32k_clk)
|
||||
_CLK_SET_RATE_STUB(can0_clk)
|
||||
_CLK_SET_RATE_STUB(can1_clk)
|
||||
_CLK_SET_RATE_STUB(fec_clk)
|
||||
|
||||
/*
|
||||
* clk_set_parent
|
||||
*/
|
||||
#define _CLK_SET_PARENT(name, bit) \
|
||||
static int name##_set_parent(struct clk *clk, struct clk *parent) \
|
||||
{ \
|
||||
if (parent != clk->parent) { \
|
||||
__raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
|
||||
clk->parent = parent; \
|
||||
} \
|
||||
\
|
||||
return 0; \
|
||||
}
|
||||
|
||||
_CLK_SET_PARENT(cpu_clk, CPU)
|
||||
_CLK_SET_PARENT(emi_clk, EMI)
|
||||
_CLK_SET_PARENT(ssp0_clk, SSP0)
|
||||
_CLK_SET_PARENT(ssp1_clk, SSP1)
|
||||
_CLK_SET_PARENT(ssp2_clk, SSP2)
|
||||
_CLK_SET_PARENT(ssp3_clk, SSP3)
|
||||
_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
|
||||
_CLK_SET_PARENT(gpmi_clk, GPMI)
|
||||
_CLK_SET_PARENT(saif0_clk, SAIF0)
|
||||
_CLK_SET_PARENT(saif1_clk, SAIF1)
|
||||
|
||||
#define _CLK_SET_PARENT_STUB(name) \
|
||||
static int name##_set_parent(struct clk *clk, struct clk *parent) \
|
||||
{ \
|
||||
if (parent != clk->parent) \
|
||||
return -EINVAL; \
|
||||
else \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
_CLK_SET_PARENT_STUB(pwm_clk)
|
||||
_CLK_SET_PARENT_STUB(uart_clk)
|
||||
_CLK_SET_PARENT_STUB(clk32k_clk)
|
||||
_CLK_SET_PARENT_STUB(spdif_clk)
|
||||
_CLK_SET_PARENT_STUB(fec_clk)
|
||||
_CLK_SET_PARENT_STUB(can0_clk)
|
||||
_CLK_SET_PARENT_STUB(can1_clk)
|
||||
|
||||
/*
|
||||
* clk definition
|
||||
*/
|
||||
static struct clk cpu_clk = {
|
||||
.get_rate = cpu_clk_get_rate,
|
||||
.set_rate = cpu_clk_set_rate,
|
||||
.set_parent = cpu_clk_set_parent,
|
||||
.parent = &ref_cpu_clk,
|
||||
};
|
||||
|
||||
static struct clk hbus_clk = {
|
||||
.get_rate = hbus_clk_get_rate,
|
||||
.parent = &cpu_clk,
|
||||
};
|
||||
|
||||
static struct clk xbus_clk = {
|
||||
.get_rate = xbus_clk_get_rate,
|
||||
.set_rate = xbus_clk_set_rate,
|
||||
.parent = &ref_xtal_clk,
|
||||
};
|
||||
|
||||
static struct clk lradc_clk = {
|
||||
.get_rate = lradc_clk_get_rate,
|
||||
.parent = &clk32k_clk,
|
||||
};
|
||||
|
||||
static struct clk rtc_clk = {
|
||||
.get_rate = rtc_clk_get_rate,
|
||||
.parent = &ref_xtal_clk,
|
||||
};
|
||||
|
||||
/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
|
||||
static struct clk usb0_clk = {
|
||||
.enable_reg = DIGCTRL_BASE_ADDR,
|
||||
.enable_shift = 2,
|
||||
.enable = _raw_clk_enable,
|
||||
.disable = _raw_clk_disable,
|
||||
.parent = &pll0_clk,
|
||||
};
|
||||
|
||||
static struct clk usb1_clk = {
|
||||
.enable_reg = DIGCTRL_BASE_ADDR,
|
||||
.enable_shift = 16,
|
||||
.enable = _raw_clk_enable,
|
||||
.disable = _raw_clk_disable,
|
||||
.parent = &pll1_clk,
|
||||
};
|
||||
|
||||
#define _DEFINE_CLOCK(name, er, es, p) \
|
||||
static struct clk name = { \
|
||||
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
|
||||
.enable_shift = BP_CLKCTRL_##er##_##es, \
|
||||
.get_rate = name##_get_rate, \
|
||||
.set_rate = name##_set_rate, \
|
||||
.set_parent = name##_set_parent, \
|
||||
.enable = _raw_clk_enable, \
|
||||
.disable = _raw_clk_disable, \
|
||||
.parent = p, \
|
||||
}
|
||||
|
||||
_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
|
||||
_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
|
||||
_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
|
||||
|
||||
#define _REGISTER_CLOCK(d, n, c) \
|
||||
{ \
|
||||
.dev_id = d, \
|
||||
.con_id = n, \
|
||||
.clk = &c, \
|
||||
},
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* for amba bus driver */
|
||||
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
|
||||
/* for amba-pl011 driver */
|
||||
_REGISTER_CLOCK("duart", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
|
||||
_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
|
||||
_REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
|
||||
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
|
||||
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
|
||||
_REGISTER_CLOCK("pll2", NULL, pll2_clk)
|
||||
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
|
||||
_REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
|
||||
_REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
|
||||
_REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
|
||||
_REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
|
||||
_REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
|
||||
_REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
|
||||
_REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
|
||||
_REGISTER_CLOCK(NULL, "usb0", usb0_clk)
|
||||
_REGISTER_CLOCK(NULL, "usb1", usb1_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
|
||||
_REGISTER_CLOCK(NULL, "lradc", lradc_clk)
|
||||
_REGISTER_CLOCK(NULL, "spdif", spdif_clk)
|
||||
_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
|
||||
_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
|
||||
_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
|
||||
};
|
||||
|
||||
static int clk_misc_init(void)
|
||||
{
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
||||
/* Fix up parent per register setting */
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
|
||||
cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
|
||||
&ref_xtal_clk : &ref_cpu_clk;
|
||||
emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
|
||||
&ref_xtal_clk : &ref_emi_clk;
|
||||
ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
|
||||
&ref_xtal_clk : &ref_io0_clk;
|
||||
ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
|
||||
&ref_xtal_clk : &ref_io0_clk;
|
||||
ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
|
||||
&ref_xtal_clk : &ref_io1_clk;
|
||||
ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
|
||||
&ref_xtal_clk : &ref_io1_clk;
|
||||
lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
|
||||
&ref_xtal_clk : &ref_pix_clk;
|
||||
gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
|
||||
&ref_xtal_clk : &ref_gpmi_clk;
|
||||
saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
|
||||
&ref_xtal_clk : &pll0_clk;
|
||||
saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
|
||||
&ref_xtal_clk : &pll0_clk;
|
||||
|
||||
/* Use int div over frac when both are available */
|
||||
__raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
|
||||
__raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
|
||||
__raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
||||
reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
|
||||
reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
|
||||
reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
|
||||
reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
|
||||
reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
|
||||
reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
|
||||
reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
|
||||
|
||||
/* SAIF has to use frac div for functional operation */
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
|
||||
reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
|
||||
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
|
||||
reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
|
||||
|
||||
/*
|
||||
* Set safe hbus clock divider. A divider of 3 ensure that
|
||||
* the Vddd voltage required for the cpu clock is sufficiently
|
||||
* high for the hbus clock.
|
||||
*/
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
||||
reg &= BM_CLKCTRL_HBUS_DIV;
|
||||
reg |= 3 << BP_CLKCTRL_HBUS_DIV;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
||||
|
||||
ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
|
||||
|
||||
/* Gate off cpu clock in WFI for power saving */
|
||||
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
|
||||
|
||||
/*
|
||||
* Extra fec clock setting
|
||||
* The DENX M28 uses an external clock source
|
||||
* and the clock output must not be enabled
|
||||
*/
|
||||
if (!machine_is_m28evk()) {
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
|
||||
reg &= ~BM_CLKCTRL_ENET_SLEEP;
|
||||
reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
|
||||
}
|
||||
|
||||
/*
|
||||
* 480 MHz seems too high to be ssp clock source directly,
|
||||
* so set frac0 to get a 288 MHz ref_io0.
|
||||
*/
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
|
||||
reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
|
||||
reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __init mx28_clocks_init(void)
|
||||
{
|
||||
clk_misc_init();
|
||||
|
||||
/*
|
||||
* source ssp clock from ref_io0 than ref_xtal,
|
||||
* as ref_xtal only provides 24 MHz as maximum.
|
||||
*/
|
||||
clk_set_parent(&ssp0_clk, &ref_io0_clk);
|
||||
clk_set_parent(&ssp1_clk, &ref_io0_clk);
|
||||
clk_set_parent(&ssp2_clk, &ref_io1_clk);
|
||||
clk_set_parent(&ssp3_clk, &ref_io1_clk);
|
||||
|
||||
clk_prepare_enable(&cpu_clk);
|
||||
clk_prepare_enable(&hbus_clk);
|
||||
clk_prepare_enable(&xbus_clk);
|
||||
clk_prepare_enable(&emi_clk);
|
||||
clk_prepare_enable(&uart_clk);
|
||||
|
||||
clk_set_parent(&lcdif_clk, &ref_pix_clk);
|
||||
clk_set_parent(&saif0_clk, &pll0_clk);
|
||||
clk_set_parent(&saif1_clk, &pll0_clk);
|
||||
|
||||
/*
|
||||
* Set an initial clock rate for the saif internal logic to work
|
||||
* properly. This is important when working in EXTMASTER mode that
|
||||
* uses the other saif's BITCLK&LRCLK but it still needs a basic
|
||||
* clock which should be fast enough for the internal logic.
|
||||
*/
|
||||
clk_set_rate(&saif0_clk, 24000000);
|
||||
clk_set_rate(&saif1_clk, 24000000);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -1,211 +0,0 @@
|
|||
/*
|
||||
* Based on arch/arm/plat-omap/clock.c
|
||||
*
|
||||
* Copyright (C) 2004 - 2005 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
|
||||
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/* #define DEBUG */
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/semaphore.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/clock.h>
|
||||
|
||||
static LIST_HEAD(clocks);
|
||||
static DEFINE_MUTEX(clocks_mutex);
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Standard clock functions defined in include/linux/clk.h
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
static void __clk_disable(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return;
|
||||
WARN_ON(!clk->usecount);
|
||||
|
||||
if (!(--clk->usecount)) {
|
||||
if (clk->disable)
|
||||
clk->disable(clk);
|
||||
__clk_disable(clk->parent);
|
||||
}
|
||||
}
|
||||
|
||||
static int __clk_enable(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->usecount++ == 0) {
|
||||
__clk_enable(clk->parent);
|
||||
|
||||
if (clk->enable)
|
||||
clk->enable(clk);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The clk_enable/clk_disable could be called by drivers in atomic context,
|
||||
* so they should not really hold mutex. Instead, clk_prepare/clk_unprepare
|
||||
* can hold a mutex, as the pair will only be called in non-atomic context.
|
||||
* Before migrating to common clk framework, we can have __clk_enable and
|
||||
* __clk_disable called in clk_prepare/clk_unprepare with mutex held and
|
||||
* leave clk_enable/clk_disable as the dummy functions.
|
||||
*/
|
||||
int clk_prepare(struct clk *clk)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
ret = __clk_enable(clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_prepare);
|
||||
|
||||
void clk_unprepare(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
__clk_disable(clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_unprepare);
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
/* Retrieve the *current* clock rate. If the clock itself
|
||||
* does not provide a special calculation routine, ask
|
||||
* its parent and so on, until one is able to return
|
||||
* a valid clock rate
|
||||
*/
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return 0UL;
|
||||
|
||||
if (clk->get_rate)
|
||||
return clk->get_rate(clk);
|
||||
|
||||
return clk_get_rate(clk->parent);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
/* Round the requested clock rate to the nearest supported
|
||||
* rate that is less than or equal to the requested rate.
|
||||
* This is dependent on the clock's current parent.
|
||||
*/
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
|
||||
return 0;
|
||||
|
||||
return clk->round_rate(clk, rate);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
|
||||
/* Set the clock to the requested clock rate. The rate must
|
||||
* match a supported rate exactly based on what clk_round_rate returns
|
||||
*/
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
|
||||
return ret;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
ret = clk->set_rate(clk, rate);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
/* Set the clock's parent to another clock source */
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
struct clk *old;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk) || parent == NULL ||
|
||||
IS_ERR(parent) || clk->set_parent == NULL)
|
||||
return ret;
|
||||
|
||||
if (clk->usecount)
|
||||
clk_prepare_enable(parent);
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
ret = clk->set_parent(clk, parent);
|
||||
if (ret == 0) {
|
||||
old = clk->parent;
|
||||
clk->parent = parent;
|
||||
} else {
|
||||
old = parent;
|
||||
}
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
if (clk->usecount)
|
||||
clk_disable(old);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
/* Retrieve the clock's parent clock source */
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
struct clk *ret = NULL;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return ret;
|
||||
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_MXS_CLOCK_H__
|
||||
#define __MACH_MXS_CLOCK_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/list.h>
|
||||
|
||||
struct module;
|
||||
|
||||
struct clk {
|
||||
int id;
|
||||
/* Source clock this clk depends on */
|
||||
struct clk *parent;
|
||||
/* Reference count of clock enable/disable */
|
||||
__s8 usecount;
|
||||
/* Register bit position for clock's enable/disable control. */
|
||||
u8 enable_shift;
|
||||
/* Register address for clock's enable/disable control. */
|
||||
void __iomem *enable_reg;
|
||||
u32 flags;
|
||||
/* get the current clock rate (always a fresh value) */
|
||||
unsigned long (*get_rate) (struct clk *);
|
||||
/* Function ptr to set the clock to a new rate. The rate must match a
|
||||
supported rate returned from round_rate. Leave blank if clock is not
|
||||
programmable */
|
||||
int (*set_rate) (struct clk *, unsigned long);
|
||||
/* Function ptr to round the requested clock rate to the nearest
|
||||
supported rate that is less than or equal to the requested rate. */
|
||||
unsigned long (*round_rate) (struct clk *, unsigned long);
|
||||
/* Function ptr to enable the clock. Leave blank if clock can not
|
||||
be gated. */
|
||||
int (*enable) (struct clk *);
|
||||
/* Function ptr to disable the clock. Leave blank if clock can not
|
||||
be gated. */
|
||||
void (*disable) (struct clk *);
|
||||
/* Function ptr to set the parent clock of the clock. */
|
||||
int (*set_parent) (struct clk *, struct clk *);
|
||||
};
|
||||
|
||||
int clk_register(struct clk *clk);
|
||||
void clk_unregister(struct clk *clk);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __MACH_MXS_CLOCK_H__ */
|
|
@ -11,11 +11,9 @@
|
|||
#ifndef __MACH_MXS_COMMON_H__
|
||||
#define __MACH_MXS_COMMON_H__
|
||||
|
||||
struct clk;
|
||||
|
||||
extern const u32 *mxs_get_ocotp(void);
|
||||
extern int mxs_reset_block(void __iomem *);
|
||||
extern void mxs_timer_init(struct clk *, int);
|
||||
extern void mxs_timer_init(int);
|
||||
extern void mxs_restart(char, const char *);
|
||||
extern int mxs_saif_clkmux_select(unsigned int clkmux);
|
||||
|
||||
|
@ -31,6 +29,4 @@ extern void mx28_init_irq(void);
|
|||
|
||||
extern void icoll_init_irq(void);
|
||||
|
||||
extern int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask);
|
||||
|
||||
#endif /* __MACH_MXS_COMMON_H__ */
|
||||
|
|
|
@ -226,7 +226,7 @@ static void __init mx28evk_fec_reset(void)
|
|||
struct clk *clk;
|
||||
|
||||
/* Enable fec phy clock */
|
||||
clk = clk_get_sys("pll2", NULL);
|
||||
clk = clk_get_sys("enet_out", NULL);
|
||||
if (!IS_ERR(clk))
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
|
|
|
@ -1,331 +0,0 @@
|
|||
/*
|
||||
* Freescale CLKCTRL Register Definitions
|
||||
*
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* This file is created by xml file. Don't Edit it.
|
||||
*
|
||||
* Xml Revision: 1.48
|
||||
* Template revision: 26195
|
||||
*/
|
||||
|
||||
#ifndef __REGS_CLKCTRL_MX23_H__
|
||||
#define __REGS_CLKCTRL_MX23_H__
|
||||
|
||||
|
||||
#define HW_CLKCTRL_PLLCTRL0 (0x00000000)
|
||||
#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
|
||||
#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
|
||||
#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
|
||||
|
||||
#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
|
||||
#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
|
||||
#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
|
||||
(((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
|
||||
#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
|
||||
#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
|
||||
#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
|
||||
#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
|
||||
(((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
|
||||
#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
|
||||
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
|
||||
#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
|
||||
|
||||
#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
|
||||
|
||||
#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
|
||||
#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
|
||||
#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
|
||||
#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
|
||||
#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
|
||||
|
||||
#define HW_CLKCTRL_CPU (0x00000020)
|
||||
#define HW_CLKCTRL_CPU_SET (0x00000024)
|
||||
#define HW_CLKCTRL_CPU_CLR (0x00000028)
|
||||
#define HW_CLKCTRL_CPU_TOG (0x0000002c)
|
||||
|
||||
#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
|
||||
#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
|
||||
#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
|
||||
#define BP_CLKCTRL_CPU_DIV_XTAL 16
|
||||
#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
|
||||
#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
|
||||
#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_CPU_DIV_CPU 0
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
|
||||
#define BF_CLKCTRL_CPU_DIV_CPU(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
|
||||
|
||||
#define HW_CLKCTRL_HBUS (0x00000030)
|
||||
#define HW_CLKCTRL_HBUS_SET (0x00000034)
|
||||
#define HW_CLKCTRL_HBUS_CLR (0x00000038)
|
||||
#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
|
||||
|
||||
#define BM_CLKCTRL_HBUS_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
|
||||
#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
|
||||
#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
|
||||
#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
|
||||
#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
|
||||
#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
|
||||
#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
|
||||
#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
|
||||
#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
|
||||
#define BP_CLKCTRL_HBUS_SLOW_DIV 16
|
||||
#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
|
||||
#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
|
||||
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
|
||||
#define BP_CLKCTRL_HBUS_DIV 0
|
||||
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
|
||||
#define BF_CLKCTRL_HBUS_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
|
||||
|
||||
#define HW_CLKCTRL_XBUS (0x00000040)
|
||||
|
||||
#define BM_CLKCTRL_XBUS_BUSY 0x80000000
|
||||
#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_XBUS_DIV 0
|
||||
#define BM_CLKCTRL_XBUS_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_XBUS_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_XBUS_DIV)
|
||||
|
||||
#define HW_CLKCTRL_XTAL (0x00000050)
|
||||
#define HW_CLKCTRL_XTAL_SET (0x00000054)
|
||||
#define HW_CLKCTRL_XTAL_CLR (0x00000058)
|
||||
#define HW_CLKCTRL_XTAL_TOG (0x0000005c)
|
||||
|
||||
#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
|
||||
#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
|
||||
#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
|
||||
#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
|
||||
#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
|
||||
#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
|
||||
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
|
||||
#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
|
||||
#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
|
||||
#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
|
||||
#define BP_CLKCTRL_XTAL_DIV_UART 0
|
||||
#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
|
||||
#define BF_CLKCTRL_XTAL_DIV_UART(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
|
||||
|
||||
#define HW_CLKCTRL_PIX (0x00000060)
|
||||
|
||||
#define BP_CLKCTRL_PIX_CLKGATE 31
|
||||
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_PIX_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
|
||||
#define BP_CLKCTRL_PIX_DIV 0
|
||||
#define BM_CLKCTRL_PIX_DIV 0x00000FFF
|
||||
#define BF_CLKCTRL_PIX_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_PIX_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SSP (0x00000070)
|
||||
|
||||
#define BP_CLKCTRL_SSP_CLKGATE 31
|
||||
#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SSP_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
|
||||
#define BP_CLKCTRL_SSP_DIV 0
|
||||
#define BM_CLKCTRL_SSP_DIV 0x000001FF
|
||||
#define BF_CLKCTRL_SSP_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SSP_DIV)
|
||||
|
||||
#define HW_CLKCTRL_GPMI (0x00000080)
|
||||
|
||||
#define BP_CLKCTRL_GPMI_CLKGATE 31
|
||||
#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_GPMI_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_GPMI_DIV 0
|
||||
#define BM_CLKCTRL_GPMI_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_GPMI_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_GPMI_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SPDIF (0x00000090)
|
||||
|
||||
#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
|
||||
|
||||
#define HW_CLKCTRL_EMI (0x000000a0)
|
||||
|
||||
#define BP_CLKCTRL_EMI_CLKGATE 31
|
||||
#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
|
||||
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
|
||||
#define BP_CLKCTRL_EMI_DIV_XTAL 8
|
||||
#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
|
||||
#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
|
||||
#define BP_CLKCTRL_EMI_DIV_EMI 0
|
||||
#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
|
||||
#define BF_CLKCTRL_EMI_DIV_EMI(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
|
||||
|
||||
#define HW_CLKCTRL_IR (0x000000b0)
|
||||
|
||||
#define BM_CLKCTRL_IR_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
|
||||
#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
|
||||
#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
|
||||
#define BP_CLKCTRL_IR_IROV_DIV 16
|
||||
#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
|
||||
#define BF_CLKCTRL_IR_IROV_DIV(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
|
||||
#define BP_CLKCTRL_IR_IR_DIV 0
|
||||
#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_IR_IR_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SAIF (0x000000c0)
|
||||
|
||||
#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SAIF_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
|
||||
#define BP_CLKCTRL_SAIF_DIV 0
|
||||
#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
|
||||
#define BF_CLKCTRL_SAIF_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SAIF_DIV)
|
||||
|
||||
#define HW_CLKCTRL_TV (0x000000d0)
|
||||
|
||||
#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
|
||||
#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
|
||||
|
||||
#define HW_CLKCTRL_ETM (0x000000e0)
|
||||
|
||||
#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_ETM_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
|
||||
#define BP_CLKCTRL_ETM_DIV 0
|
||||
#define BM_CLKCTRL_ETM_DIV 0x0000003F
|
||||
#define BF_CLKCTRL_ETM_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_ETM_DIV)
|
||||
|
||||
#define HW_CLKCTRL_FRAC (0x000000f0)
|
||||
#define HW_CLKCTRL_FRAC_SET (0x000000f4)
|
||||
#define HW_CLKCTRL_FRAC_CLR (0x000000f8)
|
||||
#define HW_CLKCTRL_FRAC_TOG (0x000000fc)
|
||||
|
||||
#define BP_CLKCTRL_FRAC_CLKGATEIO 31
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
|
||||
#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
|
||||
#define BP_CLKCTRL_FRAC_IOFRAC 24
|
||||
#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
|
||||
#define BF_CLKCTRL_FRAC_IOFRAC(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
|
||||
#define BP_CLKCTRL_FRAC_CLKGATEPIX 23
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
|
||||
#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
|
||||
#define BP_CLKCTRL_FRAC_PIXFRAC 16
|
||||
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
|
||||
#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
|
||||
#define BP_CLKCTRL_FRAC_CLKGATEEMI 15
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
|
||||
#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
|
||||
#define BP_CLKCTRL_FRAC_EMIFRAC 8
|
||||
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
|
||||
#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
|
||||
#define BP_CLKCTRL_FRAC_CLKGATECPU 7
|
||||
#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
|
||||
#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
|
||||
#define BP_CLKCTRL_FRAC_CPUFRAC 0
|
||||
#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
|
||||
#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
|
||||
|
||||
#define HW_CLKCTRL_FRAC1 (0x00000100)
|
||||
#define HW_CLKCTRL_FRAC1_SET (0x00000104)
|
||||
#define HW_CLKCTRL_FRAC1_CLR (0x00000108)
|
||||
#define HW_CLKCTRL_FRAC1_TOG (0x0000010c)
|
||||
|
||||
#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
|
||||
#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
|
||||
|
||||
#define HW_CLKCTRL_CLKSEQ (0x00000110)
|
||||
#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
|
||||
#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
|
||||
#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
|
||||
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
|
||||
|
||||
#define HW_CLKCTRL_RESET (0x00000120)
|
||||
|
||||
#define BM_CLKCTRL_RESET_CHIP 0x00000002
|
||||
#define BM_CLKCTRL_RESET_DIG 0x00000001
|
||||
|
||||
#define HW_CLKCTRL_STATUS (0x00000130)
|
||||
|
||||
#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
|
||||
#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
|
||||
#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
|
||||
(((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
|
||||
|
||||
#define HW_CLKCTRL_VERSION (0x00000140)
|
||||
|
||||
#define BP_CLKCTRL_VERSION_MAJOR 24
|
||||
#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
|
||||
#define BF_CLKCTRL_VERSION_MAJOR(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
|
||||
#define BP_CLKCTRL_VERSION_MINOR 16
|
||||
#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
|
||||
#define BF_CLKCTRL_VERSION_MINOR(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
|
||||
#define BP_CLKCTRL_VERSION_STEP 0
|
||||
#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
|
||||
#define BF_CLKCTRL_VERSION_STEP(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_VERSION_STEP)
|
||||
|
||||
#endif /* __REGS_CLKCTRL_MX23_H__ */
|
|
@ -1,486 +0,0 @@
|
|||
/*
|
||||
* Freescale CLKCTRL Register Definitions
|
||||
*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* This file is created by xml file. Don't Edit it.
|
||||
*
|
||||
* Xml Revision: 1.48
|
||||
* Template revision: 26195
|
||||
*/
|
||||
|
||||
#ifndef __REGS_CLKCTRL_MX28_H__
|
||||
#define __REGS_CLKCTRL_MX28_H__
|
||||
|
||||
#define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
|
||||
#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
|
||||
#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
|
||||
#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
|
||||
|
||||
#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
|
||||
#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
|
||||
#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
|
||||
(((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
|
||||
#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
|
||||
#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
|
||||
#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
|
||||
#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
|
||||
#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
|
||||
#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
|
||||
(((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
|
||||
#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
|
||||
#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
|
||||
#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
|
||||
#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
|
||||
#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
|
||||
|
||||
#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
|
||||
|
||||
#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
|
||||
#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
|
||||
#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
|
||||
#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
|
||||
#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
|
||||
|
||||
#define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
|
||||
#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
|
||||
#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
|
||||
#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
|
||||
|
||||
#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
|
||||
#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
|
||||
#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
|
||||
#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
|
||||
(((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
|
||||
#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
|
||||
#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
|
||||
#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
|
||||
#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
|
||||
#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
|
||||
#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
|
||||
#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
|
||||
#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
|
||||
#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
|
||||
(((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
|
||||
#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
|
||||
#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
|
||||
#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
|
||||
#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
|
||||
#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
|
||||
#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
|
||||
|
||||
#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
|
||||
|
||||
#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
|
||||
#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
|
||||
#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
|
||||
#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
|
||||
#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
|
||||
|
||||
#define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
|
||||
#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
|
||||
#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
|
||||
#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
|
||||
|
||||
#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
|
||||
#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
|
||||
#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
|
||||
#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
|
||||
(((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
|
||||
#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
|
||||
#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
|
||||
#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
|
||||
#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
|
||||
#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
|
||||
|
||||
#define HW_CLKCTRL_CPU (0x00000050)
|
||||
#define HW_CLKCTRL_CPU_SET (0x00000054)
|
||||
#define HW_CLKCTRL_CPU_CLR (0x00000058)
|
||||
#define HW_CLKCTRL_CPU_TOG (0x0000005c)
|
||||
|
||||
#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
|
||||
#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
|
||||
#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
|
||||
#define BP_CLKCTRL_CPU_DIV_XTAL 16
|
||||
#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
|
||||
#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
|
||||
#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_CPU_DIV_CPU 0
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
|
||||
#define BF_CLKCTRL_CPU_DIV_CPU(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
|
||||
|
||||
#define HW_CLKCTRL_HBUS (0x00000060)
|
||||
#define HW_CLKCTRL_HBUS_SET (0x00000064)
|
||||
#define HW_CLKCTRL_HBUS_CLR (0x00000068)
|
||||
#define HW_CLKCTRL_HBUS_TOG (0x0000006c)
|
||||
|
||||
#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
|
||||
#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
|
||||
#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
|
||||
#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
|
||||
#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
|
||||
#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
|
||||
#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
|
||||
#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
|
||||
#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
|
||||
#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
|
||||
#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
|
||||
#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
|
||||
#define BP_CLKCTRL_HBUS_SLOW_DIV 16
|
||||
#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
|
||||
#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
|
||||
#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
|
||||
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
|
||||
#define BP_CLKCTRL_HBUS_DIV 0
|
||||
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
|
||||
#define BF_CLKCTRL_HBUS_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_HBUS_DIV)
|
||||
|
||||
#define HW_CLKCTRL_XBUS (0x00000070)
|
||||
|
||||
#define BM_CLKCTRL_XBUS_BUSY 0x80000000
|
||||
#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
|
||||
#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_XBUS_DIV 0
|
||||
#define BM_CLKCTRL_XBUS_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_XBUS_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_XBUS_DIV)
|
||||
|
||||
#define HW_CLKCTRL_XTAL (0x00000080)
|
||||
#define HW_CLKCTRL_XTAL_SET (0x00000084)
|
||||
#define HW_CLKCTRL_XTAL_CLR (0x00000088)
|
||||
#define HW_CLKCTRL_XTAL_TOG (0x0000008c)
|
||||
|
||||
#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
|
||||
#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
|
||||
#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
|
||||
#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
|
||||
#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
|
||||
#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
|
||||
#define BP_CLKCTRL_XTAL_DIV_UART 0
|
||||
#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
|
||||
#define BF_CLKCTRL_XTAL_DIV_UART(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
|
||||
|
||||
#define HW_CLKCTRL_SSP0 (0x00000090)
|
||||
|
||||
#define BP_CLKCTRL_SSP0_CLKGATE 31
|
||||
#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SSP0_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
|
||||
#define BP_CLKCTRL_SSP0_DIV 0
|
||||
#define BM_CLKCTRL_SSP0_DIV 0x000001FF
|
||||
#define BF_CLKCTRL_SSP0_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SSP0_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SSP1 (0x000000a0)
|
||||
|
||||
#define BP_CLKCTRL_SSP1_CLKGATE 31
|
||||
#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SSP1_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
|
||||
#define BP_CLKCTRL_SSP1_DIV 0
|
||||
#define BM_CLKCTRL_SSP1_DIV 0x000001FF
|
||||
#define BF_CLKCTRL_SSP1_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SSP1_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SSP2 (0x000000b0)
|
||||
|
||||
#define BP_CLKCTRL_SSP2_CLKGATE 31
|
||||
#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SSP2_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
|
||||
#define BP_CLKCTRL_SSP2_DIV 0
|
||||
#define BM_CLKCTRL_SSP2_DIV 0x000001FF
|
||||
#define BF_CLKCTRL_SSP2_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SSP2_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SSP3 (0x000000c0)
|
||||
|
||||
#define BP_CLKCTRL_SSP3_CLKGATE 31
|
||||
#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SSP3_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
|
||||
#define BP_CLKCTRL_SSP3_DIV 0
|
||||
#define BM_CLKCTRL_SSP3_DIV 0x000001FF
|
||||
#define BF_CLKCTRL_SSP3_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SSP3_DIV)
|
||||
|
||||
#define HW_CLKCTRL_GPMI (0x000000d0)
|
||||
|
||||
#define BP_CLKCTRL_GPMI_CLKGATE 31
|
||||
#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_GPMI_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
|
||||
#define BP_CLKCTRL_GPMI_DIV 0
|
||||
#define BM_CLKCTRL_GPMI_DIV 0x000003FF
|
||||
#define BF_CLKCTRL_GPMI_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_GPMI_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SPDIF (0x000000e0)
|
||||
|
||||
#define BP_CLKCTRL_SPDIF_CLKGATE 31
|
||||
#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
|
||||
|
||||
#define HW_CLKCTRL_EMI (0x000000f0)
|
||||
|
||||
#define BP_CLKCTRL_EMI_CLKGATE 31
|
||||
#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
|
||||
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
|
||||
#define BP_CLKCTRL_EMI_DIV_XTAL 8
|
||||
#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
|
||||
#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
|
||||
#define BP_CLKCTRL_EMI_DIV_EMI 0
|
||||
#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
|
||||
#define BF_CLKCTRL_EMI_DIV_EMI(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
|
||||
|
||||
#define HW_CLKCTRL_SAIF0 (0x00000100)
|
||||
|
||||
#define BP_CLKCTRL_SAIF0_CLKGATE 31
|
||||
#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
|
||||
#define BP_CLKCTRL_SAIF0_DIV 0
|
||||
#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
|
||||
#define BF_CLKCTRL_SAIF0_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
|
||||
|
||||
#define HW_CLKCTRL_SAIF1 (0x00000110)
|
||||
|
||||
#define BP_CLKCTRL_SAIF1_CLKGATE 31
|
||||
#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
|
||||
#define BP_CLKCTRL_SAIF1_DIV 0
|
||||
#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
|
||||
#define BF_CLKCTRL_SAIF1_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
|
||||
|
||||
#define HW_CLKCTRL_DIS_LCDIF (0x00000120)
|
||||
|
||||
#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
|
||||
#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
|
||||
#define BP_CLKCTRL_DIS_LCDIF_DIV 0
|
||||
#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
|
||||
#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
|
||||
|
||||
#define HW_CLKCTRL_ETM (0x00000130)
|
||||
|
||||
#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
|
||||
#define BM_CLKCTRL_ETM_BUSY 0x20000000
|
||||
#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
|
||||
#define BP_CLKCTRL_ETM_DIV 0
|
||||
#define BM_CLKCTRL_ETM_DIV 0x0000007F
|
||||
#define BF_CLKCTRL_ETM_DIV(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_ETM_DIV)
|
||||
|
||||
#define HW_CLKCTRL_ENET (0x00000140)
|
||||
|
||||
#define BM_CLKCTRL_ENET_SLEEP 0x80000000
|
||||
#define BP_CLKCTRL_ENET_DISABLE 30
|
||||
#define BM_CLKCTRL_ENET_DISABLE 0x40000000
|
||||
#define BM_CLKCTRL_ENET_STATUS 0x20000000
|
||||
#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
|
||||
#define BP_CLKCTRL_ENET_DIV_TIME 21
|
||||
#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
|
||||
#define BF_CLKCTRL_ENET_DIV_TIME(v) \
|
||||
(((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
|
||||
#define BM_CLKCTRL_ENET_BUSY 0x08000000
|
||||
#define BP_CLKCTRL_ENET_DIV 21
|
||||
#define BM_CLKCTRL_ENET_DIV 0x07E00000
|
||||
#define BF_CLKCTRL_ENET_DIV(v) \
|
||||
(((v) << 21) & BM_CLKCTRL_ENET_DIV)
|
||||
#define BP_CLKCTRL_ENET_TIME_SEL 19
|
||||
#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
|
||||
#define BF_CLKCTRL_ENET_TIME_SEL(v) \
|
||||
(((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
|
||||
#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
|
||||
#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
|
||||
#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
|
||||
#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
|
||||
#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
|
||||
#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
|
||||
#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
|
||||
|
||||
#define HW_CLKCTRL_HSADC (0x00000150)
|
||||
|
||||
#define BM_CLKCTRL_HSADC_RESETB 0x40000000
|
||||
#define BP_CLKCTRL_HSADC_FREQDIV 28
|
||||
#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
|
||||
#define BF_CLKCTRL_HSADC_FREQDIV(v) \
|
||||
(((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
|
||||
|
||||
#define HW_CLKCTRL_FLEXCAN (0x00000160)
|
||||
|
||||
#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
|
||||
#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
|
||||
#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
|
||||
#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
|
||||
#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
|
||||
#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
|
||||
|
||||
#define HW_CLKCTRL_FRAC0 (0x000001b0)
|
||||
#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
|
||||
#define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
|
||||
#define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
|
||||
|
||||
#define BP_CLKCTRL_FRAC0_CLKGATEIO0 31
|
||||
#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
|
||||
#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
|
||||
#define BP_CLKCTRL_FRAC0_IO0FRAC 24
|
||||
#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
|
||||
#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
|
||||
#define BP_CLKCTRL_FRAC0_CLKGATEIO1 23
|
||||
#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
|
||||
#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
|
||||
#define BP_CLKCTRL_FRAC0_IO1FRAC 16
|
||||
#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
|
||||
#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
|
||||
#define BP_CLKCTRL_FRAC0_CLKGATEEMI 15
|
||||
#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
|
||||
#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
|
||||
#define BP_CLKCTRL_FRAC0_EMIFRAC 8
|
||||
#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
|
||||
#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
|
||||
#define BP_CLKCTRL_FRAC0_CLKGATECPU 7
|
||||
#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
|
||||
#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
|
||||
#define BP_CLKCTRL_FRAC0_CPUFRAC 0
|
||||
#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
|
||||
#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
|
||||
|
||||
#define HW_CLKCTRL_FRAC1 (0x000001c0)
|
||||
#define HW_CLKCTRL_FRAC1_SET (0x000001c4)
|
||||
#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
|
||||
#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
|
||||
|
||||
#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
|
||||
#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
|
||||
#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
|
||||
#define BP_CLKCTRL_FRAC1_GPMIFRAC 16
|
||||
#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
|
||||
#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
|
||||
#define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15
|
||||
#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
|
||||
#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
|
||||
#define BP_CLKCTRL_FRAC1_HSADCFRAC 8
|
||||
#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
|
||||
#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
|
||||
(((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
|
||||
#define BP_CLKCTRL_FRAC1_CLKGATEPIX 7
|
||||
#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
|
||||
#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
|
||||
#define BP_CLKCTRL_FRAC1_PIXFRAC 0
|
||||
#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
|
||||
#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
|
||||
|
||||
#define HW_CLKCTRL_CLKSEQ (0x000001d0)
|
||||
#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
|
||||
#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
|
||||
#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
|
||||
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
|
||||
#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
|
||||
#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
|
||||
|
||||
#define HW_CLKCTRL_RESET (0x000001e0)
|
||||
|
||||
#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
|
||||
#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
|
||||
#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
|
||||
#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
|
||||
#define BM_CLKCTRL_RESET_CHIP 0x00000002
|
||||
#define BM_CLKCTRL_RESET_DIG 0x00000001
|
||||
|
||||
#define HW_CLKCTRL_STATUS (0x000001f0)
|
||||
|
||||
#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
|
||||
#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
|
||||
#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
|
||||
(((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
|
||||
|
||||
#define HW_CLKCTRL_VERSION (0x00000200)
|
||||
|
||||
#define BP_CLKCTRL_VERSION_MAJOR 24
|
||||
#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
|
||||
#define BF_CLKCTRL_VERSION_MAJOR(v) \
|
||||
(((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
|
||||
#define BP_CLKCTRL_VERSION_MINOR 16
|
||||
#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
|
||||
#define BF_CLKCTRL_VERSION_MINOR(v) \
|
||||
(((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
|
||||
#define BP_CLKCTRL_VERSION_STEP 0
|
||||
#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
|
||||
#define BF_CLKCTRL_VERSION_STEP(v) \
|
||||
(((v) << 0) & BM_CLKCTRL_VERSION_STEP)
|
||||
|
||||
#endif /* __REGS_CLKCTRL_MX28_H__ */
|
|
@ -37,8 +37,6 @@
|
|||
#define MXS_MODULE_CLKGATE (1 << 30)
|
||||
#define MXS_MODULE_SFTRST (1 << 31)
|
||||
|
||||
#define CLKCTRL_TIMEOUT 10 /* 10 ms */
|
||||
|
||||
static void __iomem *mxs_clkctrl_reset_addr;
|
||||
|
||||
/*
|
||||
|
@ -139,17 +137,3 @@ error:
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
EXPORT_SYMBOL(mxs_reset_block);
|
||||
|
||||
int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask)
|
||||
{
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(CLKCTRL_TIMEOUT);
|
||||
while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR)
|
||||
+ reg_offset) & mask) {
|
||||
if (time_after(jiffies, timeout)) {
|
||||
pr_err("Timeout at CLKCTRL + 0x%x\n", reg_offset);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clockchips.h>
|
||||
|
@ -243,8 +244,16 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void __init mxs_timer_init(struct clk *timer_clk, int irq)
|
||||
void __init mxs_timer_init(int irq)
|
||||
{
|
||||
struct clk *timer_clk;
|
||||
|
||||
timer_clk = clk_get_sys("timrot", NULL);
|
||||
if (IS_ERR(timer_clk)) {
|
||||
pr_err("%s: failed to get clk\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
clk_prepare_enable(timer_clk);
|
||||
|
||||
/*
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
*
|
||||
* bit 23 - Input/Output (PXA2xx specific)
|
||||
* bit 24 - Wakeup Enable(PXA2xx specific)
|
||||
* bit 25 - Keep Output (PXA2xx specific)
|
||||
*/
|
||||
|
||||
#define MFP_DIR_IN (0x0 << 23)
|
||||
|
@ -25,6 +26,12 @@
|
|||
#define MFP_DIR(x) (((x) >> 23) & 0x1)
|
||||
|
||||
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
|
||||
|
||||
/*
|
||||
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
|
||||
* retain their last output level (low or high).
|
||||
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
|
||||
*/
|
||||
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
|
||||
|
||||
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
|
||||
|
|
|
@ -33,6 +33,8 @@
|
|||
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
|
||||
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
|
||||
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
|
||||
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
|
||||
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
|
||||
|
||||
#define PWER_WE35 (1 << 24)
|
||||
|
||||
|
@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
|
|||
#ifdef CONFIG_PM
|
||||
static unsigned long saved_gafr[2][4];
|
||||
static unsigned long saved_gpdr[4];
|
||||
static unsigned long saved_gplr[4];
|
||||
static unsigned long saved_pgsr[4];
|
||||
|
||||
static int pxa2xx_mfp_suspend(void)
|
||||
|
@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
|
|||
}
|
||||
|
||||
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
|
||||
|
||||
saved_gafr[0][i] = GAFR_L(i);
|
||||
saved_gafr[1][i] = GAFR_U(i);
|
||||
saved_gpdr[i] = GPDR(i * 32);
|
||||
saved_gplr[i] = GPLR(i * 32);
|
||||
saved_pgsr[i] = PGSR(i);
|
||||
|
||||
GPDR(i * 32) = gpdr_lpm[i];
|
||||
GPSR(i * 32) = PGSR(i);
|
||||
GPCR(i * 32) = ~PGSR(i);
|
||||
}
|
||||
|
||||
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
|
||||
for (i = 0; i < pxa_last_gpio; i++) {
|
||||
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
|
||||
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
|
||||
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
|
||||
GPDR(i) |= GPIO_bit(i);
|
||||
else
|
||||
GPDR(i) &= ~GPIO_bit(i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
|
|||
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
|
||||
GAFR_L(i) = saved_gafr[0][i];
|
||||
GAFR_U(i) = saved_gafr[1][i];
|
||||
GPSR(i * 32) = saved_gplr[i];
|
||||
GPCR(i * 32) = ~saved_gplr[i];
|
||||
GPDR(i * 32) = saved_gpdr[i];
|
||||
PGSR(i) = saved_pgsr[i];
|
||||
}
|
||||
|
|
|
@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
|
|||
pxa_register_device(&pxa27x_device_i2c_power, info);
|
||||
}
|
||||
|
||||
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
|
||||
.gpio_set_wake = gpio_set_wake,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&pxa_device_gpio,
|
||||
&pxa27x_device_udc,
|
||||
&pxa_device_pmu,
|
||||
&pxa_device_i2s,
|
||||
|
@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
|
|||
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
|
||||
register_syscore_ops(&pxa2xx_clock_syscore_ops);
|
||||
|
||||
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
|
||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
|
|
|
@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
|
|||
help
|
||||
Compile in platform device definition for Samsung TouchScreen.
|
||||
|
||||
# cpu-specific sections
|
||||
|
||||
if CPU_S3C2410
|
||||
|
||||
config S3C2410_DMA
|
||||
bool
|
||||
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
|
||||
|
@ -127,6 +123,10 @@ config S3C2410_PM
|
|||
help
|
||||
Power Management code common to S3C2410 and better
|
||||
|
||||
# cpu-specific sections
|
||||
|
||||
if CPU_S3C2410
|
||||
|
||||
config S3C24XX_SIMTEC_NOR
|
||||
bool
|
||||
help
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
|
|||
/* MoviNAND */
|
||||
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
};
|
||||
|
||||
|
|
|
@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
|
|||
}
|
||||
|
||||
static struct resource sa1100_rtc_resources[] = {
|
||||
DEFINE_RES_MEM(0x90010000, 0x9001003f),
|
||||
DEFINE_RES_MEM(0x90010000, 0x40),
|
||||
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
|
||||
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
|
||||
};
|
||||
|
|
|
@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
|
|||
|
||||
for (i = 0; i < U300_VIC_IRQS_END; i++)
|
||||
set_bit(i, (unsigned long *) &mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
|
||||
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
|
||||
mask[0], mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
|
||||
mask[1], mask[1]);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.min_uV = 2500000,
|
||||
.max_uV = 2500000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
REGULATOR_CHANGE_VOLTAGE,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
|
|
@ -12,101 +12,101 @@
|
|||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#define IRQ_U300_INTCON0_START 0
|
||||
#define IRQ_U300_INTCON1_START 32
|
||||
#define IRQ_U300_INTCON0_START 1
|
||||
#define IRQ_U300_INTCON1_START 33
|
||||
/* These are on INTCON0 - 30 lines */
|
||||
#define IRQ_U300_IRQ0_EXT 0
|
||||
#define IRQ_U300_IRQ1_EXT 1
|
||||
#define IRQ_U300_DMA 2
|
||||
#define IRQ_U300_VIDEO_ENC_0 3
|
||||
#define IRQ_U300_VIDEO_ENC_1 4
|
||||
#define IRQ_U300_AAIF_RX 5
|
||||
#define IRQ_U300_AAIF_TX 6
|
||||
#define IRQ_U300_AAIF_VGPIO 7
|
||||
#define IRQ_U300_AAIF_WAKEUP 8
|
||||
#define IRQ_U300_PCM_I2S0_FRAME 9
|
||||
#define IRQ_U300_PCM_I2S0_FIFO 10
|
||||
#define IRQ_U300_PCM_I2S1_FRAME 11
|
||||
#define IRQ_U300_PCM_I2S1_FIFO 12
|
||||
#define IRQ_U300_XGAM_GAMCON 13
|
||||
#define IRQ_U300_XGAM_CDI 14
|
||||
#define IRQ_U300_XGAM_CDICON 15
|
||||
#define IRQ_U300_IRQ0_EXT 1
|
||||
#define IRQ_U300_IRQ1_EXT 2
|
||||
#define IRQ_U300_DMA 3
|
||||
#define IRQ_U300_VIDEO_ENC_0 4
|
||||
#define IRQ_U300_VIDEO_ENC_1 5
|
||||
#define IRQ_U300_AAIF_RX 6
|
||||
#define IRQ_U300_AAIF_TX 7
|
||||
#define IRQ_U300_AAIF_VGPIO 8
|
||||
#define IRQ_U300_AAIF_WAKEUP 9
|
||||
#define IRQ_U300_PCM_I2S0_FRAME 10
|
||||
#define IRQ_U300_PCM_I2S0_FIFO 11
|
||||
#define IRQ_U300_PCM_I2S1_FRAME 12
|
||||
#define IRQ_U300_PCM_I2S1_FIFO 13
|
||||
#define IRQ_U300_XGAM_GAMCON 14
|
||||
#define IRQ_U300_XGAM_CDI 15
|
||||
#define IRQ_U300_XGAM_CDICON 16
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
/* MMIACC not used on the DB3210 or DB3350 chips */
|
||||
#define IRQ_U300_XGAM_MMIACC 16
|
||||
#define IRQ_U300_XGAM_MMIACC 17
|
||||
#endif
|
||||
#define IRQ_U300_XGAM_PDI 17
|
||||
#define IRQ_U300_XGAM_PDICON 18
|
||||
#define IRQ_U300_XGAM_GAMEACC 19
|
||||
#define IRQ_U300_XGAM_MCIDCT 20
|
||||
#define IRQ_U300_APEX 21
|
||||
#define IRQ_U300_UART0 22
|
||||
#define IRQ_U300_SPI 23
|
||||
#define IRQ_U300_TIMER_APP_OS 24
|
||||
#define IRQ_U300_TIMER_APP_DD 25
|
||||
#define IRQ_U300_TIMER_APP_GP1 26
|
||||
#define IRQ_U300_TIMER_APP_GP2 27
|
||||
#define IRQ_U300_TIMER_OS 28
|
||||
#define IRQ_U300_TIMER_MS 29
|
||||
#define IRQ_U300_KEYPAD_KEYBF 30
|
||||
#define IRQ_U300_KEYPAD_KEYBR 31
|
||||
#define IRQ_U300_XGAM_PDI 18
|
||||
#define IRQ_U300_XGAM_PDICON 19
|
||||
#define IRQ_U300_XGAM_GAMEACC 20
|
||||
#define IRQ_U300_XGAM_MCIDCT 21
|
||||
#define IRQ_U300_APEX 22
|
||||
#define IRQ_U300_UART0 23
|
||||
#define IRQ_U300_SPI 24
|
||||
#define IRQ_U300_TIMER_APP_OS 25
|
||||
#define IRQ_U300_TIMER_APP_DD 26
|
||||
#define IRQ_U300_TIMER_APP_GP1 27
|
||||
#define IRQ_U300_TIMER_APP_GP2 28
|
||||
#define IRQ_U300_TIMER_OS 29
|
||||
#define IRQ_U300_TIMER_MS 30
|
||||
#define IRQ_U300_KEYPAD_KEYBF 31
|
||||
#define IRQ_U300_KEYPAD_KEYBR 32
|
||||
/* These are on INTCON1 - 32 lines */
|
||||
#define IRQ_U300_GPIO_PORT0 32
|
||||
#define IRQ_U300_GPIO_PORT1 33
|
||||
#define IRQ_U300_GPIO_PORT2 34
|
||||
#define IRQ_U300_GPIO_PORT0 33
|
||||
#define IRQ_U300_GPIO_PORT1 34
|
||||
#define IRQ_U300_GPIO_PORT2 35
|
||||
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
|
||||
defined(CONFIG_MACH_U300_BS335)
|
||||
/* These are for DB3150, DB3200 and DB3350 */
|
||||
#define IRQ_U300_WDOG 35
|
||||
#define IRQ_U300_EVHIST 36
|
||||
#define IRQ_U300_MSPRO 37
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 38
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 39
|
||||
#define IRQ_U300_I2C0 40
|
||||
#define IRQ_U300_I2C1 41
|
||||
#define IRQ_U300_RTC 42
|
||||
#define IRQ_U300_NFIF 43
|
||||
#define IRQ_U300_NFIF2 44
|
||||
#define IRQ_U300_WDOG 36
|
||||
#define IRQ_U300_EVHIST 37
|
||||
#define IRQ_U300_MSPRO 38
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 39
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 40
|
||||
#define IRQ_U300_I2C0 41
|
||||
#define IRQ_U300_I2C1 42
|
||||
#define IRQ_U300_RTC 43
|
||||
#define IRQ_U300_NFIF 44
|
||||
#define IRQ_U300_NFIF2 45
|
||||
#endif
|
||||
|
||||
/* DB3150 and DB3200 have only 45 IRQs */
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
#define U300_VIC_IRQS_END 45
|
||||
#define U300_VIC_IRQS_END 46
|
||||
#endif
|
||||
|
||||
/* The DB3350-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define IRQ_U300_ISP_F0 45
|
||||
#define IRQ_U300_ISP_F1 46
|
||||
#define IRQ_U300_ISP_F2 47
|
||||
#define IRQ_U300_ISP_F3 48
|
||||
#define IRQ_U300_ISP_F4 49
|
||||
#define IRQ_U300_GPIO_PORT3 50
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 51
|
||||
#define IRQ_U300_UART1 52
|
||||
#define IRQ_U300_GPIO_PORT4 53
|
||||
#define IRQ_U300_GPIO_PORT5 54
|
||||
#define IRQ_U300_GPIO_PORT6 55
|
||||
#define U300_VIC_IRQS_END 56
|
||||
#define IRQ_U300_ISP_F0 46
|
||||
#define IRQ_U300_ISP_F1 47
|
||||
#define IRQ_U300_ISP_F2 48
|
||||
#define IRQ_U300_ISP_F3 49
|
||||
#define IRQ_U300_ISP_F4 50
|
||||
#define IRQ_U300_GPIO_PORT3 51
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 52
|
||||
#define IRQ_U300_UART1 53
|
||||
#define IRQ_U300_GPIO_PORT4 54
|
||||
#define IRQ_U300_GPIO_PORT5 55
|
||||
#define IRQ_U300_GPIO_PORT6 56
|
||||
#define U300_VIC_IRQS_END 57
|
||||
#endif
|
||||
|
||||
/* The DB3210-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS365
|
||||
#define IRQ_U300_GPIO_PORT3 35
|
||||
#define IRQ_U300_GPIO_PORT4 36
|
||||
#define IRQ_U300_WDOG 37
|
||||
#define IRQ_U300_EVHIST 38
|
||||
#define IRQ_U300_MSPRO 39
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 41
|
||||
#define IRQ_U300_I2C0 42
|
||||
#define IRQ_U300_I2C1 43
|
||||
#define IRQ_U300_RTC 44
|
||||
#define IRQ_U300_NFIF 45
|
||||
#define IRQ_U300_NFIF2 46
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 47
|
||||
#define U300_VIC_IRQS_END 48
|
||||
#define IRQ_U300_GPIO_PORT3 36
|
||||
#define IRQ_U300_GPIO_PORT4 37
|
||||
#define IRQ_U300_WDOG 38
|
||||
#define IRQ_U300_EVHIST 39
|
||||
#define IRQ_U300_MSPRO 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 41
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 42
|
||||
#define IRQ_U300_I2C0 43
|
||||
#define IRQ_U300_I2C1 44
|
||||
#define IRQ_U300_RTC 45
|
||||
#define IRQ_U300_NFIF 46
|
||||
#define IRQ_U300_NFIF2 47
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 48
|
||||
#define U300_VIC_IRQS_END 49
|
||||
#endif
|
||||
|
||||
/* Maximum 8*7 GPIO lines */
|
||||
|
@ -117,6 +117,6 @@
|
|||
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
|
||||
#endif
|
||||
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END)
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
|
|||
return sprintf(buf, "0x%X\n", mbox_value);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
|
||||
static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
|
||||
|
||||
static int mbox_show(struct seq_file *s, void *data)
|
||||
{
|
||||
|
|
|
@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
|
|||
mrc p15, 0, r1, c5, c0, 0 @ get FSR
|
||||
mrc p15, 0, r0, c6, c0, 0 @ get FAR
|
||||
/*
|
||||
* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
|
||||
* The test below covers all the write situations, including Java bytecodes
|
||||
* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
|
||||
*/
|
||||
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
|
||||
tst r5, #PSR_J_BIT @ Java?
|
||||
#ifdef CONFIG_ARM_ERRATA_326103
|
||||
ldr ip, =0x4107b36
|
||||
mrc p15, 0, r3, c0, c0, 0 @ get processor id
|
||||
teq ip, r3, lsr #4 @ r0 ARM1136?
|
||||
bne do_DataAbort
|
||||
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
|
||||
ldreq r3, [r4] @ read aborted ARM instruction
|
||||
tst r5, #PSR_J_BIT @ Java?
|
||||
tsteq r5, #PSR_T_BIT @ Thumb?
|
||||
bne do_DataAbort
|
||||
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
|
||||
ldr r3, [r4] @ read aborted ARM instruction
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
reveq r3, r3
|
||||
rev r3, r3
|
||||
#endif
|
||||
do_ldrd_abort tmp=ip, insn=r3
|
||||
tst r3, #1 << 20 @ L = 0 -> write
|
||||
orreq r1, r1, #1 << 11 @ yes.
|
||||
#endif
|
||||
b do_DataAbort
|
||||
|
|
|
@ -32,6 +32,7 @@ static void __iomem *l2x0_base;
|
|||
static DEFINE_RAW_SPINLOCK(l2x0_lock);
|
||||
static u32 l2x0_way_mask; /* Bitmask of active ways */
|
||||
static u32 l2x0_size;
|
||||
static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
|
||||
|
||||
struct l2x0_regs l2x0_saved_regs;
|
||||
|
||||
|
@ -61,12 +62,7 @@ static inline void cache_sync(void)
|
|||
{
|
||||
void __iomem *base = l2x0_base;
|
||||
|
||||
#ifdef CONFIG_PL310_ERRATA_753970
|
||||
/* write to an unmmapped register */
|
||||
writel_relaxed(0, base + L2X0_DUMMY_REG);
|
||||
#else
|
||||
writel_relaxed(0, base + L2X0_CACHE_SYNC);
|
||||
#endif
|
||||
writel_relaxed(0, base + sync_reg_offset);
|
||||
cache_wait(base + L2X0_CACHE_SYNC, 1);
|
||||
}
|
||||
|
||||
|
@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
|
||||
static inline void debug_writel(unsigned long val)
|
||||
{
|
||||
if (outer_cache.set_debug)
|
||||
outer_cache.set_debug(val);
|
||||
}
|
||||
|
||||
#define debug_writel(val) outer_cache.set_debug(val)
|
||||
|
||||
static void l2x0_set_debug(unsigned long val)
|
||||
static void pl310_set_debug(unsigned long val)
|
||||
{
|
||||
writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
|
||||
}
|
||||
|
@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val)
|
|||
{
|
||||
}
|
||||
|
||||
#define l2x0_set_debug NULL
|
||||
#define pl310_set_debug NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PL310_ERRATA_588369
|
||||
|
@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
|
|||
else
|
||||
ways = 8;
|
||||
type = "L310";
|
||||
#ifdef CONFIG_PL310_ERRATA_753970
|
||||
/* Unmapped register. */
|
||||
sync_reg_offset = L2X0_DUMMY_REG;
|
||||
#endif
|
||||
outer_cache.set_debug = pl310_set_debug;
|
||||
break;
|
||||
case L2X0_CACHE_ID_PART_L210:
|
||||
ways = (aux >> 13) & 0xf;
|
||||
|
@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
|
|||
outer_cache.flush_all = l2x0_flush_all;
|
||||
outer_cache.inv_all = l2x0_inv_all;
|
||||
outer_cache.disable = l2x0_disable;
|
||||
outer_cache.set_debug = l2x0_set_debug;
|
||||
|
||||
printk(KERN_INFO "%s cache controller enabled\n", type);
|
||||
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
|
||||
|
|
|
@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid);
|
|||
#endif
|
||||
|
||||
#ifndef CONFIG_SPARSEMEM
|
||||
static void arm_memory_present(void)
|
||||
static void __init arm_memory_present(void)
|
||||
{
|
||||
}
|
||||
#else
|
||||
static void arm_memory_present(void)
|
||||
static void __init arm_memory_present(void)
|
||||
{
|
||||
struct memblock_region *reg;
|
||||
|
||||
|
|
|
@ -618,8 +618,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
|
|||
}
|
||||
}
|
||||
|
||||
static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
|
||||
unsigned long phys, const struct mem_type *type)
|
||||
static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
|
||||
unsigned long end, unsigned long phys, const struct mem_type *type)
|
||||
{
|
||||
pud_t *pud = pud_offset(pgd, addr);
|
||||
unsigned long next;
|
||||
|
|
|
@ -916,6 +916,13 @@ void omap_start_dma(int lch)
|
|||
l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
|
||||
l |= OMAP_DMA_CCR_EN;
|
||||
|
||||
/*
|
||||
* As dma_write() uses IO accessors which are weakly ordered, there
|
||||
* is no guarantee that data in coherent DMA memory will be visible
|
||||
* to the DMA device. Add a memory barrier here to ensure that any
|
||||
* such data is visible prior to enabling DMA.
|
||||
*/
|
||||
mb();
|
||||
p->dma_write(l, CCR, lch);
|
||||
|
||||
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
|
||||
|
@ -965,6 +972,13 @@ void omap_stop_dma(int lch)
|
|||
p->dma_write(l, CCR, lch);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that data transferred by DMA is visible to any access
|
||||
* after DMA has been disabled. This is important for coherent
|
||||
* DMA regions.
|
||||
*/
|
||||
mb();
|
||||
|
||||
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
|
||||
int next_lch, cur_lch = lch;
|
||||
char dma_chan_link_map[dma_lch_count];
|
||||
|
|
|
@ -18,6 +18,8 @@
|
|||
#ifndef __PLAT_S3C_SDHCI_H
|
||||
#define __PLAT_S3C_SDHCI_H __FILE__
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
struct platform_device;
|
||||
struct mmc_host;
|
||||
struct mmc_card;
|
||||
|
@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
|
|||
|
||||
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
|
||||
|
||||
static inline void s3c_sdhci_setname(int id, char *name)
|
||||
{
|
||||
switch (id) {
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC
|
||||
case 0:
|
||||
s3c_device_hsmmc0.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC1
|
||||
case 1:
|
||||
s3c_device_hsmmc1.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC2
|
||||
case 2:
|
||||
s3c_device_hsmmc2.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC3
|
||||
case 3:
|
||||
s3c_device_hsmmc3.name = name;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __PLAT_S3C_SDHCI_H */
|
||||
|
|
|
@ -17,6 +17,8 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/user.h>
|
||||
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/cputype.h>
|
||||
|
@ -528,6 +530,103 @@ void vfp_flush_hwstate(struct thread_info *thread)
|
|||
put_cpu();
|
||||
}
|
||||
|
||||
/*
|
||||
* Save the current VFP state into the provided structures and prepare
|
||||
* for entry into a new function (signal handler).
|
||||
*/
|
||||
int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp,
|
||||
struct user_vfp_exc __user *ufp_exc)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
|
||||
int err = 0;
|
||||
|
||||
/* Ensure that the saved hwstate is up-to-date. */
|
||||
vfp_sync_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs,
|
||||
sizeof(hwstate->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__put_user_error(hwstate->fpscr, &ufp->fpscr, err);
|
||||
|
||||
/*
|
||||
* Copy the exception registers.
|
||||
*/
|
||||
__put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err);
|
||||
__put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
|
||||
__put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
|
||||
|
||||
if (err)
|
||||
return -EFAULT;
|
||||
|
||||
/* Ensure that VFP is disabled. */
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* As per the PCS, clear the length and stride bits for function
|
||||
* entry.
|
||||
*/
|
||||
hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK);
|
||||
|
||||
/*
|
||||
* Disable VFP in the hwstate so that we can detect if it gets
|
||||
* used.
|
||||
*/
|
||||
hwstate->fpexc &= ~FPEXC_EN;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Sanitise and restore the current VFP state from the provided structures. */
|
||||
int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
|
||||
struct user_vfp_exc __user *ufp_exc)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
|
||||
unsigned long fpexc;
|
||||
int err = 0;
|
||||
|
||||
/*
|
||||
* If VFP has been used, then disable it to avoid corrupting
|
||||
* the new thread state.
|
||||
*/
|
||||
if (hwstate->fpexc & FPEXC_EN)
|
||||
vfp_flush_hwstate(thread);
|
||||
|
||||
/*
|
||||
* Copy the floating point registers. There can be unused
|
||||
* registers see asm/hwcap.h for details.
|
||||
*/
|
||||
err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs,
|
||||
sizeof(hwstate->fpregs));
|
||||
/*
|
||||
* Copy the status and control register.
|
||||
*/
|
||||
__get_user_error(hwstate->fpscr, &ufp->fpscr, err);
|
||||
|
||||
/*
|
||||
* Sanitise and restore the exception registers.
|
||||
*/
|
||||
__get_user_error(fpexc, &ufp_exc->fpexc, err);
|
||||
|
||||
/* Ensure the VFP is enabled. */
|
||||
fpexc |= FPEXC_EN;
|
||||
|
||||
/* Ensure FPINST2 is invalid and the exception flag is cleared. */
|
||||
fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
|
||||
hwstate->fpexc = fpexc;
|
||||
|
||||
__get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
|
||||
__get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* VFP hardware can lose all context when a CPU goes offline.
|
||||
* As we will be running in SMP mode with CPU hotplug, we will save the
|
||||
|
|
|
@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
|
|||
.name = "rtc-bfin",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_RTC_DRV_BFIN */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
|
@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
|
|||
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART0 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
static struct resource bfin_uart1_resources[] = {
|
||||
{
|
||||
|
@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
|
|||
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART1 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART2
|
||||
static struct resource bfin_uart2_resources[] = {
|
||||
{
|
||||
|
@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
|
|||
.platform_data = &bfin_uart2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART2 */
|
||||
#endif /* CONFIG_SERIAL_BFIN */
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
|
@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR0 */
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
static struct resource bfin_sir1_resources[] = {
|
||||
{
|
||||
|
@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
||||
.resource = bfin_sir1_resources,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR1 */
|
||||
#ifdef CONFIG_BFIN_SIR2
|
||||
static struct resource bfin_sir2_resources[] = {
|
||||
{
|
||||
|
@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir2_resources),
|
||||
.resource = bfin_sir2_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR2 */
|
||||
#endif /* CONFIG_BFIN_SIR */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||||
|
@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
|
|||
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||||
static struct resource bfin_sport1_uart_resources[] = {
|
||||
{
|
||||
|
@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
|
|||
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
|
||||
static struct resource bfin_sport2_uart_resources[] = {
|
||||
{
|
||||
|
@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
|
|||
.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
|
||||
static struct resource bfin_sport3_uart_resources[] = {
|
||||
{
|
||||
|
@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
|
|||
.platform_data = &bfin_sport3_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT */
|
||||
|
||||
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
|
||||
static unsigned short bfin_can_peripherals[] = {
|
||||
|
@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
|
|||
.platform_data = &bfin_can_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_CAN_BFIN */
|
||||
|
||||
/*
|
||||
* USB-LAN EzExtender board
|
||||
|
@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
|
|||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
|
||||
/* all SPI peripherals info goes here */
|
||||
|
@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
|
|||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#endif /* CONFIG_SPI_BFIN5XX */
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
|
||||
#include <linux/spi/ad7879.h>
|
||||
|
@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
|
|||
.gpio_export = 1, /* Export GPIO to gpiolib */
|
||||
.gpio_base = -1, /* Dynamic allocation */
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879 */
|
||||
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
#include <asm/bfin-lq035q1.h>
|
||||
|
@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
|
|||
.platform_data = &bfin_lq035q1_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
|
||||
static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|
@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
|
||||
{
|
||||
.modalias = "ad7879",
|
||||
|
@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.chip_select = 1,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
{
|
||||
.modalias = "bfin-lq035q1-spi",
|
||||
|
@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.chip_select = 2,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
|
@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_SPI_SPIDEV */
|
||||
};
|
||||
|
||||
/* SPI (0) */
|
||||
|
@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
|
|||
},
|
||||
};
|
||||
|
||||
#endif /* spi master and devices */
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
static struct resource bfin_twi0_resource[] = {
|
||||
[0] = {
|
||||
|
@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
|
||||
.resource = bfin_twi1_resource,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_BF542 */
|
||||
#endif /* CONFIG_I2C_BLACKFIN_TWI */
|
||||
|
||||
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
|
||||
#include <linux/gpio_keys.h>
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/bootmem.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <asm/dma-mapping.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
struct dma_map_ops *dma_ops;
|
||||
EXPORT_SYMBOL(dma_ops);
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Process creation support for Hexagon
|
||||
*
|
||||
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
|
|||
void cpu_idle(void)
|
||||
{
|
||||
while (1) {
|
||||
tick_nohz_stop_sched_tick(1);
|
||||
tick_nohz_idle_enter();
|
||||
local_irq_disable();
|
||||
while (!need_resched()) {
|
||||
idle_sleep();
|
||||
|
@ -97,7 +97,7 @@ void cpu_idle(void)
|
|||
local_irq_disable();
|
||||
}
|
||||
local_irq_enable();
|
||||
tick_nohz_restart_sched_tick();
|
||||
tick_nohz_idle_exit();
|
||||
schedule();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/ptrace.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/elf.h>
|
||||
|
||||
#include <asm/user.h>
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SMP support for Hexagon
|
||||
*
|
||||
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -28,6 +28,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/cpu.h>
|
||||
|
||||
#include <asm/time.h> /* timer_interrupt */
|
||||
#include <asm/hexagon_vm.h>
|
||||
|
@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
|
|||
|
||||
printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
|
||||
|
||||
notify_cpu_starting(cpu);
|
||||
|
||||
ipi_call_lock();
|
||||
set_cpu_online(cpu, true);
|
||||
ipi_call_unlock();
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
cpu_idle();
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/timer-regs.h>
|
||||
#include <asm/hexagon_vm.h>
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/binfmts.h>
|
||||
|
||||
#include <asm/vdso.h>
|
||||
|
||||
|
|
|
@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void)
|
|||
|
||||
static int ar933x_wmac_reset(void)
|
||||
{
|
||||
ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||
ath79_device_reset_set(AR933X_RESET_WMAC);
|
||||
ath79_device_reset_clear(AR933X_RESET_WMAC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -45,7 +45,7 @@
|
|||
#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
|
||||
|
||||
/* 2nd-level interrupts */
|
||||
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X))
|
||||
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (x))
|
||||
|
||||
#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
|
||||
#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
|
||||
|
|
|
@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
|
|||
write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
|
||||
} while (0)
|
||||
|
||||
|
||||
static inline unsigned long get_current_pgd(void)
|
||||
{
|
||||
return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
|
||||
}
|
||||
|
||||
#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
|
||||
|
||||
/*
|
||||
|
|
|
@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&blocked, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = blocked;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
sig = restore_sigcontext(®s, &frame->sf_sc);
|
||||
if (sig < 0)
|
||||
|
@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
|
||||
sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext);
|
||||
if (sig < 0)
|
||||
|
@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NODEFER))
|
||||
sigaddset(¤t->blocked, sig);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
block_sigmask(ka, sig);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
return -EFAULT;
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&blocked, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = blocked;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
sig = restore_sigcontext32(®s, &frame->sf_sc);
|
||||
if (sig < 0)
|
||||
|
@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
|
||||
sig = restore_sigcontext32(®s, &frame->rs_uc.uc_mcontext);
|
||||
if (sig < 0)
|
||||
|
|
|
@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
|
|||
sigset_from_compat(&newset, &uset);
|
||||
sigdelsetmask(&newset, ~_BLOCKABLE);
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->saved_sigmask = current->blocked;
|
||||
current->blocked = newset;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&newset);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
|
|||
goto badframe;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
|
||||
sig = restore_sigcontext(®s, &frame->rs_uc.uc_mcontext);
|
||||
if (sig < 0)
|
||||
|
|
|
@ -104,7 +104,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
|
|||
|
||||
static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
|
||||
{
|
||||
if (!tty->count) {
|
||||
if (tty->count == 1) {
|
||||
del_timer_sync(&pdc_console_timer);
|
||||
tty_port_tty_set(&tty_port, NULL);
|
||||
}
|
||||
|
|
43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
Normal file
43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
Normal file
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
message@42400 {
|
||||
compatible = "fsl,mpic-v3.1-msgr";
|
||||
reg = <0x42400 0x200>;
|
||||
interrupts = <
|
||||
0xb4 2 0 0
|
||||
0xb5 2 0 0
|
||||
0xb6 2 0 0
|
||||
0xb7 2 0 0>;
|
||||
};
|
|
@ -53,6 +53,16 @@ timer@41100 {
|
|||
3 0 3 0>;
|
||||
};
|
||||
|
||||
message@41400 {
|
||||
compatible = "fsl,mpic-v3.1-msgr";
|
||||
reg = <0x41400 0x200>;
|
||||
interrupts = <
|
||||
0xb0 2 0 0
|
||||
0xb1 2 0 0
|
||||
0xb2 2 0 0
|
||||
0xb3 2 0 0>;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
|
|
|
@ -18,10 +18,6 @@
|
|||
#include <linux/atomic.h>
|
||||
|
||||
|
||||
/* Define a way to iterate across irqs. */
|
||||
#define for_each_irq(i) \
|
||||
for ((i) = 0; (i) < NR_IRQS; ++(i))
|
||||
|
||||
extern atomic_t ppc_n_lost_interrupts;
|
||||
|
||||
/* This number is used when no interrupt has been assigned */
|
||||
|
|
|
@ -275,9 +275,6 @@ struct mpic
|
|||
unsigned int isu_mask;
|
||||
/* Number of sources */
|
||||
unsigned int num_sources;
|
||||
/* default senses array */
|
||||
unsigned char *senses;
|
||||
unsigned int senses_count;
|
||||
|
||||
/* vector numbers used for internal sources (ipi/timers) */
|
||||
unsigned int ipi_vecs[4];
|
||||
|
@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
|
|||
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
|
||||
phys_addr_t phys_addr);
|
||||
|
||||
/* Set default sense codes
|
||||
*
|
||||
* @mpic: controller
|
||||
* @senses: array of sense codes
|
||||
* @count: size of above array
|
||||
*
|
||||
* Optionally provide an array (indexed on hardware interrupt numbers
|
||||
* for this MPIC) of default sense codes for the chip. Those are linux
|
||||
* sense codes IRQ_TYPE_*
|
||||
*
|
||||
* The driver gets ownership of the pointer, don't dispose of it or
|
||||
* anything like that. __init only.
|
||||
*/
|
||||
extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
|
||||
|
||||
|
||||
/* Initialize the controller. After this has been called, none of the above
|
||||
* should be called again for this mpic
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/smp.h>
|
||||
|
||||
struct mpic_msgr {
|
||||
u32 __iomem *base;
|
||||
|
|
|
@ -15,11 +15,6 @@
|
|||
#ifndef __ASM_POWERPC_REG_BOOKE_H__
|
||||
#define __ASM_POWERPC_REG_BOOKE_H__
|
||||
|
||||
#ifdef CONFIG_BOOKE_WDT
|
||||
extern u32 booke_wdt_enabled;
|
||||
extern u32 booke_wdt_period;
|
||||
#endif /* CONFIG_BOOKE_WDT */
|
||||
|
||||
/* Machine State Register (MSR) Fields */
|
||||
#define MSR_GS (1<<28) /* Guest state */
|
||||
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
|
||||
|
|
|
@ -330,14 +330,10 @@ void migrate_irqs(void)
|
|||
|
||||
alloc_cpumask_var(&mask, GFP_KERNEL);
|
||||
|
||||
for_each_irq(irq) {
|
||||
for_each_irq_desc(irq, desc) {
|
||||
struct irq_data *data;
|
||||
struct irq_chip *chip;
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
if (!desc)
|
||||
continue;
|
||||
|
||||
data = irq_desc_get_irq_data(desc);
|
||||
if (irqd_is_per_cpu(data))
|
||||
continue;
|
||||
|
|
|
@ -23,14 +23,11 @@
|
|||
|
||||
void machine_kexec_mask_interrupts(void) {
|
||||
unsigned int i;
|
||||
struct irq_desc *desc;
|
||||
|
||||
for_each_irq(i) {
|
||||
struct irq_desc *desc = irq_to_desc(i);
|
||||
for_each_irq_desc(i, desc) {
|
||||
struct irq_chip *chip;
|
||||
|
||||
if (!desc)
|
||||
continue;
|
||||
|
||||
chip = irq_desc_get_chip(desc);
|
||||
if (!chip)
|
||||
continue;
|
||||
|
|
|
@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_BOOKE_WDT
|
||||
extern u32 booke_wdt_enabled;
|
||||
extern u32 booke_wdt_period;
|
||||
|
||||
/* Checks wdt=x and wdt_period=xx command-line option */
|
||||
notrace int __init early_parse_wdt(char *p)
|
||||
{
|
||||
|
|
|
@ -48,7 +48,13 @@
|
|||
/*
|
||||
* Assembly helpers from arch/powerpc/net/bpf_jit.S:
|
||||
*/
|
||||
extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[];
|
||||
#define DECLARE_LOAD_FUNC(func) \
|
||||
extern u8 func[], func##_negative_offset[], func##_positive_offset[]
|
||||
|
||||
DECLARE_LOAD_FUNC(sk_load_word);
|
||||
DECLARE_LOAD_FUNC(sk_load_half);
|
||||
DECLARE_LOAD_FUNC(sk_load_byte);
|
||||
DECLARE_LOAD_FUNC(sk_load_byte_msh);
|
||||
|
||||
#define FUNCTION_DESCR_SIZE 24
|
||||
|
||||
|
|
|
@ -31,14 +31,13 @@
|
|||
* then branch directly to slow_path_XXX if required. (In fact, could
|
||||
* load a spare GPR with the address of slow_path_generic and pass size
|
||||
* as an argument, making the call site a mtlr, li and bllr.)
|
||||
*
|
||||
* Technically, the "is addr < 0" check is unnecessary & slowing down
|
||||
* the ABS path, as it's statically checked on generation.
|
||||
*/
|
||||
.globl sk_load_word
|
||||
sk_load_word:
|
||||
cmpdi r_addr, 0
|
||||
blt bpf_error
|
||||
blt bpf_slow_path_word_neg
|
||||
.globl sk_load_word_positive_offset
|
||||
sk_load_word_positive_offset:
|
||||
/* Are we accessing past headlen? */
|
||||
subi r_scratch1, r_HL, 4
|
||||
cmpd r_scratch1, r_addr
|
||||
|
@ -51,7 +50,9 @@ sk_load_word:
|
|||
.globl sk_load_half
|
||||
sk_load_half:
|
||||
cmpdi r_addr, 0
|
||||
blt bpf_error
|
||||
blt bpf_slow_path_half_neg
|
||||
.globl sk_load_half_positive_offset
|
||||
sk_load_half_positive_offset:
|
||||
subi r_scratch1, r_HL, 2
|
||||
cmpd r_scratch1, r_addr
|
||||
blt bpf_slow_path_half
|
||||
|
@ -61,7 +62,9 @@ sk_load_half:
|
|||
.globl sk_load_byte
|
||||
sk_load_byte:
|
||||
cmpdi r_addr, 0
|
||||
blt bpf_error
|
||||
blt bpf_slow_path_byte_neg
|
||||
.globl sk_load_byte_positive_offset
|
||||
sk_load_byte_positive_offset:
|
||||
cmpd r_HL, r_addr
|
||||
ble bpf_slow_path_byte
|
||||
lbzx r_A, r_D, r_addr
|
||||
|
@ -69,22 +72,20 @@ sk_load_byte:
|
|||
|
||||
/*
|
||||
* BPF_S_LDX_B_MSH: ldxb 4*([offset]&0xf)
|
||||
* r_addr is the offset value, already known positive
|
||||
* r_addr is the offset value
|
||||
*/
|
||||
.globl sk_load_byte_msh
|
||||
sk_load_byte_msh:
|
||||
cmpdi r_addr, 0
|
||||
blt bpf_slow_path_byte_msh_neg
|
||||
.globl sk_load_byte_msh_positive_offset
|
||||
sk_load_byte_msh_positive_offset:
|
||||
cmpd r_HL, r_addr
|
||||
ble bpf_slow_path_byte_msh
|
||||
lbzx r_X, r_D, r_addr
|
||||
rlwinm r_X, r_X, 2, 32-4-2, 31-2
|
||||
blr
|
||||
|
||||
bpf_error:
|
||||
/* Entered with cr0 = lt */
|
||||
li r3, 0
|
||||
/* Generated code will 'blt epilogue', returning 0. */
|
||||
blr
|
||||
|
||||
/* Call out to skb_copy_bits:
|
||||
* We'll need to back up our volatile regs first; we have
|
||||
* local variable space at r1+(BPF_PPC_STACK_BASIC).
|
||||
|
@ -136,3 +137,84 @@ bpf_slow_path_byte_msh:
|
|||
lbz r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
|
||||
rlwinm r_X, r_X, 2, 32-4-2, 31-2
|
||||
blr
|
||||
|
||||
/* Call out to bpf_internal_load_pointer_neg_helper:
|
||||
* We'll need to back up our volatile regs first; we have
|
||||
* local variable space at r1+(BPF_PPC_STACK_BASIC).
|
||||
* Allocate a new stack frame here to remain ABI-compliant in
|
||||
* stashing LR.
|
||||
*/
|
||||
#define sk_negative_common(SIZE) \
|
||||
mflr r0; \
|
||||
std r0, 16(r1); \
|
||||
/* R3 goes in parameter space of caller's frame */ \
|
||||
std r_skb, (BPF_PPC_STACKFRAME+48)(r1); \
|
||||
std r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1); \
|
||||
std r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1); \
|
||||
stdu r1, -BPF_PPC_SLOWPATH_FRAME(r1); \
|
||||
/* R3 = r_skb, as passed */ \
|
||||
mr r4, r_addr; \
|
||||
li r5, SIZE; \
|
||||
bl bpf_internal_load_pointer_neg_helper; \
|
||||
/* R3 != 0 on success */ \
|
||||
addi r1, r1, BPF_PPC_SLOWPATH_FRAME; \
|
||||
ld r0, 16(r1); \
|
||||
ld r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1); \
|
||||
ld r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1); \
|
||||
mtlr r0; \
|
||||
cmpldi r3, 0; \
|
||||
beq bpf_error_slow; /* cr0 = EQ */ \
|
||||
mr r_addr, r3; \
|
||||
ld r_skb, (BPF_PPC_STACKFRAME+48)(r1); \
|
||||
/* Great success! */
|
||||
|
||||
bpf_slow_path_word_neg:
|
||||
lis r_scratch1,-32 /* SKF_LL_OFF */
|
||||
cmpd r_addr, r_scratch1 /* addr < SKF_* */
|
||||
blt bpf_error /* cr0 = LT */
|
||||
.globl sk_load_word_negative_offset
|
||||
sk_load_word_negative_offset:
|
||||
sk_negative_common(4)
|
||||
lwz r_A, 0(r_addr)
|
||||
blr
|
||||
|
||||
bpf_slow_path_half_neg:
|
||||
lis r_scratch1,-32 /* SKF_LL_OFF */
|
||||
cmpd r_addr, r_scratch1 /* addr < SKF_* */
|
||||
blt bpf_error /* cr0 = LT */
|
||||
.globl sk_load_half_negative_offset
|
||||
sk_load_half_negative_offset:
|
||||
sk_negative_common(2)
|
||||
lhz r_A, 0(r_addr)
|
||||
blr
|
||||
|
||||
bpf_slow_path_byte_neg:
|
||||
lis r_scratch1,-32 /* SKF_LL_OFF */
|
||||
cmpd r_addr, r_scratch1 /* addr < SKF_* */
|
||||
blt bpf_error /* cr0 = LT */
|
||||
.globl sk_load_byte_negative_offset
|
||||
sk_load_byte_negative_offset:
|
||||
sk_negative_common(1)
|
||||
lbz r_A, 0(r_addr)
|
||||
blr
|
||||
|
||||
bpf_slow_path_byte_msh_neg:
|
||||
lis r_scratch1,-32 /* SKF_LL_OFF */
|
||||
cmpd r_addr, r_scratch1 /* addr < SKF_* */
|
||||
blt bpf_error /* cr0 = LT */
|
||||
.globl sk_load_byte_msh_negative_offset
|
||||
sk_load_byte_msh_negative_offset:
|
||||
sk_negative_common(1)
|
||||
lbz r_X, 0(r_addr)
|
||||
rlwinm r_X, r_X, 2, 32-4-2, 31-2
|
||||
blr
|
||||
|
||||
bpf_error_slow:
|
||||
/* fabricate a cr0 = lt */
|
||||
li r_scratch1, -1
|
||||
cmpdi r_scratch1, 0
|
||||
bpf_error:
|
||||
/* Entered with cr0 = lt */
|
||||
li r3, 0
|
||||
/* Generated code will 'blt epilogue', returning 0. */
|
||||
blr
|
||||
|
|
|
@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
|
|||
PPC_BLR();
|
||||
}
|
||||
|
||||
#define CHOOSE_LOAD_FUNC(K, func) \
|
||||
((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
|
||||
|
||||
/* Assemble the body code between the prologue & epilogue. */
|
||||
static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
|
||||
struct codegen_context *ctx,
|
||||
|
@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
|
|||
|
||||
/*** Absolute loads from packet header/data ***/
|
||||
case BPF_S_LD_W_ABS:
|
||||
func = sk_load_word;
|
||||
func = CHOOSE_LOAD_FUNC(K, sk_load_word);
|
||||
goto common_load;
|
||||
case BPF_S_LD_H_ABS:
|
||||
func = sk_load_half;
|
||||
func = CHOOSE_LOAD_FUNC(K, sk_load_half);
|
||||
goto common_load;
|
||||
case BPF_S_LD_B_ABS:
|
||||
func = sk_load_byte;
|
||||
func = CHOOSE_LOAD_FUNC(K, sk_load_byte);
|
||||
common_load:
|
||||
/*
|
||||
* Load from [K]. Reference with the (negative)
|
||||
* SKF_NET_OFF/SKF_LL_OFF offsets is unsupported.
|
||||
*/
|
||||
/* Load from [K]. */
|
||||
ctx->seen |= SEEN_DATAREF;
|
||||
if ((int)K < 0)
|
||||
return -ENOTSUPP;
|
||||
PPC_LI64(r_scratch1, func);
|
||||
PPC_MTLR(r_scratch1);
|
||||
PPC_LI32(r_addr, K);
|
||||
|
@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
|
|||
common_load_ind:
|
||||
/*
|
||||
* Load from [X + K]. Negative offsets are tested for
|
||||
* in the helper functions, and result in a 'ret 0'.
|
||||
* in the helper functions.
|
||||
*/
|
||||
ctx->seen |= SEEN_DATAREF | SEEN_XREG;
|
||||
PPC_LI64(r_scratch1, func);
|
||||
|
@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
|
|||
break;
|
||||
|
||||
case BPF_S_LDX_B_MSH:
|
||||
/*
|
||||
* x86 version drops packet (RET 0) when K<0, whereas
|
||||
* interpreter does allow K<0 (__load_pointer, special
|
||||
* ancillary data). common_load returns ENOTSUPP if K<0,
|
||||
* so we fall back to interpreter & filter works.
|
||||
*/
|
||||
func = sk_load_byte_msh;
|
||||
func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh);
|
||||
goto common_load;
|
||||
break;
|
||||
|
||||
|
|
|
@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
|
|||
{ .compatible = "fsl,qe", },
|
||||
{ .compatible = "fsl,cpm2", },
|
||||
{ .compatible = "fsl,srio", },
|
||||
/* So that the DMA channel nodes can be probed individually: */
|
||||
{ .compatible = "fsl,eloplus-dma", },
|
||||
/* For the PMC driver */
|
||||
{ .compatible = "fsl,mpc8548-guts", },
|
||||
/* Probably unnecessary? */
|
||||
{ .compatible = "gpio-leds", },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -399,12 +399,6 @@ static int __init board_fixups(void)
|
|||
machine_arch_initcall(mpc8568_mds, board_fixups);
|
||||
machine_arch_initcall(mpc8569_mds, board_fixups);
|
||||
|
||||
static struct of_device_id mpc85xx_ids[] = {
|
||||
{ .compatible = "fsl,mpc8548-guts", },
|
||||
{ .compatible = "gpio-leds", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init mpc85xx_publish_devices(void)
|
||||
{
|
||||
if (machine_is(mpc8568_mds))
|
||||
|
@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
|
|||
if (machine_is(mpc8569_mds))
|
||||
simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
|
||||
|
||||
mpc85xx_common_publish_devices();
|
||||
of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
|
||||
|
||||
return 0;
|
||||
return mpc85xx_common_publish_devices();
|
||||
}
|
||||
|
||||
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
|
||||
|
|
|
@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
|
|||
pr_info("Freescale P1022 DS reference board\n");
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata p1022_ds_ids[] = {
|
||||
/* So that the DMA channel nodes can be probed individually: */
|
||||
{ .compatible = "fsl,eloplus-dma", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init p1022_ds_publish_devices(void)
|
||||
{
|
||||
mpc85xx_common_publish_devices();
|
||||
return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
|
||||
}
|
||||
machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
|
||||
machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
|
||||
|
||||
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
|
||||
|
||||
|
|
|
@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
|
|||
pr_devel("axon_msi: woff %x roff %x msi %x\n",
|
||||
write_offset, msic->read_offset, msi);
|
||||
|
||||
if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
|
||||
if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
|
||||
generic_handle_irq(msi);
|
||||
msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
|
||||
} else {
|
||||
|
@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
|
|||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* We rely on being able to stash a virq in a u16 */
|
||||
BUILD_BUG_ON(NR_IRQS > 65536);
|
||||
|
||||
list_for_each_entry(entry, &dev->msi_list, list) {
|
||||
virq = irq_create_direct_mapping(msic->irq_domain);
|
||||
if (virq == NO_IRQ) {
|
||||
|
@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device)
|
|||
}
|
||||
memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
|
||||
|
||||
msic->irq_domain = irq_domain_add_nomap(dn, 0, &msic_host_ops, msic);
|
||||
/* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
|
||||
msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
|
||||
if (!msic->irq_domain) {
|
||||
printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
|
||||
dn->full_name);
|
||||
|
|
|
@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void)
|
|||
{
|
||||
int i;
|
||||
|
||||
for (i = 1; i < NR_IRQS; i++)
|
||||
for (i = 1; i < nr_irqs; i++)
|
||||
beat_destruct_irq_plug(i);
|
||||
}
|
||||
|
|
|
@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
|
|||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
|
||||
/*
|
||||
* If the timer is pending, that means we raced with the
|
||||
* irq, in which case we just return
|
||||
*/
|
||||
if (timer_pending(&host->timeout_timer))
|
||||
goto skip;
|
||||
|
||||
kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
|
||||
if (host->state != state_idle) {
|
||||
host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
|
||||
add_timer(&host->timeout_timer);
|
||||
}
|
||||
skip:
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
@ -57,9 +57,9 @@ static int max_real_irqs;
|
|||
|
||||
static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
|
||||
|
||||
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
|
||||
static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
|
||||
static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
|
||||
/* The max irq number this driver deals with is 128; see max_irqs */
|
||||
static DECLARE_BITMAP(ppc_lost_interrupts, 128);
|
||||
static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
|
||||
static int pmac_irq_cascade = -1;
|
||||
static struct irq_domain *pmac_pic_host;
|
||||
|
||||
|
|
|
@ -30,9 +30,9 @@ config PPC_SPLPAR
|
|||
two or more partitions.
|
||||
|
||||
config EEH
|
||||
bool "PCI Extended Error Handling (EEH)" if EXPERT
|
||||
bool
|
||||
depends on PPC_PSERIES && PCI
|
||||
default y if !EXPERT
|
||||
default y
|
||||
|
||||
config PSERIES_MSI
|
||||
bool
|
||||
|
|
|
@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
|
|||
pr_debug("EEH: Adding device %s\n", pci_name(dev));
|
||||
|
||||
dn = pci_device_to_OF_node(dev);
|
||||
edev = pci_dev_to_eeh_dev(dev);
|
||||
edev = of_node_to_eeh_dev(dn);
|
||||
if (edev->pdev == dev) {
|
||||
pr_debug("EEH: Already referenced !\n");
|
||||
return;
|
||||
|
|
|
@ -51,8 +51,7 @@
|
|||
static intctl_cpm2_t __iomem *cpm2_intctl;
|
||||
|
||||
static struct irq_domain *cpm2_pic_host;
|
||||
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
|
||||
static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
|
||||
static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
|
||||
|
||||
static const u_char irq_to_siureg[] = {
|
||||
1, 1, 1, 1, 1, 1, 1, 1,
|
||||
|
|
|
@ -18,69 +18,45 @@
|
|||
extern int cpm_get_irq(struct pt_regs *regs);
|
||||
|
||||
static struct irq_domain *mpc8xx_pic_host;
|
||||
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
|
||||
static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
|
||||
static unsigned long mpc8xx_cached_irq_mask;
|
||||
static sysconf8xx_t __iomem *siu_reg;
|
||||
|
||||
int cpm_get_irq(struct pt_regs *regs);
|
||||
static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
|
||||
{
|
||||
return 0x80000000 >> irqd_to_hwirq(d);
|
||||
}
|
||||
|
||||
static void mpc8xx_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
int bit, word;
|
||||
unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
|
||||
|
||||
bit = irq_nr & 0x1f;
|
||||
word = irq_nr >> 5;
|
||||
|
||||
ppc_cached_irq_mask[word] |= (1 << (31-bit));
|
||||
out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
|
||||
mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
|
||||
out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
|
||||
}
|
||||
|
||||
static void mpc8xx_mask_irq(struct irq_data *d)
|
||||
{
|
||||
int bit, word;
|
||||
unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
|
||||
|
||||
bit = irq_nr & 0x1f;
|
||||
word = irq_nr >> 5;
|
||||
|
||||
ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
|
||||
out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
|
||||
mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
|
||||
out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
|
||||
}
|
||||
|
||||
static void mpc8xx_ack(struct irq_data *d)
|
||||
{
|
||||
int bit;
|
||||
unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
|
||||
|
||||
bit = irq_nr & 0x1f;
|
||||
out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
|
||||
out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
|
||||
}
|
||||
|
||||
static void mpc8xx_end_irq(struct irq_data *d)
|
||||
{
|
||||
int bit, word;
|
||||
unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
|
||||
|
||||
bit = irq_nr & 0x1f;
|
||||
word = irq_nr >> 5;
|
||||
|
||||
ppc_cached_irq_mask[word] |= (1 << (31-bit));
|
||||
out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
|
||||
mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
|
||||
out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
|
||||
}
|
||||
|
||||
static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
|
||||
{
|
||||
if (flow_type & IRQ_TYPE_EDGE_FALLING) {
|
||||
irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
|
||||
/* only external IRQ senses are programmable */
|
||||
if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
|
||||
unsigned int siel = in_be32(&siu_reg->sc_siel);
|
||||
|
||||
/* only external IRQ senses are programmable */
|
||||
if ((hw & 1) == 0) {
|
||||
siel |= (0x80000000 >> hw);
|
||||
out_be32(&siu_reg->sc_siel, siel);
|
||||
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
||||
}
|
||||
siel |= mpc8xx_irqd_to_bit(d);
|
||||
out_be32(&siu_reg->sc_siel, siel);
|
||||
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
|
|||
IRQ_TYPE_EDGE_FALLING,
|
||||
};
|
||||
|
||||
if (intspec[0] > 0x1f)
|
||||
return 0;
|
||||
|
||||
*out_hwirq = intspec[0];
|
||||
if (intsize > 1 && intspec[1] < 4)
|
||||
*out_flags = map_pic_senses[intspec[1]];
|
||||
|
|
|
@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
|
|||
}
|
||||
|
||||
/* Determine if the linux irq is an IPI */
|
||||
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
|
||||
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
|
||||
{
|
||||
unsigned int src = virq_to_hw(irq);
|
||||
|
||||
return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
|
||||
}
|
||||
|
||||
/* Determine if the linux irq is a timer */
|
||||
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
|
||||
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
|
||||
{
|
||||
unsigned int src = virq_to_hw(irq);
|
||||
|
||||
return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
|
||||
}
|
||||
|
||||
|
@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
|
|||
if (src >= mpic->num_sources)
|
||||
return -EINVAL;
|
||||
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
if (mpic->senses && src < mpic->senses_count)
|
||||
flow_type = mpic->senses[src];
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
|
||||
|
||||
/* We don't support "none" type */
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_DEFAULT;
|
||||
|
||||
/* Default: read HW settings */
|
||||
if (flow_type == IRQ_TYPE_DEFAULT) {
|
||||
switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
|
||||
MPIC_INFO(VECPRI_SENSE_MASK))) {
|
||||
case MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
|
||||
flow_type = IRQ_TYPE_EDGE_RISING;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
|
||||
flow_type = IRQ_TYPE_EDGE_FALLING;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
|
||||
flow_type = IRQ_TYPE_LEVEL_HIGH;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Apply to irq desc */
|
||||
irqd_set_trigger_type(d, flow_type);
|
||||
|
||||
/* Apply to HW */
|
||||
if (mpic_is_ht_interrupt(mpic, src))
|
||||
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
|
||||
MPIC_VECPRI_SENSE_EDGE;
|
||||
else
|
||||
vecpri = mpic_type_to_vecpri(mpic, flow_type);
|
||||
|
||||
vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
|
||||
vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
|
||||
MPIC_INFO(VECPRI_SENSE_MASK));
|
||||
vnew |= vecpri;
|
||||
|
@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
|
|||
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
|
||||
|
||||
/* Set default irq type */
|
||||
irq_set_irq_type(virq, IRQ_TYPE_NONE);
|
||||
irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
|
||||
|
||||
/* If the MPIC was reset, then all vectors have already been
|
||||
* initialized. Otherwise, a per source lazy initialization
|
||||
|
@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
|
|||
mpic->num_sources = isu_first + mpic->isu_size;
|
||||
}
|
||||
|
||||
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
|
||||
{
|
||||
mpic->senses = senses;
|
||||
mpic->senses_count = count;
|
||||
}
|
||||
|
||||
void __init mpic_init(struct mpic *mpic)
|
||||
{
|
||||
int i, cpu;
|
||||
|
@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
|
|||
return;
|
||||
|
||||
raw_spin_lock_irqsave(&mpic_lock, flags);
|
||||
if (mpic_is_ipi(mpic, irq)) {
|
||||
if (mpic_is_ipi(mpic, src)) {
|
||||
reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
|
||||
~MPIC_VECPRI_PRIORITY_MASK;
|
||||
mpic_ipi_write(src - mpic->ipi_vecs[0],
|
||||
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
|
||||
} else if (mpic_is_tm(mpic, irq)) {
|
||||
} else if (mpic_is_tm(mpic, src)) {
|
||||
reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
|
||||
~MPIC_VECPRI_PRIORITY_MASK;
|
||||
mpic_tm_write(src - mpic->timer_vecs[0],
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
|
||||
static struct mpic_msgr **mpic_msgrs;
|
||||
static unsigned int mpic_msgr_count;
|
||||
static DEFINE_RAW_SPINLOCK(msgrs_lock);
|
||||
|
||||
static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
|
||||
{
|
||||
|
@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
|
|||
if (reg_num >= mpic_msgr_count)
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
raw_spin_lock_irqsave(&msgr->lock, flags);
|
||||
if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
|
||||
msgr = mpic_msgrs[reg_num];
|
||||
raw_spin_lock_irqsave(&msgrs_lock, flags);
|
||||
msgr = mpic_msgrs[reg_num];
|
||||
if (msgr->in_use == MSGR_FREE)
|
||||
msgr->in_use = MSGR_INUSE;
|
||||
}
|
||||
raw_spin_unlock_irqrestore(&msgr->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&msgrs_lock, flags);
|
||||
|
||||
return msgr;
|
||||
}
|
||||
|
@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
|
|||
|
||||
reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
|
||||
msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
|
||||
msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
|
||||
msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
|
||||
msgr->in_use = MSGR_FREE;
|
||||
msgr->num = i;
|
||||
raw_spin_lock_init(&msgr->lock);
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/debugfs.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/export.h>
|
||||
#include <asm/debug.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/scom.h>
|
||||
|
||||
|
|
|
@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void)
|
|||
{
|
||||
int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
|
||||
unsigned int irq, virq;
|
||||
struct irq_desc *desc;
|
||||
|
||||
/* If we used to be the default server, move to the new "boot_cpuid" */
|
||||
if (hw_cpu == xics_default_server)
|
||||
|
@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void)
|
|||
/* Allow IPIs again... */
|
||||
icp_ops->set_priority(DEFAULT_PRIORITY);
|
||||
|
||||
for_each_irq(virq) {
|
||||
struct irq_desc *desc;
|
||||
for_each_irq_desc(virq, desc) {
|
||||
struct irq_chip *chip;
|
||||
long server;
|
||||
unsigned long flags;
|
||||
|
@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void)
|
|||
/* We can't set affinity on ISA interrupts */
|
||||
if (virq < NUM_ISA_INTERRUPTS)
|
||||
continue;
|
||||
desc = irq_to_desc(virq);
|
||||
/* We only need to migrate enabled IRQS */
|
||||
if (!desc || !desc->action)
|
||||
if (!desc->action)
|
||||
continue;
|
||||
if (desc->irq_data.domain != xics_host)
|
||||
continue;
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#include <linux/types.h>
|
||||
#include <asm/cmpxchg.h>
|
||||
|
||||
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
|
||||
#define ATOMIC_INIT(i) { (i) }
|
||||
|
||||
#define atomic_read(v) (*(volatile int *)&(v)->counter)
|
||||
#define atomic_set(v,i) ((v)->counter = (i))
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue