sh: MS7712SE01 board support.
Support the SH7712 (SH3-DSP) Solution Engine reference board. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
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c86c5a9104
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9465a54fa4
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@ -33,6 +33,7 @@ config EARLY_SCIF_CONSOLE_PORT
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default "0xffe00000" if CPU_SUBTYPE_SH7780
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default "0xfffe9800" if CPU_SUBTYPE_SH7206
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default "0xf8420000" if CPU_SUBTYPE_SH7619
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default "0xa4400000" if CPU_SUBTYPE_SH7712
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default "0xffe80000" if CPU_SH4
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config EARLY_PRINTK
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@ -27,6 +27,8 @@ int sh_pcic_io_dummy;
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static inline volatile __u16 *
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port2adr(unsigned int port)
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{
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if (port & 0xff000000)
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return ( volatile __u16 *) port;
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if (port >= 0x2000)
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return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
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else if (port >= 0x1000)
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@ -55,6 +55,17 @@ void make_se770x_irq(struct ipr_data *table, unsigned int nr_irqs)
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}
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static struct ipr_data se770x_ipr_map[] = {
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/*
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* Super I/O (Just mimic PC):
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* 1: keyboard
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* 3: serial 0
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* 4: serial 1
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* 5: printer
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* 6: floppy
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* 8: rtc
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* 12: mouse
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* 14: ide0
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*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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/* This is default value */
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{ 0xf-0x2, 0, 8, 0x2 , BCR_ILCRA},
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@ -81,8 +92,10 @@ static struct ipr_data se770x_ipr_map[] = {
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{ 4, 0, 4, 0x0f- 4 ,BCR_ILCRC},
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{ 3, 0, 0, 0x0f- 3 ,BCR_ILCRC},
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{ 1, 0, 12, 0x0f- 1 ,BCR_ILCRD},
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#if defined(CONFIG_STNIC)
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/* ST NIC */
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{ 10, 0, 4, 0x0f-10 ,BCR_ILCRD}, /* LAN */
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#endif
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/* MRSHPC IRQs setting */
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{ 0, 0, 12, 0x0f- 0 ,BCR_ILCRE}, /* PCIRQ3 */
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{ 11, 0, 8, 0x0f-11 ,BCR_ILCRE}, /* PCIRQ2 */
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@ -100,18 +113,6 @@ static struct ipr_data se770x_ipr_map[] = {
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*/
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void __init init_se_IRQ(void)
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{
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/*
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* Super I/O (Just mimic PC):
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* 1: keyboard
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* 3: serial 0
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* 4: serial 1
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* 5: printer
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* 6: floppy
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* 8: rtc
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* 12: mouse
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* 14: ide0
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*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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/* Disable all interrupts */
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ctrl_outw(0, BCR_ILCRA);
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ctrl_outw(0, BCR_ILCRB);
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@ -120,6 +121,6 @@ void __init init_se_IRQ(void)
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ctrl_outw(0, BCR_ILCRE);
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ctrl_outw(0, BCR_ILCRF);
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ctrl_outw(0, BCR_ILCRG);
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#endif
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make_se770x_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
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}
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@ -117,7 +117,7 @@ static int __init se_devices_setup(void)
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{
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return platform_add_devices(se_devices, ARRAY_SIZE(se_devices));
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}
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__initcall(se_devices_setup);
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device_initcall(se_devices_setup);
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/*
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* The Machine Vector
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@ -133,6 +133,8 @@ struct sh_machine_vector mv_se __initmv = {
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.mv_nr_irqs = 61,
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
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.mv_nr_irqs = 86,
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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.mv_nr_irqs = 104,
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#endif
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.mv_inb = se_inb,
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@ -12,6 +12,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh7708.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh7709.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7300) += setup-sh7300.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
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# Primary on-chip clocks (common)
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clock-$(CONFIG_CPU_SH3) := clock-sh3.o
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@ -78,6 +78,9 @@ int __init detect_cpu_and_cache_system(void)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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current_cpu_data.type = CPU_SH7710;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7712)
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current_cpu_data.type = CPU_SH7712;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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current_cpu_data.type = CPU_SH7705;
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@ -2,6 +2,7 @@
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* SH7710 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -19,6 +20,12 @@ static struct plat_sci_port sci_platform_data[] = {
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55, 54 },
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}, {
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.mapbase = 0xa4420000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 56, 57, 59, 58 },
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}, {
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.flags = 0,
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}
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};
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@ -41,3 +48,56 @@ static int __init sh7710_devices_setup(void)
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ARRAY_SIZE(sh7710_devices));
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}
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__initcall(sh7710_devices_setup);
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static struct ipr_data sh7710_ipr_map[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 8, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
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{ 21, 0, 0, 2 }, /* RTC PRI (period) */
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{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
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{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
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{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
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{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
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{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
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{ 52, 4, 8, 3 }, /* SCIF0 ERI */
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{ 53, 4, 8, 3 }, /* SCIF0 RXI */
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{ 54, 4, 8, 3 }, /* SCIF0 BRI */
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{ 55, 4, 8, 3 }, /* SCIF0 TXI */
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{ 56, 4, 4, 3 }, /* SCIF1 ERI */
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{ 57, 4, 4, 3 }, /* SCIF1 RXI */
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{ 58, 4, 4, 3 }, /* SCIF1 BRI */
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{ 59, 4, 4, 3 }, /* SCIF1 TXI */
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{ 76, 5, 8, 7 }, /* DMAC DMTE4 */
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{ 77, 5, 8, 7 }, /* DMAC DMTE5 */
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{ 80, 6, 12, 5 }, /* EDMAC EINT0 */
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{ 81, 6, 8, 5 }, /* EDMAC EINT1 */
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{ 82, 6, 4, 5 }, /* EDMAC EINT2 */
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};
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static unsigned long ipr_offsets[] = {
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0xA414FEE2 /* 0: IPRA */
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, 0xA414FEE4 /* 1: IPRB */
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, 0xA4140016 /* 2: IPRC */
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, 0xA4140018 /* 3: IPRD */
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, 0xA414001A /* 4: IPRE */
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, 0xA4080000 /* 5: IPRF */
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, 0xA4080002 /* 6: IPRG */
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, 0xA4080004 /* 7: IPRH */
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, 0xA4080006 /* 8: IPRI */
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};
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/* given the IPR index return the address of the IPR register */
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unsigned int map_ipridx_to_addr(int idx)
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{
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if (idx >= ARRAY_SIZE(ipr_offsets))
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return 0;
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return ipr_offsets[idx];
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}
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void __init init_IRQ_ipr()
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{
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make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map));
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}
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@ -299,7 +299,8 @@ static void ubc_set_tracing(int asid, unsigned long pc)
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ctrl_outl(0, UBC_BAMRA);
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if (current_cpu_data.type == CPU_SH7729 ||
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current_cpu_data.type == CPU_SH7710) {
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current_cpu_data.type == CPU_SH7710 ||
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current_cpu_data.type == CPU_SH7712 ) {
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ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
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ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
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} else {
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@ -377,6 +377,7 @@ static const char *cpu_name[] = {
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[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
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[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
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[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
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[CPU_SH7712] = "SH7712",
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[CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
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[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
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[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
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@ -101,9 +101,17 @@ config CPU_SUBTYPE_SH7709
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config CPU_SUBTYPE_SH7710
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bool "Support SH7710 processor"
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select CPU_SH3
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select CPU_HAS_IPR_IRQ
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help
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Select SH7710 if you have a SH3-DSP SH7710 CPU.
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config CPU_SUBTYPE_SH7712
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bool "Support SH7712 processor"
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select CPU_SH3
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select CPU_HAS_IPR_IRQ
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help
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Select SH7712 if you have a SH3-DSP SH7712 CPU.
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comment "SH-4 Processor Support"
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config CPU_SUBTYPE_SH7750
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@ -284,12 +284,23 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
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#endif
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#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
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#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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/* SH7300 doesn't use RTS/CTS */
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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{
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sci_out(port, SCFCR, 0);
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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set_sh771x_scif_pfc(port);
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if (cflag & CRTSCTS) {
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fcr_val |= SCFCR_MCE;
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}
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sci_out(port, SCFCR, fcr_val);
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}
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#elif defined(CONFIG_CPU_SH3)
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/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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@ -73,9 +73,13 @@
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# define SCPDR 0xA4050136 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define SCI_NPORTS 2
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define PACR 0xa4050100
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# define PBCR 0xa4050102
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# define SCSCR_INIT(port) 0x3B
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
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# define SCPDR 0xA4050138 /* 16 bit SCIF */
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@ -346,9 +350,15 @@
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}
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#ifdef CONFIG_CPU_SH3
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#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
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sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
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h8_sci_offset, h8_sci_size) \
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CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
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#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
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CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define SCIF_FNS(name, scif_offset, scif_size) \
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CPU_SCIF_FNS(name, scif_offset, scif_size)
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#else
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@ -375,8 +385,8 @@
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710)
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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SCIF_FNS(SCSMR, 0x00, 16)
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SCIF_FNS(SCBRR, 0x04, 8)
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SCIF_FNS(SCSCR, 0x08, 16)
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@ -486,13 +496,24 @@ static inline int sci_rxd_in(struct uart_port *port)
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return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
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return 1;
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static inline int sci_rxd_in(struct uart_port *port)
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{
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if (port->mapbase == SCSPTR0)
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return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
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return 1;
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return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
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}
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static inline void set_sh771x_scif_pfc(struct uart_port *port)
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{
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if (port->mapbase == 0xA4400000){
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ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
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ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
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return;
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}
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if (port->mapbase == 0xA4410000){
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ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
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return;
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}
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH4_202)
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@ -32,6 +32,7 @@
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7712) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710)
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#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
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#else
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@ -44,7 +44,7 @@ enum cpu_type {
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
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CPU_SH7709, CPU_SH7709A, CPU_SH7710,
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CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
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CPU_SH7729, CPU_SH7300,
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/* SH-4 types */
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@ -73,6 +73,7 @@
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#else
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#define IRQ_STNIC 10
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#endif
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#define IRQ_CFCARD 7
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#define __IO_PREFIX se
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#include <asm/io_generic.h>
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