PCI: tegra: Add Tegra 30 PCIe support
Introduce a data structure to parameterize the driver according to SoC generation, add Tegra30 specific code and update the device tree binding document for Tegra30 support. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Jay Agarwal
Stephen Warren
parent
d1523b52bf
commit
94716cddbe
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@ -1,7 +1,7 @@
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NVIDIA Tegra PCIe controller
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Required properties:
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- compatible: "nvidia,tegra20-pcie"
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- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
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- device_type: Must be "pci"
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- reg: A list of physical base address and length for each set of controller
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registers. Must contain an entry for each entry in the reg-names property.
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@ -16,6 +16,7 @@ Required properties:
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"msi": The Tegra interrupt that is asserted when an MSI is received
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- pex-clk-supply: Supply voltage for internal reference clock
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- vdd-supply: Power supply for controller (1.05V)
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- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
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- bus-range: Range of bus numbers associated with this controller
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- #address-cells: Address representation for root ports (must be 3)
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- cell 0 specifies the bus and device numbers of the root port:
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@ -48,6 +49,7 @@ Required properties:
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"afi": The Tegra clock of that name
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"pcie_xclk": The Tegra clock of that name
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"pll_e": The Tegra clock of that name
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"cml": The Tegra clock of that name (not required for Tegra20)
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Root ports are defined as subnodes of the PCIe controller node.
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@ -1,5 +1,5 @@
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/*
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* PCIe host controller driver for TEGRA(2) SOCs
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* PCIe host controller driver for Tegra SoCs
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*
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* Copyright (c) 2010, CompuLab, Ltd.
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* Author: Mike Rapoport <mike@compulab.co.il>
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@ -50,7 +50,6 @@
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#include <asm/mach/pci.h>
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#define INT_PCI_MSI_NR (8 * 32)
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#define TEGRA_MAX_PORTS 2
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/* register definitions */
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@ -142,22 +141,30 @@
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#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
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#define AFI_INTR_EN_AXI_DECERR (1 << 6)
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#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
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#define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
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#define AFI_PCIE_CONFIG 0x0f8
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#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
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#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
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#define AFI_FUSE 0x104
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#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
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#define AFI_PEX0_CTRL 0x110
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#define AFI_PEX1_CTRL 0x118
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#define AFI_PEX2_CTRL 0x128
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#define AFI_PEX_CTRL_RST (1 << 0)
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#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
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#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
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#define AFI_PEXBIAS_CTRL_0 0x168
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#define RP_VEND_XP 0x00000F00
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#define RP_VEND_XP_DL_UP (1 << 30)
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@ -172,7 +179,8 @@
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#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
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#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
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#define PADS_PLL_CTL 0x000000B8
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#define PADS_PLL_CTL_TEGRA20 0x000000B8
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#define PADS_PLL_CTL_TEGRA30 0x000000B4
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#define PADS_PLL_CTL_RST_B4SM (1 << 1)
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#define PADS_PLL_CTL_LOCKDET (1 << 8)
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#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
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@ -182,6 +190,10 @@
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#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
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#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
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#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
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#define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
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#define PADS_REFCLK_CFG0 0x000000C8
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#define PADS_REFCLK_CFG1 0x000000CC
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struct tegra_msi {
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struct msi_chip chip;
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@ -192,6 +204,19 @@ struct tegra_msi {
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int irq;
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};
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/* used to differentiate between Tegra SoC generations */
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struct tegra_pcie_soc_data {
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unsigned int num_ports;
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unsigned int msi_base_shift;
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u32 pads_pll_ctl;
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u32 tx_ref_sel;
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bool has_pex_clkreq_en;
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bool has_pex_bias_ctrl;
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bool has_intr_prsnt_sense;
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bool has_avdd_supply;
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bool has_cml_clk;
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};
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static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip)
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{
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return container_of(chip, struct tegra_msi, chip);
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@ -216,6 +241,7 @@ struct tegra_pcie {
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struct clk *afi_clk;
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struct clk *pcie_xclk;
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struct clk *pll_e;
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struct clk *cml_clk;
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struct tegra_msi msi;
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@ -225,6 +251,9 @@ struct tegra_pcie {
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struct regulator *pex_clk_supply;
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struct regulator *vdd_supply;
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struct regulator *avdd_supply;
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const struct tegra_pcie_soc_data *soc_data;
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};
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struct tegra_pcie_port {
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@ -469,6 +498,10 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
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case 1:
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ret = AFI_PEX1_CTRL;
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break;
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case 2:
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ret = AFI_PEX2_CTRL;
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break;
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}
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return ret;
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@ -493,12 +526,17 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
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static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
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{
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const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
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unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
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unsigned long value;
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/* enable reference clock */
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value = afi_readl(port->pcie, ctrl);
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value |= AFI_PEX_CTRL_REFCLK_EN;
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if (soc->has_pex_clkreq_en)
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value |= AFI_PEX_CTRL_CLKREQ_EN;
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afi_writel(port->pcie, value, ctrl);
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tegra_pcie_port_reset(port);
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@ -551,6 +589,8 @@ static void tegra_pcie_fixup_class(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
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/* Tegra PCIE requires relaxed ordering */
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static void tegra_pcie_relax_enable(struct pci_dev *dev)
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@ -723,10 +763,15 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
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static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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struct tegra_pcie_port *port;
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unsigned int timeout;
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unsigned long value;
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/* power down PCIe slot clock bias pad */
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if (soc->has_pex_bias_ctrl)
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afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
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/* configure mode and disable all ports */
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value = afi_readl(pcie, AFI_PCIE_CONFIG);
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value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
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@ -753,27 +798,26 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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* Set up PHY PLL inputs select PLLE output as refclock,
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* set TX ref sel to div10 (not div5).
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*/
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value = pads_readl(pcie, PADS_PLL_CTL);
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value = pads_readl(pcie, soc->pads_pll_ctl);
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value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
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value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML |
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PADS_PLL_CTL_TXCLKREF_DIV10;
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pads_writel(pcie, value, PADS_PLL_CTL);
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value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
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pads_writel(pcie, value, soc->pads_pll_ctl);
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/* take PLL out of reset */
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value = pads_readl(pcie, PADS_PLL_CTL);
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value = pads_readl(pcie, soc->pads_pll_ctl);
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value |= PADS_PLL_CTL_RST_B4SM;
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pads_writel(pcie, value, PADS_PLL_CTL);
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pads_writel(pcie, value, soc->pads_pll_ctl);
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/*
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* Hack, set the clock voltage to the DEFAULT provided by hw folks.
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* This doesn't exist in the documentation.
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*/
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pads_writel(pcie, 0xfa5cfa5c, 0xc8);
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pads_writel(pcie, 0xfa5cfa5c, PADS_REFCLK_CFG0);
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/* wait for the PLL to lock */
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timeout = 300;
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do {
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value = pads_readl(pcie, PADS_PLL_CTL);
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value = pads_readl(pcie, soc->pads_pll_ctl);
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usleep_range(1000, 2000);
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if (--timeout == 0) {
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pr_err("Tegra PCIe error: timeout waiting for PLL\n");
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@ -802,6 +846,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
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AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
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AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
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if (soc->has_intr_prsnt_sense)
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value |= AFI_INTR_EN_PRSNT_SENSE;
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afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
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afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
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@ -816,6 +864,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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static void tegra_pcie_power_off(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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int err;
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/* TODO: disable and unprepare clocks? */
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@ -826,19 +875,28 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
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tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
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if (soc->has_avdd_supply) {
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err = regulator_disable(pcie->avdd_supply);
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if (err < 0)
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dev_warn(pcie->dev,
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"failed to disable AVDD regulator: %d\n",
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err);
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}
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err = regulator_disable(pcie->pex_clk_supply);
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if (err < 0)
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dev_err(pcie->dev, "failed to disable pex-clk regulator: %d\n",
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err);
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dev_warn(pcie->dev, "failed to disable pex-clk regulator: %d\n",
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err);
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err = regulator_disable(pcie->vdd_supply);
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if (err < 0)
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dev_err(pcie->dev, "failed to disable VDD regulator: %d\n",
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err);
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dev_warn(pcie->dev, "failed to disable VDD regulator: %d\n",
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err);
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}
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static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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int err;
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tegra_periph_reset_assert(pcie->pcie_xclk);
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@ -861,6 +919,16 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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return err;
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}
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if (soc->has_avdd_supply) {
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err = regulator_enable(pcie->avdd_supply);
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if (err < 0) {
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dev_err(pcie->dev,
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"failed to enable AVDD regulator: %d\n",
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err);
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return err;
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}
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}
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
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pcie->pex_clk);
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if (err) {
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@ -876,6 +944,15 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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return err;
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}
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if (soc->has_cml_clk) {
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err = clk_prepare_enable(pcie->cml_clk);
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if (err < 0) {
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dev_err(pcie->dev, "failed to enable CML clock: %d\n",
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err);
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return err;
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}
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}
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err = clk_prepare_enable(pcie->pll_e);
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if (err < 0) {
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dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
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@ -887,6 +964,8 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
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if (IS_ERR(pcie->pex_clk))
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return PTR_ERR(pcie->pex_clk);
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@ -903,6 +982,12 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
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if (IS_ERR(pcie->pll_e))
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return PTR_ERR(pcie->pll_e);
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if (soc->has_cml_clk) {
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pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
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if (IS_ERR(pcie->cml_clk))
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return PTR_ERR(pcie->cml_clk);
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}
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return 0;
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}
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@ -1127,6 +1212,7 @@ static const struct irq_domain_ops msi_domain_ops = {
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static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
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{
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struct platform_device *pdev = to_platform_device(pcie->dev);
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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struct tegra_msi *msi = &pcie->msi;
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unsigned long base;
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int err;
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@ -1164,7 +1250,7 @@ static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
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msi->pages = __get_free_pages(GFP_KERNEL, 0);
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base = virt_to_phys((void *)msi->pages);
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afi_writel(pcie, base, AFI_MSI_FPCI_BAR_ST);
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afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
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afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
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/* this register is in 4K increments */
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afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
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@ -1233,16 +1319,35 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
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{
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struct device_node *np = pcie->dev->of_node;
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switch (lanes) {
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case 0x00000004:
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dev_info(pcie->dev, "single-mode configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
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return 0;
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if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
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switch (lanes) {
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case 0x00000204:
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dev_info(pcie->dev, "4x1, 2x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
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return 0;
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case 0x00000202:
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dev_info(pcie->dev, "dual-mode configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
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return 0;
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case 0x00020202:
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dev_info(pcie->dev, "2x3 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
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return 0;
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case 0x00010104:
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dev_info(pcie->dev, "4x1, 1x2 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
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return 0;
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}
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} else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
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switch (lanes) {
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case 0x00000004:
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dev_info(pcie->dev, "single-mode configuration\n");
|
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
|
||||
return 0;
|
||||
|
||||
case 0x00000202:
|
||||
dev_info(pcie->dev, "dual-mode configuration\n");
|
||||
*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
|
|
@ -1250,6 +1355,7 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
|
|||
|
||||
static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
|
||||
{
|
||||
const struct tegra_pcie_soc_data *soc = pcie->soc_data;
|
||||
struct device_node *np = pcie->dev->of_node, *port;
|
||||
struct of_pci_range_parser parser;
|
||||
struct of_pci_range range;
|
||||
|
|
@ -1270,6 +1376,12 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
|
|||
if (IS_ERR(pcie->pex_clk_supply))
|
||||
return PTR_ERR(pcie->pex_clk_supply);
|
||||
|
||||
if (soc->has_avdd_supply) {
|
||||
pcie->avdd_supply = devm_regulator_get(pcie->dev, "avdd");
|
||||
if (IS_ERR(pcie->avdd_supply))
|
||||
return PTR_ERR(pcie->avdd_supply);
|
||||
}
|
||||
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
of_pci_range_to_resource(&range, np, &res);
|
||||
|
||||
|
|
@ -1316,7 +1428,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
|
|||
|
||||
index = PCI_SLOT(err);
|
||||
|
||||
if (index < 1 || index > TEGRA_MAX_PORTS) {
|
||||
if (index < 1 || index > soc->num_ports) {
|
||||
dev_err(pcie->dev, "invalid port number: %d\n", index);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -1454,17 +1566,54 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_pcie_soc_data tegra20_pcie_data = {
|
||||
.num_ports = 2,
|
||||
.msi_base_shift = 0,
|
||||
.pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
|
||||
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
|
||||
.has_pex_clkreq_en = false,
|
||||
.has_pex_bias_ctrl = false,
|
||||
.has_intr_prsnt_sense = false,
|
||||
.has_avdd_supply = false,
|
||||
.has_cml_clk = false,
|
||||
};
|
||||
|
||||
static const struct tegra_pcie_soc_data tegra30_pcie_data = {
|
||||
.num_ports = 3,
|
||||
.msi_base_shift = 8,
|
||||
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
|
||||
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
|
||||
.has_pex_clkreq_en = true,
|
||||
.has_pex_bias_ctrl = true,
|
||||
.has_intr_prsnt_sense = true,
|
||||
.has_avdd_supply = true,
|
||||
.has_cml_clk = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_pcie_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
|
||||
{ .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
|
||||
|
||||
static int tegra_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct tegra_pcie *pcie;
|
||||
int err;
|
||||
|
||||
match = of_match_device(tegra_pcie_of_match, &pdev->dev);
|
||||
if (!match)
|
||||
return -ENODEV;
|
||||
|
||||
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
|
||||
if (!pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_LIST_HEAD(&pcie->busses);
|
||||
INIT_LIST_HEAD(&pcie->ports);
|
||||
pcie->soc_data = match->data;
|
||||
pcie->dev = &pdev->dev;
|
||||
|
||||
err = tegra_pcie_parse_dt(pcie);
|
||||
|
|
@ -1513,12 +1662,6 @@ put_resources:
|
|||
return err;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra_pcie_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-pcie", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
|
||||
|
||||
static struct platform_driver tegra_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-pcie",
|
||||
|
|
|
|||
Loading…
Reference in a new issue