usb: musb: da8xx: Remove mach code
Use the new phy-da8xx-usb driver to take the place of the mach code that pokes CFGCHIP2 in the da8xx musb glue driver. This unbreaks the driver. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -82,7 +82,7 @@ config USB_MUSB_DA8XX
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tristate "DA8xx/OMAP-L1x"
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depends on ARCH_DAVINCI_DA8XX
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depends on NOP_USB_XCEIV
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depends on BROKEN
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select PHY_DA8XX_USB
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config USB_MUSB_TUSB6010
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tristate "TUSB6010"
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@ -30,13 +30,11 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/usb_phy_generic.h>
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#include <mach/da8xx.h>
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#include <linux/platform_data/usb-davinci.h>
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#include "musb_core.h"
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/*
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@ -80,60 +78,14 @@
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#define DA8XX_MENTOR_CORE_OFFSET 0x400
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#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
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struct da8xx_glue {
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struct device *dev;
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struct platform_device *musb;
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struct platform_device *phy;
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struct platform_device *usb_phy;
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struct clk *clk;
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struct phy *phy;
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};
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/*
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* REVISIT (PM): we should be able to keep the PHY in low power mode most
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* of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
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* and, when in host mode, autosuspending idle root ports... PHY_PLLON
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* (overriding SUSPENDM?) then likely needs to stay off.
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*/
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static inline void phy_on(void)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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/*
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* Start the on-chip PHY and its PLL.
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*/
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cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
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cfgchip2 |= CFGCHIP2_PHY_PLLON;
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__raw_writel(cfgchip2, CFGCHIP2);
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pr_info("Waiting for USB PHY clock good...\n");
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while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
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cpu_relax();
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}
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static inline void phy_off(void)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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/*
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* Ensure that USB 1.1 reference clock is not being sourced from
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* USB 2.0 PHY. Otherwise do not power down the PHY.
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*/
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if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
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(cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
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pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
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"can't power it down\n");
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return;
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}
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/*
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* Power down the on-chip PHY.
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*/
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cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
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__raw_writel(cfgchip2, CFGCHIP2);
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}
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/*
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* Because we don't set CTRL.UINT, it's "important" to:
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* - not read/write INTRUSB/INTRUSBE (except during
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@ -385,29 +337,29 @@ static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
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static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
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{
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u32 cfgchip2 = __raw_readl(CFGCHIP2);
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struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
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enum phy_mode phy_mode;
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cfgchip2 &= ~CFGCHIP2_OTGMODE;
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switch (musb_mode) {
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case MUSB_HOST: /* Force VBUS valid, ID = 0 */
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cfgchip2 |= CFGCHIP2_FORCE_HOST;
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phy_mode = PHY_MODE_USB_HOST;
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break;
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case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
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cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
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phy_mode = PHY_MODE_USB_DEVICE;
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break;
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case MUSB_OTG: /* Don't override the VBUS/ID comparators */
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cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
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phy_mode = PHY_MODE_USB_OTG;
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break;
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default:
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dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
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return -EINVAL;
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}
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__raw_writel(cfgchip2, CFGCHIP2);
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return 0;
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return phy_set_mode(glue->phy, phy_mode);
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}
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static int da8xx_musb_init(struct musb *musb)
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{
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struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
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void __iomem *reg_base = musb->ctrl_base;
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u32 rev;
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int ret = -ENODEV;
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@ -425,32 +377,56 @@ static int da8xx_musb_init(struct musb *musb)
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goto fail;
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}
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ret = clk_prepare_enable(glue->clk);
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if (ret) {
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dev_err(glue->dev, "failed to enable clock\n");
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goto fail;
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}
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setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
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/* Reset the controller */
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musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
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/* Start the on-chip PHY and its PLL. */
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phy_on();
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ret = phy_init(glue->phy);
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if (ret) {
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dev_err(glue->dev, "Failed to init phy.\n");
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goto err_phy_init;
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}
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ret = phy_power_on(glue->phy);
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if (ret) {
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dev_err(glue->dev, "Failed to power on phy.\n");
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goto err_phy_power_on;
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}
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msleep(5);
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/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
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pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
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rev, __raw_readl(CFGCHIP2),
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pr_debug("DA8xx OTG revision %08x, control %02x\n", rev,
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musb_readb(reg_base, DA8XX_USB_CTRL_REG));
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musb->isr = da8xx_musb_interrupt;
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return 0;
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err_phy_power_on:
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phy_exit(glue->phy);
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err_phy_init:
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clk_disable_unprepare(glue->clk);
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fail:
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return ret;
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}
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static int da8xx_musb_exit(struct musb *musb)
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{
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struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
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del_timer_sync(&otg_workaround);
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phy_off();
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phy_power_off(glue->phy);
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phy_exit(glue->phy);
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clk_disable_unprepare(glue->clk);
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usb_put_phy(musb->xceiv);
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@ -502,10 +478,10 @@ static int da8xx_probe(struct platform_device *pdev)
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return PTR_ERR(clk);
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}
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ret = clk_enable(clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable clock\n");
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goto err4;
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glue->phy = devm_phy_get(&pdev->dev, "usb-phy");
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if (IS_ERR(glue->phy)) {
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dev_err(&pdev->dev, "failed to get phy\n");
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return PTR_ERR(glue->phy);
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}
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glue->dev = &pdev->dev;
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@ -513,10 +489,10 @@ static int da8xx_probe(struct platform_device *pdev)
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pdata->platform_ops = &da8xx_ops;
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glue->phy = usb_phy_generic_register();
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if (IS_ERR(glue->phy)) {
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ret = PTR_ERR(glue->phy);
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goto err5;
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glue->usb_phy = usb_phy_generic_register();
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if (IS_ERR(glue->usb_phy)) {
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dev_err(&pdev->dev, "failed to register usb_phy\n");
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return PTR_ERR(glue->usb_phy);
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}
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platform_set_drvdata(pdev, glue);
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glue->musb = musb = platform_device_register_full(&pinfo);
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if (IS_ERR(musb)) {
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ret = PTR_ERR(musb);
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dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
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goto err6;
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usb_phy_generic_unregister(glue->usb_phy);
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return PTR_ERR(musb);
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}
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return 0;
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err6:
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usb_phy_generic_unregister(glue->phy);
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err5:
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clk_disable(clk);
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err4:
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return ret;
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}
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static int da8xx_remove(struct platform_device *pdev)
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struct da8xx_glue *glue = platform_get_drvdata(pdev);
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platform_device_unregister(glue->musb);
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usb_phy_generic_unregister(glue->phy);
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clk_disable(glue->clk);
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usb_phy_generic_unregister(glue->usb_phy);
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return 0;
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}
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