MIPS: perf: Add interAptiv support
Choose event/cache maps and handle raw event mapping for interAptiv. Update code comments. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6528/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -805,7 +805,7 @@ static void reset_counters(void *arg)
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}
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}
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/* 24K/34K/1004K cores can share the same event map. */
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/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
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static const struct mips_perf_event mipsxxcore_event_map
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[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
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@ -849,7 +849,7 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
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};
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/* 24K/34K/1004K cores can share the same cache event map. */
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/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
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static const struct mips_perf_event mipsxxcore_cache_map
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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@ -1400,6 +1400,20 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
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#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
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#endif
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/* interAptiv */
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#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \
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((b) == 0 || (b) == 1 || (b) == 11)
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#ifdef CONFIG_MIPS_MT_SMP
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/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
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#define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \
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((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
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(b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \
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(r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \
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(b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \
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((b) >= 64 && (b) <= 67))
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#define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175)
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#endif
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/* BMIPS5000 */
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#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \
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((b) == 0 || (b) == 1)
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@ -1484,6 +1498,21 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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raw_event.range = V;
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else
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raw_event.range = T;
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#endif
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break;
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case CPU_INTERAPTIV:
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if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
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raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
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else
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raw_event.cntr_mask =
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raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
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#ifdef CONFIG_MIPS_MT_SMP
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if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
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raw_event.range = P;
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else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
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raw_event.range = V;
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else
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raw_event.range = T;
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#endif
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break;
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case CPU_BMIPS5000:
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@ -1614,6 +1643,11 @@ init_hw_perf_events(void)
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mipspmu.general_event_map = &mipsxxcore_event_map;
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mipspmu.cache_event_map = &mipsxxcore_cache_map;
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break;
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case CPU_INTERAPTIV:
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mipspmu.name = "mips/interAptiv";
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mipspmu.general_event_map = &mipsxxcore_event_map;
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mipspmu.cache_event_map = &mipsxxcore_cache_map;
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break;
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case CPU_LOONGSON1:
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mipspmu.name = "mips/loongson1";
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mipspmu.general_event_map = &mipsxxcore_event_map;
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