Merge branch 'drm-kdb-next' into drm-core-next
* drm-kdb-next: drm/nouveau/kms: Avoid a hang entering KDB with VT accel on. radeon, kdb, kms: Save and restore the LUT on atomic KMS enter/exit drm, kdb, kms: Add an enter argument to mode_set_base_atomic() API drm/nouveau/kms: Implement KDB debug hooks for nouveau KMS. drm/radeon/kms: Implement KDB debug hooks for radeon KMS.
This commit is contained in:
commit
96a03fce54
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@ -263,7 +263,8 @@ int drm_fb_helper_debug_enter(struct fb_info *info)
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funcs->mode_set_base_atomic(mode_set->crtc,
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funcs->mode_set_base_atomic(mode_set->crtc,
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mode_set->fb,
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mode_set->fb,
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mode_set->x,
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mode_set->x,
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mode_set->y);
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mode_set->y,
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1);
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}
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}
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}
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}
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@ -309,7 +310,7 @@ int drm_fb_helper_debug_leave(struct fb_info *info)
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}
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}
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funcs->mode_set_base_atomic(mode_set->crtc, fb, crtc->x,
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funcs->mode_set_base_atomic(mode_set->crtc, fb, crtc->x,
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crtc->y);
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crtc->y, 0);
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}
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}
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return 0;
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return 0;
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@ -1492,7 +1492,7 @@ err_unpin:
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/* Assume fb object is pinned & idle & fenced and just update base pointers */
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/* Assume fb object is pinned & idle & fenced and just update base pointers */
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static int
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static int
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intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int x, int y)
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int x, int y, int enter)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -1614,7 +1614,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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atomic_read(&obj_priv->pending_flip) == 0);
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atomic_read(&obj_priv->pending_flip) == 0);
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}
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}
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ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
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ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 0);
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if (ret) {
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if (ret) {
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i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
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i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
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mutex_unlock(&dev->struct_mutex);
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mutex_unlock(&dev->struct_mutex);
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@ -104,6 +104,8 @@ static struct fb_ops nouveau_fbcon_ops = {
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_blank = drm_fb_helper_blank,
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.fb_blank = drm_fb_helper_blank,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_debug_enter = drm_fb_helper_debug_enter,
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.fb_debug_leave = drm_fb_helper_debug_leave,
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};
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};
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static struct fb_ops nv04_fbcon_ops = {
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static struct fb_ops nv04_fbcon_ops = {
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@ -117,6 +119,8 @@ static struct fb_ops nv04_fbcon_ops = {
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_blank = drm_fb_helper_blank,
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.fb_blank = drm_fb_helper_blank,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_debug_enter = drm_fb_helper_debug_enter,
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.fb_debug_leave = drm_fb_helper_debug_leave,
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};
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};
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static struct fb_ops nv50_fbcon_ops = {
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static struct fb_ops nv50_fbcon_ops = {
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@ -130,6 +134,8 @@ static struct fb_ops nv50_fbcon_ops = {
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_blank = drm_fb_helper_blank,
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.fb_blank = drm_fb_helper_blank,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_debug_enter = drm_fb_helper_debug_enter,
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.fb_debug_leave = drm_fb_helper_debug_leave,
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};
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};
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static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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@ -33,6 +33,7 @@
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#include "nouveau_fb.h"
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#include "nouveau_fb.h"
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#include "nouveau_hw.h"
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#include "nouveau_hw.h"
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#include "nvreg.h"
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#include "nvreg.h"
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#include "nouveau_fbcon.h"
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static int
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static int
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nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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@ -769,8 +770,9 @@ nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
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}
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}
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static int
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static int
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nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
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struct drm_framebuffer *old_fb)
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struct drm_framebuffer *passed_fb,
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int x, int y, bool atomic)
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{
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{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->dev;
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@ -781,13 +783,26 @@ nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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int arb_burst, arb_lwm;
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int arb_burst, arb_lwm;
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int ret;
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int ret;
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ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
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/* If atomic, we want to switch to the fb we were passed, so
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if (ret)
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* now we update pointers to do that. (We don't pin; just
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return ret;
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* assume we're already pinned and update the base address.)
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*/
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if (atomic) {
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drm_fb = passed_fb;
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fb = nouveau_framebuffer(passed_fb);
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}
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else {
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/* If not atomic, we can go ahead and pin, and unpin the
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* old fb we were passed.
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*/
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ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
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if (ret)
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return ret;
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if (old_fb) {
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if (passed_fb) {
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struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb);
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struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
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nouveau_bo_unpin(ofb->nvbo);
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nouveau_bo_unpin(ofb->nvbo);
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}
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}
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}
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nv_crtc->fb.offset = fb->nvbo->bo.offset;
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nv_crtc->fb.offset = fb->nvbo->bo.offset;
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@ -835,6 +850,29 @@ nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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return 0;
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return 0;
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}
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}
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static int
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nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
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}
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static int
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nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y, int enter)
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{
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struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
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struct drm_device *dev = dev_priv->dev;
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if (enter)
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nouveau_fbcon_save_disable_accel(dev);
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else
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nouveau_fbcon_restore_accel(dev);
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return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
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}
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static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
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static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
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struct nouveau_bo *dst)
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struct nouveau_bo *dst)
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{
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{
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@ -963,6 +1001,7 @@ static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
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.mode_fixup = nv_crtc_mode_fixup,
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.mode_fixup = nv_crtc_mode_fixup,
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.mode_set = nv_crtc_mode_set,
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.mode_set = nv_crtc_mode_set,
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.mode_set_base = nv04_crtc_mode_set_base,
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.mode_set_base = nv04_crtc_mode_set_base,
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.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
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.load_lut = nv_crtc_gamma_load,
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.load_lut = nv_crtc_gamma_load,
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};
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};
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|
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@ -487,8 +487,9 @@ nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
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}
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}
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static int
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static int
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nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
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nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
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struct drm_framebuffer *old_fb, bool update)
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struct drm_framebuffer *passed_fb,
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int x, int y, bool update, bool atomic)
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{
|
{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct drm_device *dev = nv_crtc->base.dev;
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struct drm_device *dev = nv_crtc->base.dev;
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@ -500,6 +501,28 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
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|
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NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
|
NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
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|
|
||||||
|
/* If atomic, we want to switch to the fb we were passed, so
|
||||||
|
* now we update pointers to do that. (We don't pin; just
|
||||||
|
* assume we're already pinned and update the base address.)
|
||||||
|
*/
|
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|
if (atomic) {
|
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|
drm_fb = passed_fb;
|
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|
fb = nouveau_framebuffer(passed_fb);
|
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|
}
|
||||||
|
else {
|
||||||
|
/* If not atomic, we can go ahead and pin, and unpin the
|
||||||
|
* old fb we were passed.
|
||||||
|
*/
|
||||||
|
ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (passed_fb) {
|
||||||
|
struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
|
||||||
|
nouveau_bo_unpin(ofb->nvbo);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
switch (drm_fb->depth) {
|
switch (drm_fb->depth) {
|
||||||
case 8:
|
case 8:
|
||||||
format = NV50_EVO_CRTC_FB_DEPTH_8;
|
format = NV50_EVO_CRTC_FB_DEPTH_8;
|
||||||
|
@ -522,15 +545,6 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
if (old_fb) {
|
|
||||||
struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb);
|
|
||||||
nouveau_bo_unpin(ofb->nvbo);
|
|
||||||
}
|
|
||||||
|
|
||||||
nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base;
|
nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base;
|
||||||
nv_crtc->fb.tile_flags = fb->nvbo->tile_flags;
|
nv_crtc->fb.tile_flags = fb->nvbo->tile_flags;
|
||||||
nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
|
nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
|
||||||
|
@ -681,14 +695,22 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
||||||
nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
|
nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
|
||||||
nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
|
nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
|
||||||
|
|
||||||
return nv50_crtc_do_mode_set_base(crtc, x, y, old_fb, false);
|
return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false, false);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int
|
static int
|
||||||
nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
struct drm_framebuffer *old_fb)
|
struct drm_framebuffer *old_fb)
|
||||||
{
|
{
|
||||||
return nv50_crtc_do_mode_set_base(crtc, x, y, old_fb, true);
|
return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, true, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int enter)
|
||||||
|
{
|
||||||
|
return nv50_crtc_do_mode_set_base(crtc, fb, x, y, true, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
|
static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
|
||||||
|
@ -698,6 +720,7 @@ static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
|
||||||
.mode_fixup = nv50_crtc_mode_fixup,
|
.mode_fixup = nv50_crtc_mode_fixup,
|
||||||
.mode_set = nv50_crtc_mode_set,
|
.mode_set = nv50_crtc_mode_set,
|
||||||
.mode_set_base = nv50_crtc_mode_set_base,
|
.mode_set_base = nv50_crtc_mode_set_base,
|
||||||
|
.mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
|
||||||
.load_lut = nv50_crtc_lut_load,
|
.load_lut = nv50_crtc_lut_load,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -854,13 +854,15 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
|
||||||
struct drm_framebuffer *old_fb)
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int atomic)
|
||||||
{
|
{
|
||||||
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
||||||
struct drm_device *dev = crtc->dev;
|
struct drm_device *dev = crtc->dev;
|
||||||
struct radeon_device *rdev = dev->dev_private;
|
struct radeon_device *rdev = dev->dev_private;
|
||||||
struct radeon_framebuffer *radeon_fb;
|
struct radeon_framebuffer *radeon_fb;
|
||||||
|
struct drm_framebuffer *target_fb;
|
||||||
struct drm_gem_object *obj;
|
struct drm_gem_object *obj;
|
||||||
struct radeon_bo *rbo;
|
struct radeon_bo *rbo;
|
||||||
uint64_t fb_location;
|
uint64_t fb_location;
|
||||||
|
@ -868,28 +870,43 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
int r;
|
int r;
|
||||||
|
|
||||||
/* no fb bound */
|
/* no fb bound */
|
||||||
if (!crtc->fb) {
|
if (!atomic && !crtc->fb) {
|
||||||
DRM_DEBUG_KMS("No FB bound\n");
|
DRM_DEBUG_KMS("No FB bound\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
radeon_fb = to_radeon_framebuffer(crtc->fb);
|
if (atomic) {
|
||||||
|
radeon_fb = to_radeon_framebuffer(fb);
|
||||||
|
target_fb = fb;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
radeon_fb = to_radeon_framebuffer(crtc->fb);
|
||||||
|
target_fb = crtc->fb;
|
||||||
|
}
|
||||||
|
|
||||||
/* Pin framebuffer & get tilling informations */
|
/* If atomic, assume fb object is pinned & idle & fenced and
|
||||||
|
* just update base pointers
|
||||||
|
*/
|
||||||
obj = radeon_fb->obj;
|
obj = radeon_fb->obj;
|
||||||
rbo = obj->driver_private;
|
rbo = obj->driver_private;
|
||||||
r = radeon_bo_reserve(rbo, false);
|
r = radeon_bo_reserve(rbo, false);
|
||||||
if (unlikely(r != 0))
|
if (unlikely(r != 0))
|
||||||
return r;
|
return r;
|
||||||
r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
|
|
||||||
if (unlikely(r != 0)) {
|
if (atomic)
|
||||||
radeon_bo_unreserve(rbo);
|
fb_location = radeon_bo_gpu_offset(rbo);
|
||||||
return -EINVAL;
|
else {
|
||||||
|
r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
|
||||||
|
if (unlikely(r != 0)) {
|
||||||
|
radeon_bo_unreserve(rbo);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
|
radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
|
||||||
radeon_bo_unreserve(rbo);
|
radeon_bo_unreserve(rbo);
|
||||||
|
|
||||||
switch (crtc->fb->bits_per_pixel) {
|
switch (target_fb->bits_per_pixel) {
|
||||||
case 8:
|
case 8:
|
||||||
fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
|
fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
|
||||||
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
|
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
|
||||||
|
@ -909,7 +926,7 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
DRM_ERROR("Unsupported screen depth %d\n",
|
DRM_ERROR("Unsupported screen depth %d\n",
|
||||||
crtc->fb->bits_per_pixel);
|
target_fb->bits_per_pixel);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -955,10 +972,10 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
|
WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
|
||||||
WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
|
WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
|
||||||
WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
|
WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
|
||||||
WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
|
WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
|
||||||
WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
|
WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
|
||||||
|
|
||||||
fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
|
fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
|
||||||
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
|
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
|
||||||
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
|
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
|
||||||
|
|
||||||
|
@ -977,8 +994,8 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
else
|
else
|
||||||
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
|
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
|
||||||
|
|
||||||
if (old_fb && old_fb != crtc->fb) {
|
if (!atomic && fb && fb != crtc->fb) {
|
||||||
radeon_fb = to_radeon_framebuffer(old_fb);
|
radeon_fb = to_radeon_framebuffer(fb);
|
||||||
rbo = radeon_fb->obj->driver_private;
|
rbo = radeon_fb->obj->driver_private;
|
||||||
r = radeon_bo_reserve(rbo, false);
|
r = radeon_bo_reserve(rbo, false);
|
||||||
if (unlikely(r != 0))
|
if (unlikely(r != 0))
|
||||||
|
@ -993,8 +1010,9 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
|
||||||
struct drm_framebuffer *old_fb)
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int atomic)
|
||||||
{
|
{
|
||||||
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
||||||
struct drm_device *dev = crtc->dev;
|
struct drm_device *dev = crtc->dev;
|
||||||
|
@ -1002,33 +1020,48 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
struct radeon_framebuffer *radeon_fb;
|
struct radeon_framebuffer *radeon_fb;
|
||||||
struct drm_gem_object *obj;
|
struct drm_gem_object *obj;
|
||||||
struct radeon_bo *rbo;
|
struct radeon_bo *rbo;
|
||||||
|
struct drm_framebuffer *target_fb;
|
||||||
uint64_t fb_location;
|
uint64_t fb_location;
|
||||||
uint32_t fb_format, fb_pitch_pixels, tiling_flags;
|
uint32_t fb_format, fb_pitch_pixels, tiling_flags;
|
||||||
int r;
|
int r;
|
||||||
|
|
||||||
/* no fb bound */
|
/* no fb bound */
|
||||||
if (!crtc->fb) {
|
if (!atomic && !crtc->fb) {
|
||||||
DRM_DEBUG_KMS("No FB bound\n");
|
DRM_DEBUG_KMS("No FB bound\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
radeon_fb = to_radeon_framebuffer(crtc->fb);
|
if (atomic) {
|
||||||
|
radeon_fb = to_radeon_framebuffer(fb);
|
||||||
|
target_fb = fb;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
radeon_fb = to_radeon_framebuffer(crtc->fb);
|
||||||
|
target_fb = crtc->fb;
|
||||||
|
}
|
||||||
|
|
||||||
/* Pin framebuffer & get tilling informations */
|
|
||||||
obj = radeon_fb->obj;
|
obj = radeon_fb->obj;
|
||||||
rbo = obj->driver_private;
|
rbo = obj->driver_private;
|
||||||
r = radeon_bo_reserve(rbo, false);
|
r = radeon_bo_reserve(rbo, false);
|
||||||
if (unlikely(r != 0))
|
if (unlikely(r != 0))
|
||||||
return r;
|
return r;
|
||||||
r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
|
|
||||||
if (unlikely(r != 0)) {
|
/* If atomic, assume fb object is pinned & idle & fenced and
|
||||||
radeon_bo_unreserve(rbo);
|
* just update base pointers
|
||||||
return -EINVAL;
|
*/
|
||||||
|
if (atomic)
|
||||||
|
fb_location = radeon_bo_gpu_offset(rbo);
|
||||||
|
else {
|
||||||
|
r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
|
||||||
|
if (unlikely(r != 0)) {
|
||||||
|
radeon_bo_unreserve(rbo);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
|
radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
|
||||||
radeon_bo_unreserve(rbo);
|
radeon_bo_unreserve(rbo);
|
||||||
|
|
||||||
switch (crtc->fb->bits_per_pixel) {
|
switch (target_fb->bits_per_pixel) {
|
||||||
case 8:
|
case 8:
|
||||||
fb_format =
|
fb_format =
|
||||||
AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
|
AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
|
||||||
|
@ -1052,7 +1085,7 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
DRM_ERROR("Unsupported screen depth %d\n",
|
DRM_ERROR("Unsupported screen depth %d\n",
|
||||||
crtc->fb->bits_per_pixel);
|
target_fb->bits_per_pixel);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1093,10 +1126,10 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
|
WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
|
||||||
WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
|
WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
|
||||||
WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
|
WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
|
||||||
WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
|
WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
|
||||||
WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
|
WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
|
||||||
|
|
||||||
fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
|
fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
|
||||||
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
|
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
|
||||||
WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
|
WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
|
||||||
|
|
||||||
|
@ -1115,8 +1148,8 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
else
|
else
|
||||||
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
|
WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
|
||||||
|
|
||||||
if (old_fb && old_fb != crtc->fb) {
|
if (!atomic && fb && fb != crtc->fb) {
|
||||||
radeon_fb = to_radeon_framebuffer(old_fb);
|
radeon_fb = to_radeon_framebuffer(fb);
|
||||||
rbo = radeon_fb->obj->driver_private;
|
rbo = radeon_fb->obj->driver_private;
|
||||||
r = radeon_bo_reserve(rbo, false);
|
r = radeon_bo_reserve(rbo, false);
|
||||||
if (unlikely(r != 0))
|
if (unlikely(r != 0))
|
||||||
|
@ -1138,11 +1171,26 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
struct radeon_device *rdev = dev->dev_private;
|
struct radeon_device *rdev = dev->dev_private;
|
||||||
|
|
||||||
if (ASIC_IS_DCE4(rdev))
|
if (ASIC_IS_DCE4(rdev))
|
||||||
return evergreen_crtc_set_base(crtc, x, y, old_fb);
|
return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
|
||||||
else if (ASIC_IS_AVIVO(rdev))
|
else if (ASIC_IS_AVIVO(rdev))
|
||||||
return avivo_crtc_set_base(crtc, x, y, old_fb);
|
return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
|
||||||
else
|
else
|
||||||
return radeon_crtc_set_base(crtc, x, y, old_fb);
|
return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int enter)
|
||||||
|
{
|
||||||
|
struct drm_device *dev = crtc->dev;
|
||||||
|
struct radeon_device *rdev = dev->dev_private;
|
||||||
|
|
||||||
|
if (ASIC_IS_DCE4(rdev))
|
||||||
|
return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
|
||||||
|
else if (ASIC_IS_AVIVO(rdev))
|
||||||
|
return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
|
||||||
|
else
|
||||||
|
return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* properly set additional regs when using atombios */
|
/* properly set additional regs when using atombios */
|
||||||
|
@ -1311,6 +1359,7 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
|
||||||
.mode_fixup = atombios_crtc_mode_fixup,
|
.mode_fixup = atombios_crtc_mode_fixup,
|
||||||
.mode_set = atombios_crtc_mode_set,
|
.mode_set = atombios_crtc_mode_set,
|
||||||
.mode_set_base = atombios_crtc_set_base,
|
.mode_set_base = atombios_crtc_set_base,
|
||||||
|
.mode_set_base_atomic = atombios_crtc_set_base_atomic,
|
||||||
.prepare = atombios_crtc_prepare,
|
.prepare = atombios_crtc_prepare,
|
||||||
.commit = atombios_crtc_commit,
|
.commit = atombios_crtc_commit,
|
||||||
.load_lut = radeon_crtc_load_lut,
|
.load_lut = radeon_crtc_load_lut,
|
||||||
|
|
|
@ -138,6 +138,38 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
|
||||||
legacy_crtc_load_lut(crtc);
|
legacy_crtc_load_lut(crtc);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void radeon_crtc_save_lut(struct drm_crtc *crtc)
|
||||||
|
{
|
||||||
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (!crtc->enabled)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (i = 0; i < 256; i++) {
|
||||||
|
radeon_crtc->lut_r_copy[i] = radeon_crtc->lut_r[i];
|
||||||
|
radeon_crtc->lut_g_copy[i] = radeon_crtc->lut_g[i];
|
||||||
|
radeon_crtc->lut_b_copy[i] = radeon_crtc->lut_b[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void radeon_crtc_restore_lut(struct drm_crtc *crtc)
|
||||||
|
{
|
||||||
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (!crtc->enabled)
|
||||||
|
return;
|
||||||
|
|
||||||
|
for (i = 0; i < 256; i++) {
|
||||||
|
radeon_crtc->lut_r[i] = radeon_crtc->lut_r_copy[i];
|
||||||
|
radeon_crtc->lut_g[i] = radeon_crtc->lut_g_copy[i];
|
||||||
|
radeon_crtc->lut_b[i] = radeon_crtc->lut_b_copy[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
radeon_crtc_load_lut(crtc);
|
||||||
|
}
|
||||||
|
|
||||||
/** Sets the color ramps on behalf of fbcon */
|
/** Sets the color ramps on behalf of fbcon */
|
||||||
void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
|
void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
|
||||||
u16 blue, int regno)
|
u16 blue, int regno)
|
||||||
|
|
|
@ -59,6 +59,8 @@ static struct fb_ops radeonfb_ops = {
|
||||||
.fb_pan_display = drm_fb_helper_pan_display,
|
.fb_pan_display = drm_fb_helper_pan_display,
|
||||||
.fb_blank = drm_fb_helper_blank,
|
.fb_blank = drm_fb_helper_blank,
|
||||||
.fb_setcmap = drm_fb_helper_setcmap,
|
.fb_setcmap = drm_fb_helper_setcmap,
|
||||||
|
.fb_debug_enter = drm_fb_helper_debug_enter,
|
||||||
|
.fb_debug_leave = drm_fb_helper_debug_leave,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -347,11 +347,31 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
|
||||||
|
|
||||||
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
struct drm_framebuffer *old_fb)
|
struct drm_framebuffer *old_fb)
|
||||||
|
{
|
||||||
|
return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int enter)
|
||||||
|
{
|
||||||
|
if (enter)
|
||||||
|
radeon_crtc_save_lut(crtc);
|
||||||
|
else
|
||||||
|
radeon_crtc_restore_lut(crtc);
|
||||||
|
|
||||||
|
return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int radeon_crtc_do_set_base(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int atomic)
|
||||||
{
|
{
|
||||||
struct drm_device *dev = crtc->dev;
|
struct drm_device *dev = crtc->dev;
|
||||||
struct radeon_device *rdev = dev->dev_private;
|
struct radeon_device *rdev = dev->dev_private;
|
||||||
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
||||||
struct radeon_framebuffer *radeon_fb;
|
struct radeon_framebuffer *radeon_fb;
|
||||||
|
struct drm_framebuffer *target_fb;
|
||||||
struct drm_gem_object *obj;
|
struct drm_gem_object *obj;
|
||||||
struct radeon_bo *rbo;
|
struct radeon_bo *rbo;
|
||||||
uint64_t base;
|
uint64_t base;
|
||||||
|
@ -364,14 +384,21 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
|
|
||||||
DRM_DEBUG_KMS("\n");
|
DRM_DEBUG_KMS("\n");
|
||||||
/* no fb bound */
|
/* no fb bound */
|
||||||
if (!crtc->fb) {
|
if (!atomic && !crtc->fb) {
|
||||||
DRM_DEBUG_KMS("No FB bound\n");
|
DRM_DEBUG_KMS("No FB bound\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
radeon_fb = to_radeon_framebuffer(crtc->fb);
|
if (atomic) {
|
||||||
|
radeon_fb = to_radeon_framebuffer(fb);
|
||||||
|
target_fb = fb;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
radeon_fb = to_radeon_framebuffer(crtc->fb);
|
||||||
|
target_fb = crtc->fb;
|
||||||
|
}
|
||||||
|
|
||||||
switch (crtc->fb->bits_per_pixel) {
|
switch (target_fb->bits_per_pixel) {
|
||||||
case 8:
|
case 8:
|
||||||
format = 2;
|
format = 2;
|
||||||
break;
|
break;
|
||||||
|
@ -415,10 +442,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
|
|
||||||
crtc_offset_cntl = 0;
|
crtc_offset_cntl = 0;
|
||||||
|
|
||||||
pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
|
pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
|
||||||
crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
|
crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) +
|
||||||
((crtc->fb->bits_per_pixel * 8) - 1)) /
|
((target_fb->bits_per_pixel * 8) - 1)) /
|
||||||
(crtc->fb->bits_per_pixel * 8));
|
(target_fb->bits_per_pixel * 8));
|
||||||
crtc_pitch |= crtc_pitch << 16;
|
crtc_pitch |= crtc_pitch << 16;
|
||||||
|
|
||||||
|
|
||||||
|
@ -443,14 +470,14 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
crtc_tile_x0_y0 = x | (y << 16);
|
crtc_tile_x0_y0 = x | (y << 16);
|
||||||
base &= ~0x7ff;
|
base &= ~0x7ff;
|
||||||
} else {
|
} else {
|
||||||
int byteshift = crtc->fb->bits_per_pixel >> 4;
|
int byteshift = target_fb->bits_per_pixel >> 4;
|
||||||
int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
|
int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
|
||||||
base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
|
base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
|
||||||
crtc_offset_cntl |= (y % 16);
|
crtc_offset_cntl |= (y % 16);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
int offset = y * pitch_pixels + x;
|
int offset = y * pitch_pixels + x;
|
||||||
switch (crtc->fb->bits_per_pixel) {
|
switch (target_fb->bits_per_pixel) {
|
||||||
case 8:
|
case 8:
|
||||||
offset *= 1;
|
offset *= 1;
|
||||||
break;
|
break;
|
||||||
|
@ -496,8 +523,8 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
|
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
|
||||||
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
|
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
|
||||||
|
|
||||||
if (old_fb && old_fb != crtc->fb) {
|
if (!atomic && fb && fb != crtc->fb) {
|
||||||
radeon_fb = to_radeon_framebuffer(old_fb);
|
radeon_fb = to_radeon_framebuffer(fb);
|
||||||
rbo = radeon_fb->obj->driver_private;
|
rbo = radeon_fb->obj->driver_private;
|
||||||
r = radeon_bo_reserve(rbo, false);
|
r = radeon_bo_reserve(rbo, false);
|
||||||
if (unlikely(r != 0))
|
if (unlikely(r != 0))
|
||||||
|
@ -1040,6 +1067,7 @@ static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
|
||||||
.mode_fixup = radeon_crtc_mode_fixup,
|
.mode_fixup = radeon_crtc_mode_fixup,
|
||||||
.mode_set = radeon_crtc_mode_set,
|
.mode_set = radeon_crtc_mode_set,
|
||||||
.mode_set_base = radeon_crtc_set_base,
|
.mode_set_base = radeon_crtc_set_base,
|
||||||
|
.mode_set_base_atomic = radeon_crtc_set_base_atomic,
|
||||||
.prepare = radeon_crtc_prepare,
|
.prepare = radeon_crtc_prepare,
|
||||||
.commit = radeon_crtc_commit,
|
.commit = radeon_crtc_commit,
|
||||||
.load_lut = radeon_crtc_load_lut,
|
.load_lut = radeon_crtc_load_lut,
|
||||||
|
|
|
@ -267,6 +267,7 @@ struct radeon_crtc {
|
||||||
struct drm_crtc base;
|
struct drm_crtc base;
|
||||||
int crtc_id;
|
int crtc_id;
|
||||||
u16 lut_r[256], lut_g[256], lut_b[256];
|
u16 lut_r[256], lut_g[256], lut_b[256];
|
||||||
|
u16 lut_r_copy[256], lut_g_copy[256], lut_b_copy[256];
|
||||||
bool enabled;
|
bool enabled;
|
||||||
bool can_tile;
|
bool can_tile;
|
||||||
uint32_t crtc_offset;
|
uint32_t crtc_offset;
|
||||||
|
@ -512,8 +513,13 @@ extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
|
||||||
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
|
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
|
||||||
|
|
||||||
extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
|
extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
|
||||||
|
extern void radeon_crtc_save_lut(struct drm_crtc *crtc);
|
||||||
|
extern void radeon_crtc_restore_lut(struct drm_crtc *crtc);
|
||||||
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
struct drm_framebuffer *old_fb);
|
struct drm_framebuffer *old_fb);
|
||||||
|
extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int enter);
|
||||||
extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
|
extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
|
||||||
struct drm_display_mode *mode,
|
struct drm_display_mode *mode,
|
||||||
struct drm_display_mode *adjusted_mode,
|
struct drm_display_mode *adjusted_mode,
|
||||||
|
@ -523,7 +529,12 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
|
||||||
|
|
||||||
extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
|
||||||
struct drm_framebuffer *old_fb);
|
struct drm_framebuffer *old_fb);
|
||||||
|
extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int enter);
|
||||||
|
extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
|
||||||
|
struct drm_framebuffer *fb,
|
||||||
|
int x, int y, int atomic);
|
||||||
extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
|
extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
|
||||||
struct drm_file *file_priv,
|
struct drm_file *file_priv,
|
||||||
uint32_t handle,
|
uint32_t handle,
|
||||||
|
|
|
@ -61,7 +61,8 @@ struct drm_crtc_helper_funcs {
|
||||||
int (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
|
int (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
|
||||||
struct drm_framebuffer *old_fb);
|
struct drm_framebuffer *old_fb);
|
||||||
int (*mode_set_base_atomic)(struct drm_crtc *crtc,
|
int (*mode_set_base_atomic)(struct drm_crtc *crtc,
|
||||||
struct drm_framebuffer *fb, int x, int y);
|
struct drm_framebuffer *fb, int x, int y,
|
||||||
|
int is_enter);
|
||||||
|
|
||||||
/* reload the current crtc LUT */
|
/* reload the current crtc LUT */
|
||||||
void (*load_lut)(struct drm_crtc *crtc);
|
void (*load_lut)(struct drm_crtc *crtc);
|
||||||
|
|
Loading…
Reference in a new issue