ARM: davinci: move davinci_clk_init() to init_time
This moves the call of davinci_clk_init() from map_io to init_time for all boards. This is the proper place to init clocks. This is also done in preparation for moving to the common clock framework. dm646x is a special case because we need to handle different ref_clk rates depending on which board is being used. The clock init in this case is modified to set the rate before registering the clocks instead of using davinci_set_refclk_rate() to recalculate the entire clock tree after all of the clocks are registered. Also, the cpu_clks field is removed from struct davinci_soc_info since it is no longer needed. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
parent
4b785cc55e
commit
96c081735d
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@ -634,7 +634,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
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.atag_offset = 0x100,
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.map_io = da830_evm_map_io,
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.init_irq = cp_intc_init,
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.init_time = davinci_timer_init,
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.init_time = da830_init_time,
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.init_machine = da830_evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -1477,7 +1477,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
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.atag_offset = 0x100,
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.map_io = da850_evm_map_io,
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.init_irq = cp_intc_init,
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.init_time = davinci_timer_init,
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.init_time = da850_init_time,
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.init_machine = da850_evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -427,7 +427,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
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.atag_offset = 0x100,
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.map_io = dm355_evm_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm355_init_time,
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.init_machine = dm355_evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -271,7 +271,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
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.atag_offset = 0x100,
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.map_io = dm355_leopard_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm355_init_time,
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.init_machine = dm355_leopard_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -774,7 +774,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
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.atag_offset = 0x100,
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.map_io = dm365_evm_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm365_init_time,
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.init_machine = dm365_evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -828,7 +828,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
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.atag_offset = 0x100,
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.map_io = davinci_evm_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm644x_init_time,
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.init_machine = davinci_evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -44,10 +44,8 @@
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/serial.h>
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#include <mach/clock.h>
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#include "davinci.h"
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#include "clock.h"
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#define NAND_BLOCK_SIZE SZ_128K
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@ -716,14 +714,23 @@ static void __init evm_init_i2c(void)
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}
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#endif
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#define DM646X_REF_FREQ 27000000
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#define DM646X_AUX_FREQ 24000000
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#define DM6467T_EVM_REF_FREQ 33000000
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static void __init davinci_map_io(void)
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{
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dm646x_init();
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}
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if (machine_is_davinci_dm6467tevm())
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davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
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static void __init dm646x_evm_init_time(void)
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{
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dm646x_init_time(DM646X_REF_FREQ, DM646X_AUX_FREQ);
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}
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static void __init dm6467t_evm_init_time(void)
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{
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dm646x_init_time(DM6467T_EVM_REF_FREQ, DM646X_AUX_FREQ);
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}
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#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
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@ -797,7 +804,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
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.atag_offset = 0x100,
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.map_io = davinci_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm646x_evm_init_time,
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.init_machine = evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -807,7 +814,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
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.atag_offset = 0x100,
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.map_io = davinci_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm6467t_evm_init_time,
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.init_machine = evm_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -566,7 +566,7 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
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.atag_offset = 0x100,
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.map_io = mityomapl138_map_io,
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.init_irq = cp_intc_init,
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.init_time = davinci_timer_init,
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.init_time = da850_init_time,
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.init_machine = mityomapl138_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -227,7 +227,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
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.atag_offset = 0x100,
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.map_io = davinci_ntosd2_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm644x_init_time,
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.init_machine = davinci_ntosd2_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -330,7 +330,7 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
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.atag_offset = 0x100,
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.map_io = omapl138_hawk_map_io,
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.init_irq = cp_intc_init,
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.init_time = davinci_timer_init,
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.init_time = da850_init_time,
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.init_machine = omapl138_hawk_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -150,7 +150,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
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.atag_offset = 0x100,
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.map_io = davinci_sffsdr_map_io,
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.init_irq = davinci_irq_init,
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.init_time = davinci_timer_init,
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.init_time = dm644x_init_time,
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.init_machine = davinci_sffsdr_init,
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.init_late = davinci_init_late,
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.dma_zone_size = SZ_128M,
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@ -1200,7 +1200,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
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.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
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.ids = da830_ids,
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.ids_num = ARRAY_SIZE(da830_ids),
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.cpu_clks = da830_clks,
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.psc_bases = da830_psc_bases,
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.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
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.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
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@ -1220,6 +1219,10 @@ void __init da830_init(void)
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da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
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WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
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davinci_clk_init(davinci_soc_info_da830.cpu_clks);
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}
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void __init da830_init_time(void)
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{
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davinci_clk_init(da830_clks);
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davinci_timer_init();
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}
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@ -1353,7 +1353,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
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.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
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.ids = da850_ids,
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.ids_num = ARRAY_SIZE(da850_ids),
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.cpu_clks = da850_clks,
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.psc_bases = da850_psc_bases,
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.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
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.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
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@ -1392,6 +1391,10 @@ void __init da850_init(void)
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v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
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v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
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__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
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davinci_clk_init(davinci_soc_info_da850.cpu_clks);
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}
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void __init da850_init_time(void)
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{
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davinci_clk_init(da850_clks);
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davinci_timer_init();
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}
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@ -96,7 +96,7 @@ static const char *const da850_boards_compat[] __initconst = {
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DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
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.map_io = da850_init,
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.init_time = davinci_timer_init,
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.init_time = da850_init_time,
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.init_machine = da850_init_machine,
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.dt_compat = da850_boards_compat,
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.init_late = davinci_init_late,
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@ -83,6 +83,7 @@ int davinci_init_wdt(void);
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/* DM355 function declarations */
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void dm355_init(void);
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void dm355_init_time(void);
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void dm355_init_spi0(unsigned chipselect_mask,
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const struct spi_board_info *info, unsigned len);
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void dm355_init_asp1(u32 evt_enable);
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@ -91,6 +92,7 @@ int dm355_gpio_register(void);
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/* DM365 function declarations */
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void dm365_init(void);
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void dm365_init_time(void);
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void dm365_init_asp(void);
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void dm365_init_vc(void);
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void dm365_init_ks(struct davinci_ks_platform_data *pdata);
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@ -102,12 +104,14 @@ int dm365_gpio_register(void);
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/* DM644x function declarations */
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void dm644x_init(void);
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void dm644x_init_time(void);
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void dm644x_init_asp(void);
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int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
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int dm644x_gpio_register(void);
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/* DM646x function declarations */
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void dm646x_init(void);
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void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
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void dm646x_init_mcasp0(struct snd_platform_data *pdata);
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void dm646x_init_mcasp1(struct snd_platform_data *pdata);
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int dm646x_init_edma(struct edma_rsv_info *rsv);
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@ -1012,7 +1012,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
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.jtag_id_reg = 0x01c40028,
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.ids = dm355_ids,
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.ids_num = ARRAY_SIZE(dm355_ids),
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.cpu_clks = dm355_clks,
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.psc_bases = dm355_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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@ -1043,7 +1042,12 @@ void __init dm355_init(void)
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{
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davinci_common_init(&davinci_soc_info_dm355);
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davinci_map_sysmod();
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davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
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}
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void __init dm355_init_time(void)
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{
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davinci_clk_init(dm355_clks);
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davinci_timer_init();
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}
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int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
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@ -1116,7 +1116,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
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.jtag_id_reg = 0x01c40028,
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.ids = dm365_ids,
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.ids_num = ARRAY_SIZE(dm365_ids),
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.cpu_clks = dm365_clks,
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.psc_bases = dm365_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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@ -1168,7 +1167,12 @@ void __init dm365_init(void)
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{
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davinci_common_init(&davinci_soc_info_dm365);
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davinci_map_sysmod();
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davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
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}
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void __init dm365_init_time(void)
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{
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davinci_clk_init(dm365_clks);
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davinci_timer_init();
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}
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static struct resource dm365_vpss_resources[] = {
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@ -905,7 +905,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
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.jtag_id_reg = 0x01c40028,
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.ids = dm644x_ids,
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.ids_num = ARRAY_SIZE(dm644x_ids),
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.cpu_clks = dm644x_clks,
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.psc_bases = dm644x_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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@ -931,7 +930,12 @@ void __init dm644x_init(void)
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{
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davinci_common_init(&davinci_soc_info_dm644x);
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davinci_map_sysmod();
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davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
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}
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void __init dm644x_init_time(void)
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{
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davinci_clk_init(dm644x_clks);
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davinci_timer_init();
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}
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int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
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@ -39,12 +39,6 @@
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#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
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BIT_MASK(8))
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/*
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* Device specific clocks
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*/
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#define DM646X_REF_FREQ 27000000
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#define DM646X_AUX_FREQ 24000000
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#define DM646X_EMAC_BASE 0x01c80000
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#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
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#define DM646X_EMAC_CNTRL_OFFSET 0x0000
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@ -64,13 +58,12 @@ static struct pll_data pll2_data = {
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static struct clk ref_clk = {
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.name = "ref_clk",
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.rate = DM646X_REF_FREQ,
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.set_rate = davinci_simple_set_rate,
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/* rate is initialized in dm646x_init_time() */
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};
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static struct clk aux_clkin = {
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.name = "aux_clkin",
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.rate = DM646X_AUX_FREQ,
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/* rate is initialized in dm646x_init_time() */
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};
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static struct clk pll1_clk = {
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@ -888,7 +881,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
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.jtag_id_reg = 0x01c40028,
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.ids = dm646x_ids,
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.ids_num = ARRAY_SIZE(dm646x_ids),
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.cpu_clks = dm646x_clks,
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.psc_bases = dm646x_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
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.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
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@ -956,7 +948,15 @@ void __init dm646x_init(void)
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{
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davinci_common_init(&davinci_soc_info_dm646x);
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davinci_map_sysmod();
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davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
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}
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void __init dm646x_init_time(unsigned long ref_clk_rate,
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unsigned long aux_clkin_rate)
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{
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ref_clk.rate = ref_clk_rate;
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aux_clkin.rate = aux_clkin_rate;
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davinci_clk_init(dm646x_clks);
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davinci_timer_init();
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}
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static int __init dm646x_init_devices(void)
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@ -53,7 +53,6 @@ struct davinci_soc_info {
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u32 jtag_id_reg;
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struct davinci_id *ids;
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unsigned long ids_num;
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struct clk_lookup *cpu_clks;
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u32 *psc_bases;
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unsigned long psc_bases_num;
|
||||
u32 pinmux_base;
|
||||
|
|
|
@ -88,7 +88,10 @@ extern unsigned int da850_max_speed;
|
|||
#define DA8XX_ARM_RAM_BASE 0xffff0000
|
||||
|
||||
void da830_init(void);
|
||||
void da830_init_time(void);
|
||||
|
||||
void da850_init(void);
|
||||
void da850_init_time(void);
|
||||
|
||||
int da830_register_edma(struct edma_rsv_info *rsv);
|
||||
int da850_register_edma(struct edma_rsv_info *rsv[2]);
|
||||
|
|
Loading…
Reference in a new issue