From 971ccd302d31e40d2ccdbfbc59735bef14a9fc40 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Thu, 12 Apr 2018 11:07:15 +0800
Subject: [PATCH] MLK-18267-5: dts: Add hdmi rx property to imx8qm dts

Add hdmi rx property to imx8qm dts.
Update hdmi rx power domain.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
 .../boot/dts/freescale/fsl-imx8qm-device.dtsi | 51 ++++++++++++++++++-
 .../dts/freescale/fsl-imx8qm-mek-hdmi.dts     | 41 +++++++++++++++
 2 files changed, 90 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index 2d7e86213821..a42a819c075b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -1202,10 +1202,24 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C {
-					reg = <SC_R_HDMI_RX_I2C_0>;
+				pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS {
+					reg = <SC_R_HDMI_RX_BYPASS>;
 					#power-domain-cells = <0>;
 					power-domains =<&pd_hdmi_rx>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C {
+						reg = <SC_R_HDMI_RX_I2C_0>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_hdmi_rx_bypass>;
+					};
+
+					pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM {
+						reg = <SC_R_HDMI_RX_PWM_0>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_hdmi_rx_bypass>;
+					};
 				};
 			};
 
@@ -2482,6 +2496,27 @@
 			status = "disabled";
 		};
 
+		hdmi_rx: hdmi_rx@58268000 {
+			compatible = "fsl,imx-hdmi-rx";
+			reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */
+					<0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR  */
+			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&irqsteer_hdmi_rx>;
+			clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>,
+						<&clk IMX8QM_HDMI_RX_HD_CORE_CLK>,
+						<&clk IMX8QM_HDMI_RX_PXL_CLK>,
+						<&clk IMX8QM_HDMI_RX_SINK_PCLK>,
+						<&clk IMX8QM_HDMI_RX_SINK_SCLK>,
+						<&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>,
+						<&clk IMX8QM_HDMI_RX_SPDIF_CLK>,
+						<&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>;
+			clock-names = "ref_clk", "core_clk", "pxl_clk",
+							"pclk", "sclk", "enc_clk", "spdif_clk",
+							"pxl_link_clk";
+			power-domains = <&pd_hdmi_rx_bypass>;
+			status = "disabled";
+		};
+
 		jpegdec: jpegdec@58400000 {
 			compatible = "fsl,imx8-jpgdec";
 			reg = <0x0 0x58400000 0x0 0x00040020 >;
@@ -2622,6 +2657,18 @@
 		power-domains = <&pd_hdmi>;
 	};
 
+	irqsteer_hdmi_rx: irqsteer@58260000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x58260000 0x0 0x1000>;
+		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_hdmi_rx>;
+	};
+
+
 	i2c0_hdmi: i2c@56266000 {
 		compatible = "fsl,imx8qm-lpi2c";
 		reg = <0x0 0x56266000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
index 8298728a4823..08a3c3043b83 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
@@ -100,3 +100,44 @@
 	assigned-clock-rates = <786432000>, <49152000>, <12288000>;
 	status = "okay";
 };
+
+/* HDMI RX */
+&isi_0 {
+	status = "disabled";
+};
+
+&isi_1 {
+	interface = <4 0 2>;  /* <Input MIPI_VCx Output>
+						Input:  0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
+						VCx:    0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
+						Output: 0-DC0, 1-DC1, 2-MEM */
+	status = "okay";
+};
+
+&isi_2 {
+	status = "okay";
+	fsl,chain_buf;
+};
+
+&isi_3 {
+	status = "disabled";
+};
+
+
+&mipi_csi_0 {
+	status = "disabled";
+};
+
+&i2c0_mipi_csi0 {
+	status = "disabled";
+};
+
+&hdmi_rx {
+	assigned-clocks = <&clk IMX8QM_HDMI_RX_HD_REF_SEL>,
+						<&clk IMX8QM_HDMI_RX_PXL_SEL>,
+						<&clk IMX8QM_HDMI_RX_HD_REF_DIV>;
+	assigned-clock-parents = <&clk IMX8QM_HDMI_RX_DIG_PLL_CLK>,
+							<&clk IMX8QM_HDMI_RX_BYPASS_CLK>;
+	assigned-clock-rates = <0>, <0>, <400000000>;
+	status = "okay";
+};