drm/i915/glk: Program pipe gamma and degamma tables
The gamma tables in Geminilake were changed. There is no split-gamma mode. Instead, there is a dedicated degamma table that is enabled whenever pipe CSC is enabled. The dedicated gamma table has 16 bit precision but doesn't support separate channels. Since that doesn't match the per-channel format of the degamma LUT property, for now only a linear table is loaded and the property ignored. v2: Remove empty line. (Ville) Reuse broadwell code. (Ville) v3: Don't write PIPE_CSC_MODE. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170127090230.20302-1-ander.conselvan.de.oliveira@intel.com
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@ -403,6 +403,7 @@ static const struct intel_device_info intel_geminilake_info = {
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.platform = INTEL_GEMINILAKE,
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.is_alpha_support = 1,
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.ddb_size = 1024,
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.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
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};
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static const struct intel_device_info intel_kabylake_info = {
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@ -8176,12 +8176,26 @@ enum {
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#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
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#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
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#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
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#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
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#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
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#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
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#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
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#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
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#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
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#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
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#define _PRE_CSC_GAMC_INDEX_A 0x4A484
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#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
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#define _PRE_CSC_GAMC_INDEX_C 0x4B484
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#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
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#define _PRE_CSC_GAMC_DATA_A 0x4A488
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#define _PRE_CSC_GAMC_DATA_B 0x4AC88
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#define _PRE_CSC_GAMC_DATA_C 0x4B488
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#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
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#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
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/* pipe CSC & degamma/gamma LUTs on CHV */
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#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
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#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
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@ -380,7 +380,9 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
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WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
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I915_WRITE(PREC_PAL_INDEX(pipe),
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PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT | offset);
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(offset ? PAL_PREC_SPLIT_MODE : 0) |
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PAL_PREC_AUTO_INCREMENT |
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offset);
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if (state->gamma_lut) {
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struct drm_color_lut *lut =
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@ -443,6 +445,57 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
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I915_WRITE(PREC_PAL_INDEX(pipe), 0);
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}
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static void glk_load_degamma_lut(struct drm_crtc_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
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enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
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const uint32_t lut_size = 33;
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uint32_t i;
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/*
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* When setting the auto-increment bit, the hardware seems to
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* ignore the index bits, so we need to reset it to index 0
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* separately.
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*/
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I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
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I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
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/*
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* FIXME: The pipe degamma table in geminilake doesn't support
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* different values per channel, so this just loads a linear table.
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*/
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for (i = 0; i < lut_size; i++) {
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uint32_t v = (i * ((1 << 16) - 1)) / (lut_size - 1);
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I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
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}
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/* Clamp values > 1.0. */
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while (i++ < 35)
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I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16) - 1);
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}
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static void glk_load_luts(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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if (crtc_state_is_legacy(state)) {
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haswell_load_luts(state);
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return;
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}
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glk_load_degamma_lut(state);
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bdw_load_gamma_lut(state, 0);
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intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
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I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
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POSTING_READ(GAMMA_MODE(pipe));
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}
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/* Loads the palette/gamma unit for the CRTC on CherryView. */
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static void cherryview_load_luts(struct drm_crtc_state *state)
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{
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@ -561,6 +614,9 @@ void intel_color_init(struct drm_crtc *crtc)
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IS_BROXTON(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = broadwell_load_luts;
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} else if (IS_GEMINILAKE(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = glk_load_luts;
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} else {
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dev_priv->display.load_luts = i9xx_load_luts;
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}
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