diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts
index 1248d2138eb0..2b3046b78bd0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts
@@ -74,6 +74,9 @@
 				SC_R_SDHC_0
 				SC_R_USB_0
 				SC_R_USB_0_PHY
+				SC_R_UART_1
+				SC_R_DMA_0_CH14
+				SC_R_DMA_0_CH15
 				SC_R_MU_2A
 				>;
 			pads = <
@@ -92,6 +95,12 @@
 				SC_P_EMMC0_RESET_B
 				/* usb otg */
 				SC_P_USB_SS3_TC0
+				/* uart1 */
+				SC_P_UART1_RX
+				SC_P_UART1_TX
+				SC_P_UART1_CTS_B
+				SC_P_UART1_RTS_B
+				SC_P_QSPI1A_DQS
 				>;
 		};
 	};
@@ -132,6 +141,10 @@
 	xen,passthrough;
 };
 
+&lpuart1 {
+	xen,passthrough;
+};
+
 &lpuart1_lpcg {
 	xen,passthrough;
 };
@@ -144,15 +157,23 @@
 	xen,passthrough;
 };
 
+&edma01 {
+	#stream-id-cells = <1>;
+	xen,passthrough;
+	fsl,sc_rsrc_id = <SC_R_DMA_0_CH14>,
+			 <SC_R_DMA_0_CH15>;
+};
+
 /* SMMU */
 &smmu {
 	mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>,
-		      <&usdhc1 0x12>, <&usbotg1 0x11>;
+		      <&usdhc1 0x12>, <&usbotg1 0x11>,
+		      <&edma01 0x10>;
 };
 
 /* DC0 */
 &pd_dc1 {
-	xen,passthrogh;
+	xen,passthrough;
 };
 
 &lvds_region2 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts
index 988507f725e7..852ab8eaba03 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts
@@ -36,6 +36,7 @@
 		mmc0 = &usdhc1;
 		dpu1 = &dpu2;
 		ldb1 = &ldb2;
+		serial1 = &lpuart1;
 	};
 
 	passthrough {
@@ -68,6 +69,17 @@
 			reg = <0x1 0x5b270000 0x0 0x10000>;
 		};
 
+		edma01: dma-controller1@5a1f0000 {
+			compatible = "fsl,imx8qm-edma";
+			reg = <0x1 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
+			      <0x1 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
+			#dma-cells = <3>;
+			dma-channels = <2>;
+			interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx";
+			status = "okay";
+		};
 	};
 };
 
@@ -275,7 +287,16 @@
 /delete-node/ &i2c0_mipi_csi1;
 /delete-node/ &lpspi0;
 /delete-node/ &lpuart0;
-/delete-node/ &lpuart1;
+
+&lpuart1 {
+	/delete-property/ interrupt-parent;
+	reg = <0x1 0x5a070000 0 0x1000>;
+	dmas = <&edma01 15 0 0>, <&edma01 14 0 1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
 /delete-node/ &lpuart2;
 /delete-node/ &lpuart3;
 /delete-node/ &lpuart4;
@@ -455,8 +476,15 @@
 			>;
 		};
 
-
-
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
+				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
+				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
+				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
+				SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22		0x00000021
+			>;
+		};
 	};
 };
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
index 939914916178..64ee1cd8fa7c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
@@ -20,6 +20,66 @@
 
 	/delete-node/ wu;
 
+	edma00: dma-controller0@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
+		      <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx";
+		status = "okay";
+	};
+
+	edma01: dma-controller1@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
+		      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx";
+		status = "okay";
+	};
+
+	edma02: dma-controller2@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
+		      <0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx";
+		status = "okay";
+	};
+
+	edma03: dma-controller3@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
+		      <0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx";
+		status = "okay";
+	};
+
+	edma04: dma-controller4@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
+		      <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
+		#dma-cells = <3>;
+		dma-channels = <2>;
+		interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx";
+		status = "okay";
+	};
+
 	usbotg1_lpcg: usbotg1_lpcg@5b270000 {
 		compatible = "fsl,imx8qm-usbotg1-lpcg";
 		reg = <0x0 0x5b270000 0x0 0x10000>;
@@ -56,6 +116,8 @@
 	};
 };
 
+/delete-node/ &edma0;
+
 &mu {
 	interrupt-parent = <&gic>;
 };
@@ -66,18 +128,22 @@
 
 &lpuart1 {
 	interrupt-parent = <&gic>;
+	dmas = <&edma01 15 0 0>, <&edma01 14 0 1>;
 };
 
 &lpuart2 {
 	interrupt-parent = <&gic>;
+	dmas = <&edma02 17 0 0>, <&edma02 16 0 1>;
 };
 
 &lpuart3 {
 	interrupt-parent = <&gic>;
+	dmas = <&edma03 19 0 0>, <&edma03 18 0 1>;
 };
 
 &lpuart4 {
 	interrupt-parent = <&gic>;
+	dmas = <&edma04 21 0 0>, <&edma04 20 0 1>;
 };
 
 &usdhc1 {