PCI updates for v4.4:
MSI Only use the generic MSI layer when domain is hierarchical (Marc Zyngier) Altera host bridge driver Fix loop in tlp_read_packet() (Dan Carpenter) Fix Requester ID for config accesses (Ley Foon Tan) Check TLP completion status (Ley Foon Tan) Fix error when INTx is 4 (Ley Foon Tan) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWaE7hAAoJEFmIoMA60/r8ttwQAI7sv6+hLB+xSv8j43Xlh/wr M58VLpLHhsh0c5bhViIfTj3m56QPb1FqxzD1jD8NB29twPzf/j96UUUFHXZH5Amm kVdFVzslgpfBusGJeedL0Nei4R9TCVCaQv1BKODcLGGUZx1f29mlYLmgSVz7n3V0 oihjN4R352yjsH0goTHxsSHjnwR7mdzKmK6lWFAFgujQK3+eJ8WE+qniP0Rh5IWS voqQBE7N9vXzTqrBbEJYS1KZFUn7gBkkVPo1xFtniIHXZoT23in2Cg17eUQdMymN 6oXzzgiHkcJizuFhcxhtf7KitEbJk+6YWXxH03u5onDZQQNpJpcz17Us+vK3G4bb hdCMzOnZ2HAZgNP8W9yGdTB9Px9d6l1Kt3py3Nb9xJemMtl2IWVnxbRk/uu2ddF+ 83eX074U0lZqb8vAkR64EByKi8q+126BV5e+P7t3YgqJ1nA3luvk+bZsEiBFOePb hCNSSR2sP6mtYnVW0T3YPnZYJkrM3N28+JrZtP75szLjBNj3vmX2ani/dEJLAlkR UA6EoBiyJQvFyoZ2/pRb3dDYuNWoSP4yEAcZYwUFHmfs8AdF87Jl3BGH7HHW4C+8 sendp2WisODovdUa9/QKA0VX9VAStlzTIy5g+smMgZ340yp1Bl4HHxnZhN2kSR/P RZVNePtY/5DX60andYLb =3jiK -----END PGP SIGNATURE----- Merge tag 'pci-v4.4-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "These are more fixes I'd like to have in v4.4. Several for the Altera driver added for v4.4, and one for an MSI domain problem that affects several arm64 platforms: MSI: - Only use the generic MSI layer when domain is hierarchical (Marc Zyngier) Altera host bridge driver: - Fix loop in tlp_read_packet() (Dan Carpenter) - Fix Requester ID for config accesses (Ley Foon Tan) - Check TLP completion status (Ley Foon Tan) - Fix error when INTx is 4 (Ley Foon Tan)" * tag 'pci-v4.4-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: altera: Fix error when INTx is 4 PCI: altera: Check TLP completion status PCI: altera: Fix Requester ID for config accesses PCI: altera: Fix loop in tlp_read_packet() PCI/MSI: Only use the generic MSI layer when domain is hierarchical
This commit is contained in:
commit
978d6a9041
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@ -55,8 +55,10 @@
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#define TLP_CFG_DW2(bus, devfn, offset) \
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(((bus) << 24) | ((devfn) << 16) | (offset))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
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#define TLP_HDR_SIZE 3
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#define TLP_LOOP 500
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#define RP_DEVFN 0
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#define INTX_NUM 4
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@ -166,34 +168,41 @@ static bool altera_pcie_valid_config(struct altera_pcie *pcie,
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static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
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{
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u8 loop;
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int i;
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bool sop = 0;
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u32 ctrl;
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u32 reg0, reg1;
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u32 comp_status = 1;
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/*
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* Minimum 2 loops to read TLP headers and 1 loop to read data
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* payload.
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*/
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for (loop = 0; loop < TLP_LOOP; loop++) {
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for (i = 0; i < TLP_LOOP; i++) {
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ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
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if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
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reg0 = cra_readl(pcie, RP_RXCPL_REG0);
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reg1 = cra_readl(pcie, RP_RXCPL_REG1);
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if (ctrl & RP_RXCPL_SOP)
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if (ctrl & RP_RXCPL_SOP) {
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sop = true;
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comp_status = TLP_COMP_STATUS(reg1);
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}
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if (ctrl & RP_RXCPL_EOP) {
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if (comp_status)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (value)
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*value = reg0;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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udelay(5);
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}
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return -ENOENT;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
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@ -233,7 +242,7 @@ static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
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else
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn),
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
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TLP_READ_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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@ -253,7 +262,7 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
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else
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, devfn),
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
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TLP_WRITE_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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@ -458,7 +467,7 @@ static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
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struct device_node *node = dev->of_node;
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/* Setup INTx */
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pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM,
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pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
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&intx_domain_ops, pcie);
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if (!pcie->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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@ -54,7 +54,7 @@ static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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struct irq_domain *domain;
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domain = pci_msi_get_domain(dev);
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if (domain)
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if (domain && irq_domain_is_hierarchy(domain))
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return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
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return arch_setup_msi_irqs(dev, nvec, type);
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@ -65,7 +65,7 @@ static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
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struct irq_domain *domain;
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domain = pci_msi_get_domain(dev);
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if (domain)
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if (domain && irq_domain_is_hierarchy(domain))
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pci_msi_domain_free_irqs(domain, dev);
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else
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arch_teardown_msi_irqs(dev);
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