[SPARC64]: Add dummy host controller to root of all PCI domains.
We fake up a dummy one in all cases because that is the simplest thing to do and it happens to be necessary for hypervisor systems. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -368,7 +368,8 @@ static void pci_parse_of_addrs(struct of_device *op,
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struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
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struct device_node *node,
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struct pci_bus *bus, int devfn)
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struct pci_bus *bus, int devfn,
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int host_controller)
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{
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struct dev_archdata *sd;
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struct pci_dev *dev;
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@ -400,47 +401,62 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
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dev->devfn = devfn;
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dev->multifunction = 0; /* maybe a lie? */
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dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
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dev->device = of_getintprop_default(node, "device-id", 0xffff);
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dev->subsystem_vendor =
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of_getintprop_default(node, "subsystem-vendor-id", 0);
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dev->subsystem_device =
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of_getintprop_default(node, "subsystem-id", 0);
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dev->cfg_size = pci_cfg_space_size(dev);
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if (host_controller) {
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dev->vendor = 0x108e;
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dev->device = 0x8000;
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dev->subsystem_vendor = 0x0000;
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dev->subsystem_device = 0x0000;
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dev->cfg_size = 256;
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} else {
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dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
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dev->device = of_getintprop_default(node, "device-id", 0xffff);
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dev->subsystem_vendor =
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of_getintprop_default(node, "subsystem-vendor-id", 0);
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dev->subsystem_device =
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of_getintprop_default(node, "subsystem-id", 0);
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dev->cfg_size = pci_cfg_space_size(dev);
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}
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sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
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dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
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/* dev->class = of_getintprop_default(node, "class-code", 0); */
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/* We can't actually use the firmware value, we have to read what
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* is in the register right now. One reason is that in the case
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* of IDE interfaces the firmware can sample the value before the
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* the IDE interface is programmed into native mode.
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*/
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
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dev->class = class >> 8;
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if (host_controller) {
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dev->class = PCI_CLASS_BRIDGE_HOST << 8;
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} else {
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/* We can't actually use the firmware value, we have
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* to read what is in the register right now. One
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* reason is that in the case of IDE interfaces the
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* firmware can sample the value before the the IDE
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* interface is programmed into native mode.
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*/
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
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dev->class = class >> 8;
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}
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printk(" class: 0x%x\n", dev->class);
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dev->current_state = 4; /* unknown power state */
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dev->error_state = pci_channel_io_normal;
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if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
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/* a PCI-PCI bridge */
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if (host_controller) {
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dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
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dev->rom_base_reg = PCI_ROM_ADDRESS1;
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} else if (!strcmp(type, "cardbus")) {
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dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
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dev->irq = PCI_IRQ_NONE;
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} else {
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dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
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dev->rom_base_reg = PCI_ROM_ADDRESS;
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if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
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/* a PCI-PCI bridge */
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dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
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dev->rom_base_reg = PCI_ROM_ADDRESS1;
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} else if (!strcmp(type, "cardbus")) {
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dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
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} else {
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dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
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dev->rom_base_reg = PCI_ROM_ADDRESS;
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dev->irq = sd->op->irqs[0];
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if (dev->irq == 0xffffffff)
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dev->irq = PCI_IRQ_NONE;
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dev->irq = sd->op->irqs[0];
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if (dev->irq == 0xffffffff)
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dev->irq = PCI_IRQ_NONE;
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}
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}
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pci_parse_of_addrs(sd->op, node, dev);
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printk(" adding to system ...\n");
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@ -632,7 +648,7 @@ static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
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devfn = (reg[0] >> 8) & 0xff;
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/* create a new pci_dev for this device */
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dev = of_create_pci_dev(pbm, child, bus, devfn);
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dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
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if (!dev)
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continue;
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printk("PCI: dev header type: %x\n", dev->hdr_type);
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@ -677,10 +693,49 @@ static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
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pci_bus_register_of_sysfs(child_bus);
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}
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int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
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unsigned int devfn,
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int where, int size,
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u32 *value)
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{
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static u8 fake_pci_config[] = {
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0x8e, 0x10, /* Vendor: 0x108e (Sun) */
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0x00, 0x80, /* Device: 0x8000 (PBM) */
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0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
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0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
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0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
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0x00, /* Cacheline: 0x00 */
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0x40, /* Latency: 0x40 */
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0x00, /* Header-Type: 0x00 normal */
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};
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*value = 0;
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if (where >= 0 && where < sizeof(fake_pci_config) &&
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(where + size) >= 0 &&
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(where + size) < sizeof(fake_pci_config) &&
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size <= sizeof(u32)) {
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while (size--) {
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*value <<= 8;
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*value |= fake_pci_config[where + size];
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
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unsigned int devfn,
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int where, int size,
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u32 value)
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{
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
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{
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struct pci_controller_info *p = pbm->parent;
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struct device_node *node = pbm->prom_node;
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struct pci_dev *host_pdev;
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struct pci_bus *bus;
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printk("PCI: Scanning PBM %s\n", node->full_name);
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@ -698,6 +753,10 @@ struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
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bus->resource[0] = &pbm->io_space;
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bus->resource[1] = &pbm->mem_space;
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/* Create the dummy host bridge and link it in. */
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host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
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bus->self = host_pdev;
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pci_of_scan_bus(pbm, node, bus);
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pci_bus_add_devices(bus);
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pci_bus_register_of_sysfs(bus);
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@ -20,6 +20,15 @@ extern int pci_num_controllers;
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extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
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extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
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extern int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
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unsigned int devfn,
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int where, int size,
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u32 *value);
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extern int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
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unsigned int devfn,
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int where, int size,
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u32 value);
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/* Error reporting support. */
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extern void pci_scan_for_target_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
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extern void pci_scan_for_master_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
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@ -118,6 +118,10 @@ static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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u16 tmp16;
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u8 tmp8;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
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size, value);
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switch (size) {
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case 1:
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*value = 0xff;
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@ -171,6 +175,9 @@ static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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unsigned char bus = bus_dev->number;
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u32 *addr;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
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size, value);
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addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
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if (!addr)
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return PCIBIOS_SUCCESSFUL;
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@ -319,6 +319,12 @@ static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct pci_pbm_info *pbm = bus->sysdata;
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if (bus == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_read_pci_cfg(bus, devfn, where,
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size, value);
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if (!bus->number && sabre_out_of_range(devfn)) {
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switch (size) {
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case 1:
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@ -435,6 +441,12 @@ static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct pci_pbm_info *pbm = bus->sysdata;
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if (bus == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_write_pci_cfg(bus, devfn, where,
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size, value);
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if (bus->number)
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return __sabre_write_pci_cfg(bus, devfn, where, size, value);
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@ -125,6 +125,9 @@ static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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u16 tmp16;
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u8 tmp8;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
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size, value);
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switch (size) {
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case 1:
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*value = 0xff;
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@ -178,6 +181,9 @@ static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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unsigned char bus = bus_dev->number;
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u32 *addr;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
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size, value);
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addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
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if (!addr)
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return PCIBIOS_SUCCESSFUL;
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@ -612,6 +612,9 @@ static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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unsigned int func = PCI_FUNC(devfn);
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unsigned long ret;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
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size, value);
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if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
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ret = ~0UL;
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} else {
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@ -650,6 +653,9 @@ static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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unsigned int func = PCI_FUNC(devfn);
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unsigned long ret;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
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size, value);
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if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
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/* Do nothing. */
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} else {
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