arm-soc: clk changes
Clock support is moving to the clk subsystem. These tegra, omap and imx
changes are for code that is still platform specific and not (yet)
part of that subsystem.
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Merge tag 'clk' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc clk changes from Arnd Bergmann:
"Clock support is moving to the clk subsystem. These tegra, omap and
imx changes are for code that is still platform specific and not (yet)
part of that subsystem."
Fix up conflicts in arch/arm/mach-{imx/clk-imx51-imx53.c,omap2/Makefile}
* tag 'clk' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
ARM: imx: clk-imx31: Fix clock id for rnga driver
ARM: imx: add missing item to the list of clock event modes
ARM: i.MX5x CSPI: Fixed clock name for CSPI
ARM: i.MX5x clocks: Fix GPT clocks
ARM: i.MX5x clocks: Fix parent for PWM clocks
ARM: i.MX5x clocks: Add EPIT support
ARM: mx27: Reenable silicon version print
ARM: clk-imx27: Fix rtc clock id
ARM: tegra: Provide clock for only one PWM controller
ARM: tegra: Fix PWM clock programming
ARM: OMAP3+: clock33xx: Add AM33XX clock tree data
ARM: OMAP3+: clock: Move common clksel_rate & clock data to common file
ARM: tegra: dma: rename driver name for clock to "tegra-apbdma"
ARM: tegra: Remove second instance of uart clk
crypto: add clk_prepare/clk_unprepare
ASoC: tegra: add clk_prepare/clk_unprepare
staging: nvec: add clk_prepare/clk_unprepare
spi/tegra: add clk_prepare/clk_unprepare
Input: tegra-kbc - add clk_prepare/clk_unprepare
USB: ehci-tegra: add clk_prepare/clk_unprepare
...
This commit is contained in:
Linus Torvalds
commit
97e7292ab5
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@ -256,7 +256,7 @@ int __init mx27_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
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clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
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clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
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clk_register_clkdev(clk[rtc_ipg_gate], "rtc", NULL);
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clk_register_clkdev(clk[rtc_ipg_gate], NULL, "mxc_rtc");
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clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
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clk_register_clkdev(clk[cpu_div], "cpu", NULL);
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clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
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@ -267,6 +267,8 @@ int __init mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[emi_ahb_gate]);
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imx_print_silicon_rev("i.MX27", mx27_revision());
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return 0;
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}
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@ -124,7 +124,7 @@ int __init mx31_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
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clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
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clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
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clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
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clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
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clk_register_clkdev(clk[epit1_gate], "epit", NULL);
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clk_register_clkdev(clk[epit2_gate], "epit", NULL);
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clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
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@ -166,7 +166,7 @@ int __init mx31_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[firi_gate], "firi", NULL);
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clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
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clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
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clk_register_clkdev(clk[rng_gate], "rng", NULL);
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clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
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clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
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clk_register_clkdev(clk[iim_gate], "iim", NULL);
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@ -58,7 +58,7 @@ enum imx5_clks {
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tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
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uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
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gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
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gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
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gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
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esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
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ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
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ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
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@ -81,6 +81,7 @@ enum imx5_clks {
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ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
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ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
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ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
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epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
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clk_max
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};
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@ -167,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
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clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
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clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
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clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
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clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
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clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
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clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
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clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
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clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
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clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);
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clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
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clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
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clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
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clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
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clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
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clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
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@ -226,13 +227,17 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
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clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
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clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
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clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
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clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
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clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
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clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
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for (i = 0; i < ARRAY_SIZE(clk); i++)
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if (IS_ERR(clk[i]))
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pr_err("i.MX5 clk %d: register failed with %ld\n",
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i, PTR_ERR(clk[i]));
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clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
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clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
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clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
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@ -248,7 +253,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
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clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
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clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
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clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0");
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clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
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clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
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clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
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clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
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@ -280,6 +285,10 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
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clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
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clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
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clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
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clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
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clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
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clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
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clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
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/* Set SDHC parents to be PLL2 */
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clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
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@ -172,6 +172,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
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obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o
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obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
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obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
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@ -155,4 +155,18 @@ extern const struct clkops clkops_omap3_noncore_dpll_ops;
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extern const struct clkops clkops_omap3_core_dpll_ops;
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extern const struct clkops clkops_omap4_dpllmx_ops;
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/* clksel_rate blocks shared between OMAP44xx and AM33xx */
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extern const struct clksel_rate div_1_0_rates[];
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extern const struct clksel_rate div_1_1_rates[];
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extern const struct clksel_rate div_1_2_rates[];
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extern const struct clksel_rate div_1_3_rates[];
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extern const struct clksel_rate div_1_4_rates[];
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extern const struct clksel_rate div31_1to31_rates[];
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/* clocks shared between various OMAP SoCs */
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extern struct clk virt_19200000_ck;
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extern struct clk virt_26000000_ck;
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extern int am33xx_clk_init(void);
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#endif
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1105
arch/arm/mach-omap2/clock33xx_data.c
Normal file
1105
arch/arm/mach-omap2/clock33xx_data.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -93,18 +93,6 @@ static struct clk virt_16_8m_ck = {
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.rate = 16800000,
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};
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static struct clk virt_19_2m_ck = {
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.name = "virt_19_2m_ck",
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.ops = &clkops_null,
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.rate = 19200000,
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};
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static struct clk virt_26m_ck = {
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.name = "virt_26m_ck",
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.ops = &clkops_null,
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.rate = 26000000,
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};
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static struct clk virt_38_4m_ck = {
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.name = "virt_38_4m_ck",
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.ops = &clkops_null,
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@ -145,8 +133,8 @@ static const struct clksel osc_sys_clksel[] = {
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{ .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
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{ .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
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{ .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
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{ .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
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{ .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
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{ .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
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{ .parent = &virt_26000000_ck, .rates = osc_sys_26m_rates },
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{ .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
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{ .parent = NULL },
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};
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@ -3234,8 +3222,8 @@ static struct omap_clk omap3xxx_clks[] = {
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CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
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CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
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CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
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CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
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CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
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CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
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CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
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CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
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CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
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CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
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@ -107,18 +107,6 @@ static struct clk virt_16800000_ck = {
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.rate = 16800000,
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};
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static struct clk virt_19200000_ck = {
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.name = "virt_19200000_ck",
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.ops = &clkops_null,
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.rate = 19200000,
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};
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static struct clk virt_26000000_ck = {
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.name = "virt_26000000_ck",
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.ops = &clkops_null,
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.rate = 26000000,
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};
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static struct clk virt_27000000_ck = {
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.name = "virt_27000000_ck",
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.ops = &clkops_null,
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@ -131,31 +119,6 @@ static struct clk virt_38400000_ck = {
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.rate = 38400000,
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};
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static const struct clksel_rate div_1_0_rates[] = {
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{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
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{ .div = 0 },
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};
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static const struct clksel_rate div_1_1_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
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{ .div = 0 },
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};
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static const struct clksel_rate div_1_2_rates[] = {
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{ .div = 1, .val = 2, .flags = RATE_IN_4430 },
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{ .div = 0 },
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};
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static const struct clksel_rate div_1_3_rates[] = {
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{ .div = 1, .val = 3, .flags = RATE_IN_4430 },
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{ .div = 0 },
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};
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static const struct clksel_rate div_1_4_rates[] = {
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{ .div = 1, .val = 4, .flags = RATE_IN_4430 },
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{ .div = 0 },
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};
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static const struct clksel_rate div_1_5_rates[] = {
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{ .div = 1, .val = 5, .flags = RATE_IN_4430 },
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{ .div = 0 },
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@ -289,41 +252,6 @@ static struct clk dpll_abe_x2_ck = {
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.recalc = &omap3_clkoutx2_recalc,
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};
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static const struct clksel_rate div31_1to31_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
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{ .div = 2, .val = 2, .flags = RATE_IN_4430 },
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{ .div = 3, .val = 3, .flags = RATE_IN_4430 },
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{ .div = 4, .val = 4, .flags = RATE_IN_4430 },
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{ .div = 5, .val = 5, .flags = RATE_IN_4430 },
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{ .div = 6, .val = 6, .flags = RATE_IN_4430 },
|
||||
{ .div = 7, .val = 7, .flags = RATE_IN_4430 },
|
||||
{ .div = 8, .val = 8, .flags = RATE_IN_4430 },
|
||||
{ .div = 9, .val = 9, .flags = RATE_IN_4430 },
|
||||
{ .div = 10, .val = 10, .flags = RATE_IN_4430 },
|
||||
{ .div = 11, .val = 11, .flags = RATE_IN_4430 },
|
||||
{ .div = 12, .val = 12, .flags = RATE_IN_4430 },
|
||||
{ .div = 13, .val = 13, .flags = RATE_IN_4430 },
|
||||
{ .div = 14, .val = 14, .flags = RATE_IN_4430 },
|
||||
{ .div = 15, .val = 15, .flags = RATE_IN_4430 },
|
||||
{ .div = 16, .val = 16, .flags = RATE_IN_4430 },
|
||||
{ .div = 17, .val = 17, .flags = RATE_IN_4430 },
|
||||
{ .div = 18, .val = 18, .flags = RATE_IN_4430 },
|
||||
{ .div = 19, .val = 19, .flags = RATE_IN_4430 },
|
||||
{ .div = 20, .val = 20, .flags = RATE_IN_4430 },
|
||||
{ .div = 21, .val = 21, .flags = RATE_IN_4430 },
|
||||
{ .div = 22, .val = 22, .flags = RATE_IN_4430 },
|
||||
{ .div = 23, .val = 23, .flags = RATE_IN_4430 },
|
||||
{ .div = 24, .val = 24, .flags = RATE_IN_4430 },
|
||||
{ .div = 25, .val = 25, .flags = RATE_IN_4430 },
|
||||
{ .div = 26, .val = 26, .flags = RATE_IN_4430 },
|
||||
{ .div = 27, .val = 27, .flags = RATE_IN_4430 },
|
||||
{ .div = 28, .val = 28, .flags = RATE_IN_4430 },
|
||||
{ .div = 29, .val = 29, .flags = RATE_IN_4430 },
|
||||
{ .div = 30, .val = 30, .flags = RATE_IN_4430 },
|
||||
{ .div = 31, .val = 31, .flags = RATE_IN_4430 },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
static const struct clksel dpll_abe_m2x2_div[] = {
|
||||
{ .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
|
||||
{ .parent = NULL },
|
||||
|
|
|
|||
|
|
@ -43,3 +43,80 @@ const struct clksel_rate dsp_ick_rates[] = {
|
|||
{ .div = 3, .val = 3, .flags = RATE_IN_243X },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
|
||||
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
|
||||
|
||||
const struct clksel_rate div_1_0_rates[] = {
|
||||
{ .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
const struct clksel_rate div_1_1_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
const struct clksel_rate div_1_2_rates[] = {
|
||||
{ .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
const struct clksel_rate div_1_3_rates[] = {
|
||||
{ .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
const struct clksel_rate div_1_4_rates[] = {
|
||||
{ .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
const struct clksel_rate div31_1to31_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
|
||||
{ .div = 0 },
|
||||
};
|
||||
|
||||
/* Clocks shared between various OMAP SoCs */
|
||||
|
||||
struct clk virt_19200000_ck = {
|
||||
.name = "virt_19200000_ck",
|
||||
.ops = &clkops_null,
|
||||
.rate = 19200000,
|
||||
};
|
||||
|
||||
struct clk virt_26000000_ck = {
|
||||
.name = "virt_26000000_ck",
|
||||
.ops = &clkops_null,
|
||||
.rate = 26000000,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#include "powerdomain.h"
|
||||
#include "clockdomain.h"
|
||||
#include "common.h"
|
||||
#include "clock.h"
|
||||
#include "clock2xxx.h"
|
||||
#include "clock3xxx.h"
|
||||
#include "clock44xx.h"
|
||||
|
|
@ -522,6 +523,7 @@ void __init am33xx_init_early(void)
|
|||
am33xx_voltagedomains_init();
|
||||
am33xx_powerdomains_init();
|
||||
am33xx_clockdomains_init();
|
||||
am33xx_clk_init();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
|
|||
return PTR_ERR(emc_clk);
|
||||
}
|
||||
|
||||
clk_enable(emc_clk);
|
||||
clk_enable(cpu_clk);
|
||||
clk_prepare_enable(emc_clk);
|
||||
clk_prepare_enable(cpu_clk);
|
||||
|
||||
cpufreq_frequency_table_cpuinfo(policy, freq_table);
|
||||
cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
|
||||
|
|
@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
|
|||
static int tegra_cpu_exit(struct cpufreq_policy *policy)
|
||||
{
|
||||
cpufreq_frequency_table_cpuinfo(policy, freq_table);
|
||||
clk_disable(emc_clk);
|
||||
clk_disable_unprepare(emc_clk);
|
||||
clk_put(emc_clk);
|
||||
clk_put(cpu_clk);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -714,13 +714,13 @@ int __init tegra_dma_init(void)
|
|||
|
||||
bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
|
||||
|
||||
c = clk_get_sys("tegra-dma", NULL);
|
||||
c = clk_get_sys("tegra-apbdma", NULL);
|
||||
if (IS_ERR(c)) {
|
||||
pr_err("Unable to get clock for APB DMA\n");
|
||||
ret = PTR_ERR(c);
|
||||
goto fail;
|
||||
}
|
||||
ret = clk_enable(c);
|
||||
ret = clk_prepare_enable(c);
|
||||
if (ret != 0) {
|
||||
pr_err("Unable to enable clock for APB DMA\n");
|
||||
goto fail;
|
||||
|
|
|
|||
|
|
@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
|
|||
|
||||
tegra_pcie_xclk_clamp(false);
|
||||
|
||||
clk_enable(tegra_pcie.afi_clk);
|
||||
clk_enable(tegra_pcie.pex_clk);
|
||||
return clk_enable(tegra_pcie.pll_e);
|
||||
clk_prepare_enable(tegra_pcie.afi_clk);
|
||||
clk_prepare_enable(tegra_pcie.pex_clk);
|
||||
return clk_prepare_enable(tegra_pcie.pll_e);
|
||||
}
|
||||
|
||||
static int tegra_pcie_clocks_get(void)
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
|
|||
if (ret)
|
||||
goto err_power;
|
||||
|
||||
ret = clk_enable(clk);
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
|
|
@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
|
|||
return 0;
|
||||
|
||||
err_clamp:
|
||||
clk_disable(clk);
|
||||
clk_disable_unprepare(clk);
|
||||
err_clk:
|
||||
tegra_powergate_power_off(id);
|
||||
err_power:
|
||||
|
|
|
|||
|
|
@ -69,6 +69,8 @@
|
|||
|
||||
#define PERIPH_CLK_SOURCE_MASK (3<<30)
|
||||
#define PERIPH_CLK_SOURCE_SHIFT 30
|
||||
#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
|
||||
#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
|
||||
#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
|
||||
#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
|
||||
#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
|
||||
|
|
@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c)
|
|||
u32 val = clk_readl(c->reg);
|
||||
const struct clk_mux_sel *mux = NULL;
|
||||
const struct clk_mux_sel *sel;
|
||||
u32 shift;
|
||||
u32 mask;
|
||||
|
||||
if (c->flags & MUX_PWM) {
|
||||
shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
|
||||
mask = PERIPH_CLK_SOURCE_PWM_MASK;
|
||||
} else {
|
||||
shift = PERIPH_CLK_SOURCE_SHIFT;
|
||||
mask = PERIPH_CLK_SOURCE_MASK;
|
||||
}
|
||||
|
||||
if (c->flags & MUX) {
|
||||
for (sel = c->inputs; sel->input != NULL; sel++) {
|
||||
if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
|
||||
if ((val & mask) >> shift == sel->value)
|
||||
mux = sel;
|
||||
}
|
||||
BUG_ON(!mux);
|
||||
|
|
@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
|
|||
{
|
||||
u32 val;
|
||||
const struct clk_mux_sel *sel;
|
||||
u32 mask, shift;
|
||||
|
||||
pr_debug("%s: %s %s\n", __func__, c->name, p->name);
|
||||
|
||||
if (c->flags & MUX_PWM) {
|
||||
shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
|
||||
mask = PERIPH_CLK_SOURCE_PWM_MASK;
|
||||
} else {
|
||||
shift = PERIPH_CLK_SOURCE_SHIFT;
|
||||
mask = PERIPH_CLK_SOURCE_MASK;
|
||||
}
|
||||
|
||||
for (sel = c->inputs; sel->input != NULL; sel++) {
|
||||
if (sel->input == p) {
|
||||
val = clk_readl(c->reg);
|
||||
val &= ~PERIPH_CLK_SOURCE_MASK;
|
||||
val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
|
||||
val &= ~mask;
|
||||
val |= (sel->value) << shift;
|
||||
|
||||
if (c->refcnt)
|
||||
clk_enable(p);
|
||||
|
|
@ -2149,14 +2173,14 @@ static struct clk tegra_clk_emc = {
|
|||
}
|
||||
|
||||
static struct clk tegra_list_clks[] = {
|
||||
PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
|
||||
PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
|
||||
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
|
||||
PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
|
||||
PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
|
||||
PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
|
||||
PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
|
||||
PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
|
||||
|
|
@ -2189,11 +2213,11 @@ static struct clk tegra_list_clks[] = {
|
|||
PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
|
||||
PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
|
||||
PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
|
||||
PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
|
||||
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
|
||||
PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
|
||||
PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
|
||||
|
|
@ -2245,20 +2269,16 @@ static struct clk tegra_list_clks[] = {
|
|||
* table under two names.
|
||||
*/
|
||||
static struct clk_duplicate tegra_clk_duplicates[] = {
|
||||
CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
|
||||
CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
|
||||
CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
|
||||
CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
|
||||
CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
|
||||
CLK_DUPLICATE("uarta", "serial8250.0", NULL),
|
||||
CLK_DUPLICATE("uartb", "serial8250.1", NULL),
|
||||
CLK_DUPLICATE("uartc", "serial8250.2", NULL),
|
||||
CLK_DUPLICATE("uartd", "serial8250.3", NULL),
|
||||
CLK_DUPLICATE("uarte", "serial8250.4", NULL),
|
||||
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
|
||||
CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
|
||||
CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
|
||||
CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
|
||||
CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
|
||||
CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
|
||||
|
|
|
|||
|
|
@ -2871,7 +2871,7 @@ static struct clk tegra30_clk_twd = {
|
|||
}, \
|
||||
}
|
||||
struct clk tegra_list_clks[] = {
|
||||
PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0),
|
||||
PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
|
||||
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
|
||||
PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
|
||||
PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
|
||||
|
|
@ -2886,7 +2886,7 @@ struct clk tegra_list_clks[] = {
|
|||
PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
|
||||
PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
|
||||
|
|
@ -2924,16 +2924,11 @@ struct clk tegra_list_clks[] = {
|
|||
PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
|
||||
PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
|
||||
PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
|
||||
PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
|
||||
|
|
@ -2983,6 +2978,11 @@ struct clk tegra_list_clks[] = {
|
|||
* table under two names.
|
||||
*/
|
||||
struct clk_duplicate tegra_clk_duplicates[] = {
|
||||
CLK_DUPLICATE("uarta", "serial8250.0", NULL),
|
||||
CLK_DUPLICATE("uartb", "serial8250.1", NULL),
|
||||
CLK_DUPLICATE("uartc", "serial8250.2", NULL),
|
||||
CLK_DUPLICATE("uartd", "serial8250.3", NULL),
|
||||
CLK_DUPLICATE("uarte", "serial8250.4", NULL),
|
||||
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
|
||||
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
|
||||
|
|
@ -2990,10 +2990,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
|
|||
CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
|
||||
CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
|
||||
CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
|
||||
CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
|
||||
CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
|
||||
CLK_DUPLICATE("bsev", "nvavp", "bsev"),
|
||||
CLK_DUPLICATE("vde", "tegra-aes", "vde"),
|
||||
|
|
|
|||
|
|
@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
|
|||
" Assuming 12Mhz input clock.\n");
|
||||
rate = 12000000;
|
||||
} else {
|
||||
clk_enable(clk);
|
||||
clk_prepare_enable(clk);
|
||||
rate = clk_get_rate(clk);
|
||||
}
|
||||
|
||||
|
|
@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
|
|||
if (IS_ERR(clk))
|
||||
pr_warn("Unable to get rtc-tegra clock\n");
|
||||
else
|
||||
clk_enable(clk);
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
switch (rate) {
|
||||
case 12000000:
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
|
|||
unsigned long val, flags;
|
||||
void __iomem *base = phy->pad_regs;
|
||||
|
||||
clk_enable(phy->pad_clk);
|
||||
clk_prepare_enable(phy->pad_clk);
|
||||
|
||||
spin_lock_irqsave(&utmip_pad_lock, flags);
|
||||
|
||||
|
|
@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
|
|||
|
||||
spin_unlock_irqrestore(&utmip_pad_lock, flags);
|
||||
|
||||
clk_disable(phy->pad_clk);
|
||||
clk_disable_unprepare(phy->pad_clk);
|
||||
}
|
||||
|
||||
static int utmip_pad_power_off(struct tegra_usb_phy *phy)
|
||||
|
|
@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk_enable(phy->pad_clk);
|
||||
clk_prepare_enable(phy->pad_clk);
|
||||
|
||||
spin_lock_irqsave(&utmip_pad_lock, flags);
|
||||
|
||||
|
|
@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
|
|||
|
||||
spin_unlock_irqrestore(&utmip_pad_lock, flags);
|
||||
|
||||
clk_disable(phy->pad_clk);
|
||||
clk_disable_unprepare(phy->pad_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
|
|||
msleep(5);
|
||||
gpio_direction_output(config->reset_gpio, 1);
|
||||
|
||||
clk_enable(phy->clk);
|
||||
clk_prepare_enable(phy->clk);
|
||||
msleep(1);
|
||||
|
||||
val = readl(base + USB_SUSP_CTRL);
|
||||
|
|
@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
|
|||
err = PTR_ERR(phy->pll_u);
|
||||
goto err0;
|
||||
}
|
||||
clk_enable(phy->pll_u);
|
||||
clk_prepare_enable(phy->pll_u);
|
||||
|
||||
parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
|
||||
for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
|
||||
|
|
@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
|
|||
return phy;
|
||||
|
||||
err1:
|
||||
clk_disable(phy->pll_u);
|
||||
clk_disable_unprepare(phy->pll_u);
|
||||
clk_put(phy->pll_u);
|
||||
err0:
|
||||
kfree(phy);
|
||||
|
|
@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
|
|||
clk_put(phy->clk);
|
||||
else
|
||||
utmip_pad_close(phy);
|
||||
clk_disable(phy->pll_u);
|
||||
clk_disable_unprepare(phy->pll_u);
|
||||
clk_put(phy->pll_u);
|
||||
kfree(phy);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
|
|||
#ifdef CONFIG_SOC_IMX53
|
||||
/* i.mx53 has the i.mx35 type cspi */
|
||||
const struct imx_spi_imx_data imx53_cspi_data __initconst =
|
||||
imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 0, , SZ_4K);
|
||||
imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
|
||||
|
||||
/* i.mx53 has the i.mx51 type ecspi */
|
||||
const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -160,7 +160,8 @@ static const char *clock_event_mode_label[] = {
|
|||
[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
|
||||
[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
|
||||
[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
|
||||
[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
|
||||
[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
|
||||
[CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
|
||||
};
|
||||
#endif /* DEBUG */
|
||||
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ struct omap_clk {
|
|||
#define CK_443X (1 << 11)
|
||||
#define CK_TI816X (1 << 12)
|
||||
#define CK_446X (1 << 13)
|
||||
#define CK_AM33XX (1 << 14) /* AM33xx specific clocks */
|
||||
#define CK_1710 (1 << 15) /* 1710 extra for rate selection */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -572,7 +572,7 @@ static void aes_workqueue_handler(struct work_struct *work)
|
|||
struct tegra_aes_dev *dd = aes_dev;
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(dd->aes_clk);
|
||||
ret = clk_prepare_enable(dd->aes_clk);
|
||||
if (ret)
|
||||
BUG_ON("clock enable failed");
|
||||
|
||||
|
|
@ -581,7 +581,7 @@ static void aes_workqueue_handler(struct work_struct *work)
|
|||
ret = tegra_aes_handle_req(dd);
|
||||
} while (!ret);
|
||||
|
||||
clk_disable(dd->aes_clk);
|
||||
clk_disable_unprepare(dd->aes_clk);
|
||||
}
|
||||
|
||||
static irqreturn_t aes_irq(int irq, void *dev_id)
|
||||
|
|
@ -673,7 +673,7 @@ static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata,
|
|||
/* take mutex to access the aes hw */
|
||||
mutex_lock(&aes_lock);
|
||||
|
||||
ret = clk_enable(dd->aes_clk);
|
||||
ret = clk_prepare_enable(dd->aes_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -700,7 +700,7 @@ static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata,
|
|||
}
|
||||
|
||||
out:
|
||||
clk_disable(dd->aes_clk);
|
||||
clk_disable_unprepare(dd->aes_clk);
|
||||
mutex_unlock(&aes_lock);
|
||||
|
||||
dev_dbg(dd->dev, "%s: done\n", __func__);
|
||||
|
|
@ -758,7 +758,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
|
|||
|
||||
dd->flags = FLAGS_ENCRYPT | FLAGS_RNG;
|
||||
|
||||
ret = clk_enable(dd->aes_clk);
|
||||
ret = clk_prepare_enable(dd->aes_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -788,7 +788,7 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
|
|||
memcpy(dd->dt, dt, DEFAULT_RNG_BLK_SZ);
|
||||
|
||||
out:
|
||||
clk_disable(dd->aes_clk);
|
||||
clk_disable_unprepare(dd->aes_clk);
|
||||
mutex_unlock(&aes_lock);
|
||||
|
||||
dev_dbg(dd->dev, "%s: done\n", __func__);
|
||||
|
|
|
|||
|
|
@ -341,7 +341,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
|
|||
u32 val;
|
||||
int err = 0;
|
||||
|
||||
clk_enable(i2c_dev->clk);
|
||||
clk_prepare_enable(i2c_dev->clk);
|
||||
|
||||
tegra_periph_reset_assert(i2c_dev->clk);
|
||||
udelay(2);
|
||||
|
|
@ -372,7 +372,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
|
|||
if (tegra_i2c_flush_fifos(i2c_dev))
|
||||
err = -ETIMEDOUT;
|
||||
|
||||
clk_disable(i2c_dev->clk);
|
||||
clk_disable_unprepare(i2c_dev->clk);
|
||||
|
||||
if (i2c_dev->irq_disabled) {
|
||||
i2c_dev->irq_disabled = 0;
|
||||
|
|
@ -546,14 +546,14 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
|
|||
if (i2c_dev->is_suspended)
|
||||
return -EBUSY;
|
||||
|
||||
clk_enable(i2c_dev->clk);
|
||||
clk_prepare_enable(i2c_dev->clk);
|
||||
for (i = 0; i < num; i++) {
|
||||
int stop = (i == (num - 1)) ? 1 : 0;
|
||||
ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
clk_disable(i2c_dev->clk);
|
||||
clk_disable_unprepare(i2c_dev->clk);
|
||||
return ret ?: i;
|
||||
}
|
||||
|
||||
|
|
@ -666,7 +666,7 @@ static int __devinit tegra_i2c_probe(struct platform_device *pdev)
|
|||
goto err_free;
|
||||
}
|
||||
|
||||
clk_enable(i2c_dev->i2c_clk);
|
||||
clk_prepare_enable(i2c_dev->i2c_clk);
|
||||
|
||||
i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
|
||||
i2c_dev->adapter.owner = THIS_MODULE;
|
||||
|
|
|
|||
|
|
@ -492,7 +492,7 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
|
|||
unsigned int debounce_cnt;
|
||||
u32 val = 0;
|
||||
|
||||
clk_enable(kbc->clk);
|
||||
clk_prepare_enable(kbc->clk);
|
||||
|
||||
/* Reset the KBC controller to clear all previous status.*/
|
||||
tegra_periph_reset_assert(kbc->clk);
|
||||
|
|
@ -556,7 +556,7 @@ static void tegra_kbc_stop(struct tegra_kbc *kbc)
|
|||
disable_irq(kbc->irq);
|
||||
del_timer_sync(&kbc->timer);
|
||||
|
||||
clk_disable(kbc->clk);
|
||||
clk_disable_unprepare(kbc->clk);
|
||||
}
|
||||
|
||||
static int tegra_kbc_open(struct input_dev *dev)
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
rc = PTR_ERR(clk);
|
||||
goto err_clk_get;
|
||||
}
|
||||
clk_enable(clk);
|
||||
clk_prepare_enable(clk);
|
||||
pltfm_host->clk = clk;
|
||||
|
||||
host->mmc->pm_caps = plat->pm_flags;
|
||||
|
|
@ -352,7 +352,7 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
|
||||
err_add_host:
|
||||
clk_disable(pltfm_host->clk);
|
||||
clk_disable_unprepare(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
err_clk_get:
|
||||
if (gpio_is_valid(plat->wp_gpio))
|
||||
|
|
@ -393,7 +393,7 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
|
|||
if (gpio_is_valid(plat->power_gpio))
|
||||
gpio_free(plat->power_gpio);
|
||||
|
||||
clk_disable(pltfm_host->clk);
|
||||
clk_disable_unprepare(pltfm_host->clk);
|
||||
clk_put(pltfm_host->clk);
|
||||
|
||||
sdhci_pltfm_free(pdev);
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ static void spi_tegra_start_transfer(struct spi_device *spi,
|
|||
clk_set_rate(tspi->clk, speed);
|
||||
|
||||
if (tspi->cur_speed == 0)
|
||||
clk_enable(tspi->clk);
|
||||
clk_prepare_enable(tspi->clk);
|
||||
|
||||
tspi->cur_speed = speed;
|
||||
|
||||
|
|
@ -373,7 +373,7 @@ static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
|
|||
spi = m->state;
|
||||
spi_tegra_start_message(spi, m);
|
||||
} else {
|
||||
clk_disable(tspi->clk);
|
||||
clk_disable_unprepare(tspi->clk);
|
||||
tspi->cur_speed = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -675,7 +675,7 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
|
|||
{
|
||||
u32 val;
|
||||
|
||||
clk_enable(nvec->i2c_clk);
|
||||
clk_prepare_enable(nvec->i2c_clk);
|
||||
|
||||
tegra_periph_reset_assert(nvec->i2c_clk);
|
||||
udelay(2);
|
||||
|
|
@ -695,14 +695,14 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
|
|||
|
||||
enable_irq(nvec->irq);
|
||||
|
||||
clk_disable(nvec->i2c_clk);
|
||||
clk_disable_unprepare(nvec->i2c_clk);
|
||||
}
|
||||
|
||||
static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
|
||||
{
|
||||
disable_irq(nvec->irq);
|
||||
writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
|
||||
clk_disable(nvec->i2c_clk);
|
||||
clk_disable_unprepare(nvec->i2c_clk);
|
||||
}
|
||||
|
||||
static void nvec_power_off(void)
|
||||
|
|
@ -812,7 +812,7 @@ static int __devinit tegra_nvec_probe(struct platform_device *pdev)
|
|||
|
||||
tegra_init_i2c_slave(nvec);
|
||||
|
||||
clk_enable(i2c_clk);
|
||||
clk_prepare_enable(i2c_clk);
|
||||
|
||||
|
||||
/* enable event reporting */
|
||||
|
|
|
|||
|
|
@ -46,8 +46,8 @@ static void tegra_ehci_power_up(struct usb_hcd *hcd)
|
|||
{
|
||||
struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
|
||||
|
||||
clk_enable(tegra->emc_clk);
|
||||
clk_enable(tegra->clk);
|
||||
clk_prepare_enable(tegra->emc_clk);
|
||||
clk_prepare_enable(tegra->clk);
|
||||
tegra_usb_phy_power_on(tegra->phy);
|
||||
tegra->host_resumed = 1;
|
||||
}
|
||||
|
|
@ -58,8 +58,8 @@ static void tegra_ehci_power_down(struct usb_hcd *hcd)
|
|||
|
||||
tegra->host_resumed = 0;
|
||||
tegra_usb_phy_power_off(tegra->phy);
|
||||
clk_disable(tegra->clk);
|
||||
clk_disable(tegra->emc_clk);
|
||||
clk_disable_unprepare(tegra->clk);
|
||||
clk_disable_unprepare(tegra->emc_clk);
|
||||
}
|
||||
|
||||
static int tegra_ehci_internal_port_reset(
|
||||
|
|
@ -671,7 +671,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
|
|||
goto fail_clk;
|
||||
}
|
||||
|
||||
err = clk_enable(tegra->clk);
|
||||
err = clk_prepare_enable(tegra->clk);
|
||||
if (err)
|
||||
goto fail_clken;
|
||||
|
||||
|
|
@ -682,7 +682,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
|
|||
goto fail_emc_clk;
|
||||
}
|
||||
|
||||
clk_enable(tegra->emc_clk);
|
||||
clk_prepare_enable(tegra->emc_clk);
|
||||
clk_set_rate(tegra->emc_clk, 400000000);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
|
@ -782,10 +782,10 @@ fail:
|
|||
fail_phy:
|
||||
iounmap(hcd->regs);
|
||||
fail_io:
|
||||
clk_disable(tegra->emc_clk);
|
||||
clk_disable_unprepare(tegra->emc_clk);
|
||||
clk_put(tegra->emc_clk);
|
||||
fail_emc_clk:
|
||||
clk_disable(tegra->clk);
|
||||
clk_disable_unprepare(tegra->clk);
|
||||
fail_clken:
|
||||
clk_put(tegra->clk);
|
||||
fail_clk:
|
||||
|
|
@ -820,10 +820,10 @@ static int tegra_ehci_remove(struct platform_device *pdev)
|
|||
tegra_usb_phy_close(tegra->phy);
|
||||
iounmap(hcd->regs);
|
||||
|
||||
clk_disable(tegra->clk);
|
||||
clk_disable_unprepare(tegra->clk);
|
||||
clk_put(tegra->clk);
|
||||
|
||||
clk_disable(tegra->emc_clk);
|
||||
clk_disable_unprepare(tegra->emc_clk);
|
||||
clk_put(tegra->emc_clk);
|
||||
|
||||
kfree(tegra);
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ static int tegra20_i2s_runtime_suspend(struct device *dev)
|
|||
{
|
||||
struct tegra20_i2s *i2s = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable(i2s->clk_i2s);
|
||||
clk_disable_unprepare(i2s->clk_i2s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -72,7 +72,7 @@ static int tegra20_i2s_runtime_resume(struct device *dev)
|
|||
struct tegra20_i2s *i2s = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(i2s->clk_i2s);
|
||||
ret = clk_prepare_enable(i2s->clk_i2s);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ static int tegra20_spdif_runtime_suspend(struct device *dev)
|
|||
{
|
||||
struct tegra20_spdif *spdif = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable(spdif->clk_spdif_out);
|
||||
clk_disable_unprepare(spdif->clk_spdif_out);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -64,7 +64,7 @@ static int tegra20_spdif_runtime_resume(struct device *dev)
|
|||
struct tegra20_spdif *spdif = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(spdif->clk_spdif_out);
|
||||
ret = clk_prepare_enable(spdif->clk_spdif_out);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -56,8 +56,8 @@ static int tegra30_ahub_runtime_suspend(struct device *dev)
|
|||
regcache_cache_only(ahub->regmap_apbif, true);
|
||||
regcache_cache_only(ahub->regmap_ahub, true);
|
||||
|
||||
clk_disable(ahub->clk_apbif);
|
||||
clk_disable(ahub->clk_d_audio);
|
||||
clk_disable_unprepare(ahub->clk_apbif);
|
||||
clk_disable_unprepare(ahub->clk_d_audio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -77,12 +77,12 @@ static int tegra30_ahub_runtime_resume(struct device *dev)
|
|||
{
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(ahub->clk_d_audio);
|
||||
ret = clk_prepare_enable(ahub->clk_d_audio);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable d_audio failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ret = clk_enable(ahub->clk_apbif);
|
||||
ret = clk_prepare_enable(ahub->clk_apbif);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable apbif failed: %d\n", ret);
|
||||
clk_disable(ahub->clk_d_audio);
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ static int tegra30_i2s_runtime_suspend(struct device *dev)
|
|||
|
||||
regcache_cache_only(i2s->regmap, true);
|
||||
|
||||
clk_disable(i2s->clk_i2s);
|
||||
clk_disable_unprepare(i2s->clk_i2s);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -72,7 +72,7 @@ static int tegra30_i2s_runtime_resume(struct device *dev)
|
|||
struct tegra30_i2s *i2s = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(i2s->clk_i2s);
|
||||
ret = clk_prepare_enable(i2s->clk_i2s);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -69,9 +69,9 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
|
|||
data->set_baseclock = 0;
|
||||
data->set_mclk = 0;
|
||||
|
||||
clk_disable(data->clk_cdev1);
|
||||
clk_disable(data->clk_pll_a_out0);
|
||||
clk_disable(data->clk_pll_a);
|
||||
clk_disable_unprepare(data->clk_cdev1);
|
||||
clk_disable_unprepare(data->clk_pll_a_out0);
|
||||
clk_disable_unprepare(data->clk_pll_a);
|
||||
|
||||
err = clk_set_rate(data->clk_pll_a, new_baseclock);
|
||||
if (err) {
|
||||
|
|
@ -87,19 +87,19 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
|
|||
|
||||
/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
|
||||
|
||||
err = clk_enable(data->clk_pll_a);
|
||||
err = clk_prepare_enable(data->clk_pll_a);
|
||||
if (err) {
|
||||
dev_err(data->dev, "Can't enable pll_a: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_enable(data->clk_pll_a_out0);
|
||||
err = clk_prepare_enable(data->clk_pll_a_out0);
|
||||
if (err) {
|
||||
dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_enable(data->clk_cdev1);
|
||||
err = clk_prepare_enable(data->clk_cdev1);
|
||||
if (err) {
|
||||
dev_err(data->dev, "Can't enable cdev1: %d\n", err);
|
||||
return err;
|
||||
|
|
|
|||
Loading…
Reference in a new issue