arm64 fixes for -rc5
Just a couple of stragglers here: - Fix an issue migrating interrupts on CPU hotplug - Fix a potential information leak of TLS registers across an exec (Nathan has sent a corresponding patch for arch/arm/ to rmk) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJUEfKCAAoJELescNyEwWM0I/8H/RLpR9kvk0npB8lroFJZUJfa yIveU5kWnFpEpycjkDDHTYmXbbAMni1t6wII4ofMErDtMkJMW3y11gAp2iUEdP8w YNGSO9WV8uddbEamoDnO1jMS2eE1sHSSFjXN5529ygM00mAdSq/sIYUkGrjkbRmo 6DHWFvaHYjZDIAb1teFFqtuaL5c4SX+DTwInqwO0hXIPXfgjmSD9PDk8KXJN0Qiu daX3sNHlFyb4Bh4Q2/aIvQHrkFPVcNUnekCwNoHGgYJ/FMjTV67Kb5SmnlV41rSu GU4dUuc26gumgrOQ9Yhob2AU6RhC4Auuht7ck+STZWy5kllmjX5TLZMLXmrLIRM= =0A4L -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Will Deacon: "Just a couple of stragglers here: - fix an issue migrating interrupts on CPU hotplug - fix a potential information leak of TLS registers across an exec (Nathan has sent a corresponding patch for arch/arm/ to rmk)" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: flush TLS registers during exec arm64: use irq_set_affinity with force=false when migrating irqs
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9925cc1396
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@ -97,19 +97,15 @@ static bool migrate_one_irq(struct irq_desc *desc)
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if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
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return false;
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if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids)
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if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
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affinity = cpu_online_mask;
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ret = true;
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}
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/*
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* when using forced irq_set_affinity we must ensure that the cpu
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* being offlined is not present in the affinity mask, it may be
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* selected as the target CPU otherwise
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*/
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affinity = cpu_online_mask;
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c = irq_data_get_irq_chip(d);
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if (!c->irq_set_affinity)
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pr_debug("IRQ%u: unable to set affinity\n", d->irq);
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else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
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else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
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cpumask_copy(d->affinity, affinity);
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return ret;
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@ -230,9 +230,27 @@ void exit_thread(void)
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{
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}
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static void tls_thread_flush(void)
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{
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asm ("msr tpidr_el0, xzr");
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if (is_compat_task()) {
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current->thread.tp_value = 0;
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/*
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* We need to ensure ordering between the shadow state and the
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* hardware state, so that we don't corrupt the hardware state
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* with a stale shadow state during context switch.
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*/
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barrier();
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asm ("msr tpidrro_el0, xzr");
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}
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}
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void flush_thread(void)
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{
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fpsimd_flush_thread();
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tls_thread_flush();
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flush_ptrace_hw_breakpoint(current);
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}
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@ -79,6 +79,12 @@ long compat_arm_syscall(struct pt_regs *regs)
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case __ARM_NR_compat_set_tls:
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current->thread.tp_value = regs->regs[0];
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/*
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* Protect against register corruption from context switch.
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* See comment in tls_thread_flush.
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*/
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barrier();
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asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
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return 0;
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