Merge branches 'pm-devfreq' and 'pm-sleep'
* pm-devfreq: PM / devfreq: rk3399_dmc: Remove explictly regulator_put call in .remove PM / devfreq: rockchip: add PM_DEVFREQ_EVENT dependency partial revert of "PM / devfreq: Add COMPILE_TEST for build coverage" PM / devfreq: rockchip: add devfreq driver for rk3399 dmc Documentation: bindings: add dt documentation for rk3399 dmc PM / devfreq: event: support rockchip dfi controller Documentation: bindings: add dt documentation for dfi controller PM / devfreq: event: remove duplicate devfreq_event_get_drvdata() PM / devfreq: fix Kconfig indent style PM / devfreq: Add COMPILE_TEST for build coverage PM / devfreq: exynos-ppmu: remove unneeded of_node_put() * pm-sleep: PM / Hibernate: allow hibernation with PAGE_POISONING_ZERO PM / sleep: enable suspend-to-idle even without registered suspend_ops PM / sleep: Increase default DPM watchdog timeout to 120
This commit is contained in:
Rafael J. Wysocki
commit
993eb0aeae
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@ -0,0 +1,19 @@
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* Rockchip rk3399 DFI device
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Required properties:
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- compatible: Must be "rockchip,rk3399-dfi".
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- reg: physical base address of each DFI and length of memory mapped region
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- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
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- clocks: phandles for clock specified in "clock-names" property
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- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
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||||
|
||||
Example:
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dfi: dfi@0xff630000 {
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compatible = "rockchip,rk3399-dfi";
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reg = <0x00 0xff630000 0x00 0x4000>;
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rockchip,pmu = <&pmugrf>;
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clocks = <&cru PCLK_DDR_MON>;
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clock-names = "pclk_ddr_mon";
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status = "disabled";
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};
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209
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
Normal file
209
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
Normal file
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@ -0,0 +1,209 @@
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* Rockchip rk3399 DMC(Dynamic Memory Controller) device
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Required properties:
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- compatible: Must be "rockchip,rk3399-dmc".
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- devfreq-events: Node to get DDR loading, Refer to
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Documentation/devicetree/bindings/devfreq/
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rockchip-dfi.txt
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- interrupts: The interrupt number to the CPU. The interrupt
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specifier format depends on the interrupt controller.
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It should be DCF interrupts, when DDR dvfs finish,
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it will happen.
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- clocks: Phandles for clock specified in "clock-names" property
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- clock-names : The name of clock used by the DFI, must be
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"pclk_ddr_mon";
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- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
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for details.
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- center-supply: DMC supply node.
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- status: Marks the node enabled/disabled.
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Following properties are ddr timing:
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- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h,
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it select ddr3 cl-trp-trcd type, default value
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"DDR3_DEFAULT".it must selected according to
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"Speed Bin" in ddr3 datasheet, DO NOT use
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smaller "Speed Bin" than ddr3 exactly is.
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- rockchip,pd_idle : Config the PD_IDLE value, defined the power-down
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idle period, memories are places into power-down
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mode if bus is idle for PD_IDLE DFI clocks.
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- rockchip,sr_idle : Configure the SR_IDLE value, defined the
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selfrefresh idle period, memories are places
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into self-refresh mode if bus is idle for
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SR_IDLE*1024 DFI clocks (DFI clocks freq is
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half of dram's clocks), defaule value is "0".
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- rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and
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controller clock gating idle period, memories
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are places into self-refresh mode and memory
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controller clock arg gating if bus is idle for
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sr_mc_gate_idle*1024 DFI clocks.
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- rockchip,srpd_lite_idle : Defined the self-refresh power down idle
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period, memories are places into self-refresh
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power down mode if bus is idle for
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srpd_lite_idle*1024 DFI clocks. This parameter
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is for LPDDR4 only.
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- rockchip,standby_idle : Defined the standby idle period, memories are
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places into self-refresh than controller, pi,
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phy and dram clock will gating if bus is idle
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for standby_idle * DFI clocks.
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- rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in
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MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,
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ddr3 dll will bypssed note: if dll was bypassed,
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the odt also stop working.
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- rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in
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MHz (Mega Hz), when ddr freq less than
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DRAM_DLL_DISB_FREQ, phy dll will bypssed.
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note: phy dll and phy odt are independent.
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- rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined
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the odt disable frequency in MHz (Mega Hz),
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when ddr frequency less then ddr3_odt_disb_freq,
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the odt on dram side and controller side are
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both disabled.
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- rockchip,ddr3_drv : When dram type is DDR3, this parameter define
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the dram side driver stength in ohm, default
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value is DDR3_DS_40ohm.
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- rockchip,ddr3_odt : When dram type is DDR3, this parameter define
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the dram side ODT stength in ohm, default value
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is DDR3_ODT_120ohm.
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- rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define
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the phy side CA line(incluing command line,
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address line and clock line) driver strength.
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Default value is PHY_DRV_ODT_40.
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- rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define
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the phy side DQ line(incluing DQS/DQ/DM line)
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driver strength. default value is PHY_DRV_ODT_40.
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- rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the
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phy side odt strength, default value is
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PHY_DRV_ODT_240.
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- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined
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then odt disable frequency in MHz (Mega Hz),
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when ddr frequency less then ddr3_odt_disb_freq,
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the odt on dram side and controller side are
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both disabled.
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- rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define
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the dram side driver stength in ohm, default
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value is LP3_DS_34ohm.
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- rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define
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the dram side ODT stength in ohm, default value
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is LP3_ODT_240ohm.
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- rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define
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the phy side CA line(incluing command line,
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address line and clock line) driver strength.
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default value is PHY_DRV_ODT_40.
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- rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define
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the phy side DQ line(incluing DQS/DQ/DM line)
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driver strength. default value is
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PHY_DRV_ODT_40.
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- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
|
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the phy side odt strength, default value is
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PHY_DRV_ODT_240.
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- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter
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defined the odt disable frequency in
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MHz (Mega Hz), when ddr frequency less then
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ddr3_odt_disb_freq, the odt on dram side and
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controller side are both disabled.
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- rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define
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the dram side driver stength in ohm, default
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value is LP4_PDDS_60ohm.
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- rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define
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the dram side ODT on dqs/dq line stength in ohm,
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default value is LP4_DQ_ODT_40ohm.
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- rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define
|
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the dram side ODT on ca line stength in ohm,
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default value is LP4_CA_ODT_40ohm.
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- rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define
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the phy side CA line(incluing command address
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line) driver strength. default value is
|
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PHY_DRV_ODT_40.
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||||
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- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define
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the phy side clock line and cs line driver
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strength. default value is PHY_DRV_ODT_80.
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- rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define
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the phy side DQ line(incluing DQS/DQ/DM line)
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driver strength. default value is PHY_DRV_ODT_80.
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- rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define
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the phy side odt strength, default value is
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PHY_DRV_ODT_60.
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Example:
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dmc_opp_table: dmc_opp_table {
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compatible = "operating-points-v2";
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opp00 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <900000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <666000000>;
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opp-microvolt = <900000>;
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};
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};
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dmc: dmc {
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_DDRCLK>;
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clock-names = "dmc_clk";
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operating-points-v2 = <&dmc_opp_table>;
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center-supply = <&ppvar_centerlogic>;
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upthreshold = <15>;
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downdifferential = <10>;
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rockchip,ddr3_speed_bin = <21>;
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rockchip,pd_idle = <0x40>;
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rockchip,sr_idle = <0x2>;
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rockchip,sr_mc_gate_idle = <0x3>;
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rockchip,srpd_lite_idle = <0x4>;
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rockchip,standby_idle = <0x2000>;
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rockchip,dram_dll_dis_freq = <300>;
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rockchip,phy_dll_dis_freq = <125>;
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rockchip,auto_pd_dis_freq = <666>;
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rockchip,ddr3_odt_dis_freq = <333>;
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rockchip,ddr3_drv = <DDR3_DS_40ohm>;
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rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
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rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr3_odt_dis_freq = <333>;
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rockchip,lpddr3_drv = <LP3_DS_34ohm>;
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rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
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rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr4_odt_dis_freq = <333>;
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rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
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rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
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status = "disabled";
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};
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@ -76,7 +76,7 @@ comment "DEVFREQ Drivers"
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config ARM_EXYNOS_BUS_DEVFREQ
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tristate "ARM EXYNOS Generic Memory Bus DEVFREQ Driver"
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depends on ARCH_EXYNOS
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depends on ARCH_EXYNOS || COMPILE_TEST
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select DEVFREQ_GOV_SIMPLE_ONDEMAND
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select DEVFREQ_GOV_PASSIVE
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select DEVFREQ_EVENT_EXYNOS_PPMU
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@ -91,14 +91,26 @@ config ARM_EXYNOS_BUS_DEVFREQ
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This does not yet operate with optimal voltages.
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config ARM_TEGRA_DEVFREQ
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tristate "Tegra DEVFREQ Driver"
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depends on ARCH_TEGRA_124_SOC
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select DEVFREQ_GOV_SIMPLE_ONDEMAND
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select PM_OPP
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||||
help
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This adds the DEVFREQ driver for the Tegra family of SoCs.
|
||||
It reads ACTMON counters of memory controllers and adjusts the
|
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operating frequencies and voltages with OPP support.
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tristate "Tegra DEVFREQ Driver"
|
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depends on ARCH_TEGRA_124_SOC
|
||||
select DEVFREQ_GOV_SIMPLE_ONDEMAND
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||||
select PM_OPP
|
||||
help
|
||||
This adds the DEVFREQ driver for the Tegra family of SoCs.
|
||||
It reads ACTMON counters of memory controllers and adjusts the
|
||||
operating frequencies and voltages with OPP support.
|
||||
|
||||
config ARM_RK3399_DMC_DEVFREQ
|
||||
tristate "ARM RK3399 DMC DEVFREQ Driver"
|
||||
depends on ARCH_ROCKCHIP
|
||||
select DEVFREQ_EVENT_ROCKCHIP_DFI
|
||||
select DEVFREQ_GOV_SIMPLE_ONDEMAND
|
||||
select PM_DEVFREQ_EVENT
|
||||
select PM_OPP
|
||||
help
|
||||
This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
|
||||
It sets the frequency for the memory controller and reads the usage counts
|
||||
from hardware.
|
||||
|
||||
source "drivers/devfreq/event/Kconfig"
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
|
|||
|
||||
# DEVFREQ Drivers
|
||||
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
|
||||
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
|
||||
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o
|
||||
|
||||
# DEVFREQ Event Drivers
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ if PM_DEVFREQ_EVENT
|
|||
|
||||
config DEVFREQ_EVENT_EXYNOS_NOCP
|
||||
tristate "EXYNOS NoC (Network On Chip) Probe DEVFREQ event Driver"
|
||||
depends on ARCH_EXYNOS
|
||||
depends on ARCH_EXYNOS || COMPILE_TEST
|
||||
select PM_OPP
|
||||
help
|
||||
This add the devfreq-event driver for Exynos SoC. It provides NoC
|
||||
|
|
@ -23,11 +23,18 @@ config DEVFREQ_EVENT_EXYNOS_NOCP
|
|||
|
||||
config DEVFREQ_EVENT_EXYNOS_PPMU
|
||||
tristate "EXYNOS PPMU (Platform Performance Monitoring Unit) DEVFREQ event Driver"
|
||||
depends on ARCH_EXYNOS
|
||||
depends on ARCH_EXYNOS || COMPILE_TEST
|
||||
select PM_OPP
|
||||
help
|
||||
This add the devfreq-event driver for Exynos SoC. It provides PPMU
|
||||
(Platform Performance Monitoring Unit) counters to estimate the
|
||||
utilization of each module.
|
||||
|
||||
config DEVFREQ_EVENT_ROCKCHIP_DFI
|
||||
tristate "ROCKCHIP DFI DEVFREQ event Driver"
|
||||
depends on ARCH_ROCKCHIP
|
||||
help
|
||||
This add the devfreq-event driver for Rockchip SoC. It provides DFI
|
||||
(DDR Monitor Module) driver to count ddr load.
|
||||
|
||||
endif # PM_DEVFREQ_EVENT
|
||||
|
|
|
|||
|
|
@ -2,3 +2,4 @@
|
|||
|
||||
obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP) += exynos-nocp.o
|
||||
obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
|
||||
obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
|
||||
|
|
|
|||
|
|
@ -406,8 +406,6 @@ static int of_get_devfreq_events(struct device_node *np,
|
|||
of_property_read_string(node, "event-name", &desc[j].name);
|
||||
|
||||
j++;
|
||||
|
||||
of_node_put(node);
|
||||
}
|
||||
info->desc = desc;
|
||||
|
||||
|
|
|
|||
256
drivers/devfreq/event/rockchip-dfi.c
Normal file
256
drivers/devfreq/event/rockchip-dfi.c
Normal file
|
|
@ -0,0 +1,256 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Author: Lin Huang <hl@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/devfreq-event.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#define RK3399_DMC_NUM_CH 2
|
||||
|
||||
/* DDRMON_CTRL */
|
||||
#define DDRMON_CTRL 0x04
|
||||
#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
#define LPDDR4_EN (0x10001 << 4)
|
||||
#define HARDWARE_EN (0x10001 << 3)
|
||||
#define LPDDR3_EN (0x10001 << 2)
|
||||
#define SOFTWARE_EN (0x10001 << 1)
|
||||
#define SOFTWARE_DIS (0x10000 << 1)
|
||||
#define TIME_CNT_EN (0x10001 << 0)
|
||||
|
||||
#define DDRMON_CH0_COUNT_NUM 0x28
|
||||
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
|
||||
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||
|
||||
/* pmu grf */
|
||||
#define PMUGRF_OS_REG2 0x308
|
||||
#define DDRTYPE_SHIFT 13
|
||||
#define DDRTYPE_MASK 7
|
||||
|
||||
enum {
|
||||
DDR3 = 3,
|
||||
LPDDR3 = 6,
|
||||
LPDDR4 = 7,
|
||||
UNUSED = 0xFF
|
||||
};
|
||||
|
||||
struct dmc_usage {
|
||||
u32 access;
|
||||
u32 total;
|
||||
};
|
||||
|
||||
/*
|
||||
* The dfi controller can monitor DDR load. It has an upper and lower threshold
|
||||
* for the operating points. Whenever the usage leaves these bounds an event is
|
||||
* generated to indicate the DDR frequency should be changed.
|
||||
*/
|
||||
struct rockchip_dfi {
|
||||
struct devfreq_event_dev *edev;
|
||||
struct devfreq_event_desc *desc;
|
||||
struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
u32 val;
|
||||
u32 ddr_type;
|
||||
|
||||
/* get ddr type */
|
||||
regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
|
||||
ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
|
||||
|
||||
/* clear DDRMON_CTRL setting */
|
||||
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* set ddr type to dfi */
|
||||
if (ddr_type == LPDDR3)
|
||||
writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
else if (ddr_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* enable count, use software mode */
|
||||
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||
}
|
||||
|
||||
static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
|
||||
writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
|
||||
}
|
||||
|
||||
static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
u32 tmp, max = 0;
|
||||
u32 i, busier_ch = 0;
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
|
||||
/* Find out which channel is busier */
|
||||
for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
tmp = info->ch_usage[i].access;
|
||||
if (tmp > max) {
|
||||
busier_ch = i;
|
||||
max = tmp;
|
||||
}
|
||||
}
|
||||
rockchip_dfi_start_hardware_counter(edev);
|
||||
|
||||
return busier_ch;
|
||||
}
|
||||
|
||||
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
clk_disable_unprepare(info->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(info->clk);
|
||||
if (ret) {
|
||||
dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
rockchip_dfi_start_hardware_counter(edev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
struct devfreq_event_data *edata)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int busier_ch;
|
||||
|
||||
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
||||
|
||||
edata->load_count = info->ch_usage[busier_ch].access;
|
||||
edata->total_count = info->ch_usage[busier_ch].total;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct devfreq_event_ops rockchip_dfi_ops = {
|
||||
.disable = rockchip_dfi_disable,
|
||||
.enable = rockchip_dfi_enable,
|
||||
.get_event = rockchip_dfi_get_event,
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
{ .compatible = "rockchip,rk3399-dfi" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rockchip_dfi *data;
|
||||
struct resource *res;
|
||||
struct devfreq_event_desc *desc;
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(data->regs))
|
||||
return PTR_ERR(data->regs);
|
||||
|
||||
data->clk = devm_clk_get(dev, "pclk_ddr_mon");
|
||||
if (IS_ERR(data->clk)) {
|
||||
dev_err(dev, "Cannot get the clk dmc_clk\n");
|
||||
return PTR_ERR(data->clk);
|
||||
};
|
||||
|
||||
/* try to find the optional reference to the pmu syscon */
|
||||
node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
if (node) {
|
||||
data->regmap_pmu = syscon_node_to_regmap(node);
|
||||
if (IS_ERR(data->regmap_pmu))
|
||||
return PTR_ERR(data->regmap_pmu);
|
||||
}
|
||||
data->dev = dev;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
desc->ops = &rockchip_dfi_ops;
|
||||
desc->driver_data = data;
|
||||
desc->name = np->name;
|
||||
data->desc = desc;
|
||||
|
||||
data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
||||
if (IS_ERR(data->edev)) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to add devfreq-event device\n");
|
||||
return PTR_ERR(data->edev);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rockchip_dfi_driver = {
|
||||
.probe = rockchip_dfi_probe,
|
||||
.driver = {
|
||||
.name = "rockchip-dfi",
|
||||
.of_match_table = rockchip_dfi_id_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rockchip_dfi_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Rockchip DFI driver");
|
||||
470
drivers/devfreq/rk3399_dmc.c
Normal file
470
drivers/devfreq/rk3399_dmc.c
Normal file
|
|
@ -0,0 +1,470 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Huang <hl@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/devfreq-event.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <soc/rockchip/rockchip_sip.h>
|
||||
|
||||
struct dram_timing {
|
||||
unsigned int ddr3_speed_bin;
|
||||
unsigned int pd_idle;
|
||||
unsigned int sr_idle;
|
||||
unsigned int sr_mc_gate_idle;
|
||||
unsigned int srpd_lite_idle;
|
||||
unsigned int standby_idle;
|
||||
unsigned int auto_pd_dis_freq;
|
||||
unsigned int dram_dll_dis_freq;
|
||||
unsigned int phy_dll_dis_freq;
|
||||
unsigned int ddr3_odt_dis_freq;
|
||||
unsigned int ddr3_drv;
|
||||
unsigned int ddr3_odt;
|
||||
unsigned int phy_ddr3_ca_drv;
|
||||
unsigned int phy_ddr3_dq_drv;
|
||||
unsigned int phy_ddr3_odt;
|
||||
unsigned int lpddr3_odt_dis_freq;
|
||||
unsigned int lpddr3_drv;
|
||||
unsigned int lpddr3_odt;
|
||||
unsigned int phy_lpddr3_ca_drv;
|
||||
unsigned int phy_lpddr3_dq_drv;
|
||||
unsigned int phy_lpddr3_odt;
|
||||
unsigned int lpddr4_odt_dis_freq;
|
||||
unsigned int lpddr4_drv;
|
||||
unsigned int lpddr4_dq_odt;
|
||||
unsigned int lpddr4_ca_odt;
|
||||
unsigned int phy_lpddr4_ca_drv;
|
||||
unsigned int phy_lpddr4_ck_cs_drv;
|
||||
unsigned int phy_lpddr4_dq_drv;
|
||||
unsigned int phy_lpddr4_odt;
|
||||
};
|
||||
|
||||
struct rk3399_dmcfreq {
|
||||
struct device *dev;
|
||||
struct devfreq *devfreq;
|
||||
struct devfreq_simple_ondemand_data ondemand_data;
|
||||
struct clk *dmc_clk;
|
||||
struct devfreq_event_dev *edev;
|
||||
struct mutex lock;
|
||||
struct dram_timing timing;
|
||||
|
||||
/*
|
||||
* DDR Converser of Frequency (DCF) is used to implement DDR frequency
|
||||
* conversion without the participation of CPU, we will implement and
|
||||
* control it in arm trust firmware.
|
||||
*/
|
||||
wait_queue_head_t wait_dcf_queue;
|
||||
int irq;
|
||||
int wait_dcf_flag;
|
||||
struct regulator *vdd_center;
|
||||
unsigned long rate, target_rate;
|
||||
unsigned long volt, target_volt;
|
||||
struct dev_pm_opp *curr_opp;
|
||||
};
|
||||
|
||||
static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
|
||||
u32 flags)
|
||||
{
|
||||
struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long old_clk_rate = dmcfreq->rate;
|
||||
unsigned long target_volt, target_rate;
|
||||
int err;
|
||||
|
||||
rcu_read_lock();
|
||||
opp = devfreq_recommended_opp(dev, freq, flags);
|
||||
if (IS_ERR(opp)) {
|
||||
rcu_read_unlock();
|
||||
return PTR_ERR(opp);
|
||||
}
|
||||
|
||||
target_rate = dev_pm_opp_get_freq(opp);
|
||||
target_volt = dev_pm_opp_get_voltage(opp);
|
||||
|
||||
dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
|
||||
dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
|
||||
|
||||
rcu_read_unlock();
|
||||
|
||||
if (dmcfreq->rate == target_rate)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&dmcfreq->lock);
|
||||
|
||||
/*
|
||||
* If frequency scaling from low to high, adjust voltage first.
|
||||
* If frequency scaling from high to low, adjust frequency first.
|
||||
*/
|
||||
if (old_clk_rate < target_rate) {
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot to set voltage %lu uV\n",
|
||||
target_volt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
dmcfreq->wait_dcf_flag = 1;
|
||||
|
||||
err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot to set frequency %lu (%d)\n",
|
||||
target_rate, err);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait until bcf irq happen, it means freq scaling finish in
|
||||
* arm trust firmware, use 100ms as timeout time.
|
||||
*/
|
||||
if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
|
||||
!dmcfreq->wait_dcf_flag, HZ / 10))
|
||||
dev_warn(dev, "Timeout waiting for dcf interrupt\n");
|
||||
|
||||
/*
|
||||
* Check the dpll rate,
|
||||
* There only two result we will get,
|
||||
* 1. Ddr frequency scaling fail, we still get the old rate.
|
||||
* 2. Ddr frequency scaling sucessful, we get the rate we set.
|
||||
*/
|
||||
dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
|
||||
|
||||
/* If get the incorrect rate, set voltage to old value. */
|
||||
if (dmcfreq->rate != target_rate) {
|
||||
dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
|
||||
Current frequency %lu\n", target_rate, dmcfreq->rate);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
} else if (old_clk_rate > target_rate)
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err)
|
||||
dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
|
||||
|
||||
dmcfreq->curr_opp = opp;
|
||||
out:
|
||||
mutex_unlock(&dmcfreq->lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rk3399_dmcfreq_get_dev_status(struct device *dev,
|
||||
struct devfreq_dev_status *stat)
|
||||
{
|
||||
struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct devfreq_event_data edata;
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_get_event(dmcfreq->edev, &edata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
stat->current_frequency = dmcfreq->rate;
|
||||
stat->busy_time = edata.load_count;
|
||||
stat->total_time = edata.total_count;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
|
||||
{
|
||||
struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
|
||||
*freq = dmcfreq->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
|
||||
.polling_ms = 200,
|
||||
.target = rk3399_dmcfreq_target,
|
||||
.get_dev_status = rk3399_dmcfreq_get_dev_status,
|
||||
.get_cur_freq = rk3399_dmcfreq_get_cur_freq,
|
||||
};
|
||||
|
||||
static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
|
||||
{
|
||||
struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_disable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to disable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_suspend_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to suspend the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
|
||||
{
|
||||
struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_enable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_resume_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to resume the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
|
||||
rk3399_dmcfreq_resume);
|
||||
|
||||
static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct rk3399_dmcfreq *dmcfreq = dev_id;
|
||||
struct arm_smccc_res res;
|
||||
|
||||
dmcfreq->wait_dcf_flag = 0;
|
||||
wake_up(&dmcfreq->wait_dcf_queue);
|
||||
|
||||
/* Clear the DCF interrupt */
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
|
||||
0, 0, 0, 0, &res);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int of_get_ddr_timings(struct dram_timing *timing,
|
||||
struct device_node *np)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
|
||||
&timing->ddr3_speed_bin);
|
||||
ret |= of_property_read_u32(np, "rockchip,pd_idle",
|
||||
&timing->pd_idle);
|
||||
ret |= of_property_read_u32(np, "rockchip,sr_idle",
|
||||
&timing->sr_idle);
|
||||
ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
|
||||
&timing->sr_mc_gate_idle);
|
||||
ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
|
||||
&timing->srpd_lite_idle);
|
||||
ret |= of_property_read_u32(np, "rockchip,standby_idle",
|
||||
&timing->standby_idle);
|
||||
ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
|
||||
&timing->auto_pd_dis_freq);
|
||||
ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
|
||||
&timing->dram_dll_dis_freq);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
|
||||
&timing->phy_dll_dis_freq);
|
||||
ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
|
||||
&timing->ddr3_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
|
||||
&timing->ddr3_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
|
||||
&timing->ddr3_odt);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
|
||||
&timing->phy_ddr3_ca_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
|
||||
&timing->phy_ddr3_dq_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
|
||||
&timing->phy_ddr3_odt);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
|
||||
&timing->lpddr3_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
|
||||
&timing->lpddr3_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
|
||||
&timing->lpddr3_odt);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
|
||||
&timing->phy_lpddr3_ca_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
|
||||
&timing->phy_lpddr3_dq_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
|
||||
&timing->phy_lpddr3_odt);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
|
||||
&timing->lpddr4_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
|
||||
&timing->lpddr4_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
|
||||
&timing->lpddr4_dq_odt);
|
||||
ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
|
||||
&timing->lpddr4_ca_odt);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
|
||||
&timing->phy_lpddr4_ca_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
|
||||
&timing->phy_lpddr4_ck_cs_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
|
||||
&timing->phy_lpddr4_dq_drv);
|
||||
ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
|
||||
&timing->phy_lpddr4_odt);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3399_dmcfreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rk3399_dmcfreq *data;
|
||||
int ret, irq, index, size;
|
||||
uint32_t *timing;
|
||||
struct dev_pm_opp *opp;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&data->lock);
|
||||
|
||||
data->vdd_center = devm_regulator_get(dev, "center");
|
||||
if (IS_ERR(data->vdd_center)) {
|
||||
dev_err(dev, "Cannot get the regulator \"center\"\n");
|
||||
return PTR_ERR(data->vdd_center);
|
||||
}
|
||||
|
||||
data->dmc_clk = devm_clk_get(dev, "dmc_clk");
|
||||
if (IS_ERR(data->dmc_clk)) {
|
||||
dev_err(dev, "Cannot get the clk dmc_clk\n");
|
||||
return PTR_ERR(data->dmc_clk);
|
||||
};
|
||||
|
||||
data->irq = irq;
|
||||
ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
|
||||
dev_name(dev), data);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to request dmc irq: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
init_waitqueue_head(&data->wait_dcf_queue);
|
||||
data->wait_dcf_flag = 0;
|
||||
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
|
||||
if (IS_ERR(data->edev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ret = devfreq_event_enable_edev(data->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Get dram timing and pass it to arm trust firmware,
|
||||
* the dram drvier in arm trust firmware will get these
|
||||
* timing and to do dram initial.
|
||||
*/
|
||||
if (!of_get_ddr_timings(&data->timing, np)) {
|
||||
timing = &data->timing.ddr3_speed_bin;
|
||||
size = sizeof(struct dram_timing) / 4;
|
||||
for (index = 0; index < size; index++) {
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0) {
|
||||
dev_err(dev, "Failed to set dram param: %ld\n",
|
||||
res.a0);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_INIT,
|
||||
0, 0, 0, 0, &res);
|
||||
|
||||
/*
|
||||
* We add a devfreq driver to our parent since it has a device tree node
|
||||
* with operating points.
|
||||
*/
|
||||
if (dev_pm_opp_of_add_table(dev)) {
|
||||
dev_err(dev, "Invalid operating-points in device tree.\n");
|
||||
rcu_read_unlock();
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "upthreshold",
|
||||
&data->ondemand_data.upthreshold);
|
||||
of_property_read_u32(np, "downdifferential",
|
||||
&data->ondemand_data.downdifferential);
|
||||
|
||||
data->rate = clk_get_rate(data->dmc_clk);
|
||||
|
||||
rcu_read_lock();
|
||||
opp = devfreq_recommended_opp(dev, &data->rate, 0);
|
||||
if (IS_ERR(opp)) {
|
||||
rcu_read_unlock();
|
||||
return PTR_ERR(opp);
|
||||
}
|
||||
rcu_read_unlock();
|
||||
data->curr_opp = opp;
|
||||
|
||||
rk3399_devfreq_dmc_profile.initial_freq = data->rate;
|
||||
|
||||
data->devfreq = devfreq_add_device(dev,
|
||||
&rk3399_devfreq_dmc_profile,
|
||||
"simple_ondemand",
|
||||
&data->ondemand_data);
|
||||
if (IS_ERR(data->devfreq))
|
||||
return PTR_ERR(data->devfreq);
|
||||
devm_devfreq_register_opp_notifier(dev, data->devfreq);
|
||||
|
||||
data->dev = dev;
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3399-dmc" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver rk3399_dmcfreq_driver = {
|
||||
.probe = rk3399_dmcfreq_probe,
|
||||
.driver = {
|
||||
.name = "rk3399-dmc-freq",
|
||||
.pm = &rk3399_dmcfreq_pm,
|
||||
.of_match_table = rk3399dmc_devfreq_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rk3399_dmcfreq_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
|
||||
|
|
@ -148,11 +148,6 @@ static inline int devfreq_event_reset_event(struct devfreq_event_dev *edev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
|
||||
{
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static inline struct devfreq_event_dev *devfreq_event_get_edev_by_phandle(
|
||||
struct device *dev, int index)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -245,6 +245,7 @@ static inline bool idle_should_freeze(void)
|
|||
return unlikely(suspend_freeze_state == FREEZE_STATE_ENTER);
|
||||
}
|
||||
|
||||
extern void __init pm_states_init(void);
|
||||
extern void freeze_set_ops(const struct platform_freeze_ops *ops);
|
||||
extern void freeze_wake(void);
|
||||
|
||||
|
|
@ -279,6 +280,7 @@ static inline bool pm_resume_via_firmware(void) { return false; }
|
|||
static inline void suspend_set_ops(const struct platform_suspend_ops *ops) {}
|
||||
static inline int pm_suspend(suspend_state_t state) { return -ENOSYS; }
|
||||
static inline bool idle_should_freeze(void) { return false; }
|
||||
static inline void __init pm_states_init(void) {}
|
||||
static inline void freeze_set_ops(const struct platform_freeze_ops *ops) {}
|
||||
static inline void freeze_wake(void) {}
|
||||
#endif /* !CONFIG_SUSPEND */
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ config PM_SLEEP_DEBUG
|
|||
|
||||
config DPM_WATCHDOG
|
||||
bool "Device suspend/resume watchdog"
|
||||
depends on PM_DEBUG && PSTORE
|
||||
depends on PM_DEBUG && PSTORE && EXPERT
|
||||
---help---
|
||||
Sets up a watchdog timer to capture drivers that are
|
||||
locked up attempting to suspend/resume a device.
|
||||
|
|
@ -197,7 +197,7 @@ config DPM_WATCHDOG
|
|||
config DPM_WATCHDOG_TIMEOUT
|
||||
int "Watchdog timeout in seconds"
|
||||
range 1 120
|
||||
default 60
|
||||
default 120
|
||||
depends on DPM_WATCHDOG
|
||||
|
||||
config PM_TRACE
|
||||
|
|
|
|||
|
|
@ -306,8 +306,10 @@ static int create_image(int platform_mode)
|
|||
if (error)
|
||||
printk(KERN_ERR "PM: Error %d creating hibernation image\n",
|
||||
error);
|
||||
if (!in_suspend)
|
||||
if (!in_suspend) {
|
||||
events_check_enabled = false;
|
||||
clear_free_pages();
|
||||
}
|
||||
|
||||
platform_leave(platform_mode);
|
||||
|
||||
|
|
@ -1189,22 +1191,6 @@ static int __init nohibernate_setup(char *str)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int __init page_poison_nohibernate_setup(char *str)
|
||||
{
|
||||
#ifdef CONFIG_PAGE_POISONING_ZERO
|
||||
/*
|
||||
* The zeroing option for page poison skips the checks on alloc.
|
||||
* since hibernation doesn't save free pages there's no way to
|
||||
* guarantee the pages will still be zeroed.
|
||||
*/
|
||||
if (!strcmp(str, "on")) {
|
||||
pr_info("Disabling hibernation due to page poisoning\n");
|
||||
return nohibernate_setup(str);
|
||||
}
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("noresume", noresume_setup);
|
||||
__setup("resume_offset=", resume_offset_setup);
|
||||
__setup("resume=", resume_setup);
|
||||
|
|
@ -1212,4 +1198,3 @@ __setup("hibernate=", hibernate_setup);
|
|||
__setup("resumewait", resumewait_setup);
|
||||
__setup("resumedelay=", resumedelay_setup);
|
||||
__setup("nohibernate", nohibernate_setup);
|
||||
__setup("page_poison=", page_poison_nohibernate_setup);
|
||||
|
|
|
|||
|
|
@ -644,6 +644,7 @@ static int __init pm_init(void)
|
|||
return error;
|
||||
hibernate_image_size_init();
|
||||
hibernate_reserved_size_init();
|
||||
pm_states_init();
|
||||
power_kobj = kobject_create_and_add("power", NULL);
|
||||
if (!power_kobj)
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -110,6 +110,8 @@ extern int create_basic_memory_bitmaps(void);
|
|||
extern void free_basic_memory_bitmaps(void);
|
||||
extern int hibernate_preallocate_memory(void);
|
||||
|
||||
extern void clear_free_pages(void);
|
||||
|
||||
/**
|
||||
* Auxiliary structure used for reading the snapshot image data and
|
||||
* metadata from and writing them to the list of page backup entries
|
||||
|
|
|
|||
|
|
@ -1132,6 +1132,28 @@ void free_basic_memory_bitmaps(void)
|
|||
pr_debug("PM: Basic memory bitmaps freed\n");
|
||||
}
|
||||
|
||||
void clear_free_pages(void)
|
||||
{
|
||||
#ifdef CONFIG_PAGE_POISONING_ZERO
|
||||
struct memory_bitmap *bm = free_pages_map;
|
||||
unsigned long pfn;
|
||||
|
||||
if (WARN_ON(!(free_pages_map)))
|
||||
return;
|
||||
|
||||
memory_bm_position_reset(bm);
|
||||
pfn = memory_bm_next_pfn(bm);
|
||||
while (pfn != BM_END_OF_MAP) {
|
||||
if (pfn_valid(pfn))
|
||||
clear_highpage(pfn_to_page(pfn));
|
||||
|
||||
pfn = memory_bm_next_pfn(bm);
|
||||
}
|
||||
memory_bm_position_reset(bm);
|
||||
pr_info("PM: free pages cleared after restore\n");
|
||||
#endif /* PAGE_POISONING_ZERO */
|
||||
}
|
||||
|
||||
/**
|
||||
* snapshot_additional_pages - Estimate the number of extra pages needed.
|
||||
* @zone: Memory zone to carry out the computation for.
|
||||
|
|
|
|||
|
|
@ -118,10 +118,18 @@ static bool valid_state(suspend_state_t state)
|
|||
*/
|
||||
static bool relative_states;
|
||||
|
||||
void __init pm_states_init(void)
|
||||
{
|
||||
/*
|
||||
* freeze state should be supported even without any suspend_ops,
|
||||
* initialize pm_states accordingly here
|
||||
*/
|
||||
pm_states[PM_SUSPEND_FREEZE] = pm_labels[relative_states ? 0 : 2];
|
||||
}
|
||||
|
||||
static int __init sleep_states_setup(char *str)
|
||||
{
|
||||
relative_states = !strncmp(str, "1", 1);
|
||||
pm_states[PM_SUSPEND_FREEZE] = pm_labels[relative_states ? 0 : 2];
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -211,7 +219,7 @@ static int platform_suspend_begin(suspend_state_t state)
|
|||
{
|
||||
if (state == PM_SUSPEND_FREEZE && freeze_ops && freeze_ops->begin)
|
||||
return freeze_ops->begin();
|
||||
else if (suspend_ops->begin)
|
||||
else if (suspend_ops && suspend_ops->begin)
|
||||
return suspend_ops->begin(state);
|
||||
else
|
||||
return 0;
|
||||
|
|
@ -221,7 +229,7 @@ static void platform_resume_end(suspend_state_t state)
|
|||
{
|
||||
if (state == PM_SUSPEND_FREEZE && freeze_ops && freeze_ops->end)
|
||||
freeze_ops->end();
|
||||
else if (suspend_ops->end)
|
||||
else if (suspend_ops && suspend_ops->end)
|
||||
suspend_ops->end();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -76,8 +76,6 @@ config PAGE_POISONING_ZERO
|
|||
no longer necessary to write zeros when GFP_ZERO is used on
|
||||
allocation.
|
||||
|
||||
Enabling page poisoning with this option will disable hibernation
|
||||
|
||||
If unsure, say N
|
||||
bool
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue