[ARM] 3500/1: fix PXA27x DMA allocation priority
Patch from Nicolas Pitre Intel PXA27x developers manual section 5.4.1.1 lists a priority distribution for the DMA channels differently than what the code currently assumes. This patch fixes that. Noticed by Simon Vogl <vogl@soft.uni-linz.ac.at> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -45,23 +45,16 @@ int pxa_request_dma (char *name, pxa_dma_prio prio,
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local_irq_save(flags);
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/* try grabbing a DMA channel with the requested priority */
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for (i = prio; i < prio + PXA_DMA_NBCH(prio); i++) {
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if (!dma_channels[i].name) {
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found = 1;
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break;
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}
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}
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if (!found) {
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/* requested prio group is full, try hier priorities */
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for (i = prio-1; i >= 0; i--) {
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do {
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/* try grabbing a DMA channel with the requested priority */
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pxa_for_each_dma_prio (i, prio) {
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if (!dma_channels[i].name) {
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found = 1;
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break;
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}
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}
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}
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/* if requested prio group is full, try a hier priority */
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} while (!found && prio--);
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if (found) {
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DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
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@ -24,27 +24,29 @@ typedef struct pxa_dma_desc {
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volatile u32 dcmd; /* DCMD value for the current transfer */
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} pxa_dma_desc;
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typedef enum {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 1,
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DMA_PRIO_LOW = 2
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} pxa_dma_prio;
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#if defined(CONFIG_PXA27x)
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#define PXA_DMA_CHANNELS 32
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#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 16 : 8)
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typedef enum {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 8,
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DMA_PRIO_LOW = 16
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} pxa_dma_prio;
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#define pxa_for_each_dma_prio(ch, prio) \
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for ( \
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ch = prio * 4; \
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ch != (4 << prio) + 16; \
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ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
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)
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#elif defined(CONFIG_PXA25x)
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#define PXA_DMA_CHANNELS 16
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#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 8 : 4)
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typedef enum {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 4,
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DMA_PRIO_LOW = 8
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} pxa_dma_prio;
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#define pxa_for_each_dma_prio(ch, prio) \
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for (ch = prio * 4; ch != (4 << prio); ch++)
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#endif
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