clk: samsung: Add S5PV210 Audio Subsystem clock driver
This patch adds a driver for clock controller being a part of Audio Subsystem present on S5PV210 and compatible SoCs. It is used to provide clocks for other IP blocks of this subsystem. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>wifi-calibration
Tomasz Figa
Kukjin Kim
parent
32726d2d55
commit
9978f28f69
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@ -0,0 +1,53 @@
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* Samsung Audio Subsystem Clock Controller
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The Samsung Audio Subsystem clock controller generates and supplies clocks
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to Audio Subsystem block available in the S5PV210 and compatible SoCs.
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Required Properties:
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- compatible: should be "samsung,s5pv210-audss-clock".
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- reg: physical base address and length of the controller's register set.
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- #clock-cells: should be 1.
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- clocks:
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- hclk: AHB bus clock of the Audio Subsystem.
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- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
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not specified (i.e. xusbxti is used for PLL reference), it is fixed to
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a clock named "xxti".
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- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
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- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
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specified, it is fixed to a clock named "iiscdclk0".
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- sclk_audio0: Audio bus clock, parent of mout_i2s.
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- clock-names: Aliases for the above clocks. They should be "hclk",
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"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
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tree sources.
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Example: Clock controller node.
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clk_audss: clock-controller@c0900000 {
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compatible = "samsung,s5pv210-audss-clock";
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reg = <0xc0900000 0x1000>;
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#clock-cells = <1>;
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clock-names = "hclk", "xxti",
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"fout_epll", "sclk_audio0";
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clocks = <&clocks DOUT_HCLKP>, <&xxti>,
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<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
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};
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Example: I2S controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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i2s0: i2s@03830000 {
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/* ... */
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clock-names = "iis", "i2s_opclk0",
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"i2s_opclk1";
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clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
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<&clk_audss CLK_DOUT_AUD_BUS>;
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/* ... */
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};
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@ -16,4 +16,4 @@ obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
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obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
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obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
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obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
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obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o
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obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
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@ -0,0 +1,241 @@
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/*
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* Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com>
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*
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* Based on Exynos Audio Subsystem Clock Controller driver:
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Padmavathi Venna <padma.v@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
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*/
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/s5pv210-audss.h>
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static DEFINE_SPINLOCK(lock);
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static struct clk **clk_table;
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static void __iomem *reg_base;
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static struct clk_onecell_data clk_data;
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#define ASS_CLK_SRC 0x0
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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#ifdef CONFIG_PM_SLEEP
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static unsigned long reg_save[][2] = {
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{ASS_CLK_SRC, 0},
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{ASS_CLK_DIV, 0},
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{ASS_CLK_GATE, 0},
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};
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static int s5pv210_audss_clk_suspend(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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reg_save[i][1] = readl(reg_base + reg_save[i][0]);
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return 0;
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}
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static void s5pv210_audss_clk_resume(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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writel(reg_save[i][1], reg_base + reg_save[i][0]);
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}
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static struct syscore_ops s5pv210_audss_clk_syscore_ops = {
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.suspend = s5pv210_audss_clk_suspend,
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.resume = s5pv210_audss_clk_resume,
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};
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#endif /* CONFIG_PM_SLEEP */
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/* register s5pv210_audss clocks */
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static int s5pv210_audss_clk_probe(struct platform_device *pdev)
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{
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int i, ret = 0;
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struct resource *res;
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const char *mout_audss_p[2];
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const char *mout_i2s_p[3];
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const char *hclk_p;
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struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(reg_base)) {
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dev_err(&pdev->dev, "failed to map audss registers\n");
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return PTR_ERR(reg_base);
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}
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clk_table = devm_kzalloc(&pdev->dev,
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sizeof(struct clk *) * AUDSS_MAX_CLKS,
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GFP_KERNEL);
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if (!clk_table)
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return -ENOMEM;
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clk_data.clks = clk_table;
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clk_data.clk_num = AUDSS_MAX_CLKS;
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hclk = devm_clk_get(&pdev->dev, "hclk");
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if (IS_ERR(hclk)) {
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dev_err(&pdev->dev, "failed to get hclk clock\n");
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return PTR_ERR(hclk);
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}
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pll_in = devm_clk_get(&pdev->dev, "fout_epll");
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if (IS_ERR(pll_in)) {
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dev_err(&pdev->dev, "failed to get fout_epll clock\n");
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return PTR_ERR(pll_in);
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}
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sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
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if (IS_ERR(sclk_audio)) {
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dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
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return PTR_ERR(sclk_audio);
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}
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/* iiscdclk0 is an optional external I2S codec clock */
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cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
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pll_ref = devm_clk_get(&pdev->dev, "xxti");
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if (!IS_ERR(pll_ref))
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mout_audss_p[0] = __clk_get_name(pll_ref);
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else
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mout_audss_p[0] = "xxti";
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mout_audss_p[1] = __clk_get_name(pll_in);
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clk_table[CLK_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
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mout_audss_p, ARRAY_SIZE(mout_audss_p),
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CLK_SET_RATE_NO_REPARENT,
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reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
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mout_i2s_p[0] = "mout_audss";
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if (!IS_ERR(cdclk))
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mout_i2s_p[1] = __clk_get_name(cdclk);
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else
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mout_i2s_p[1] = "iiscdclk0";
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mout_i2s_p[2] = __clk_get_name(sclk_audio);
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clk_table[CLK_MOUT_I2S_A] = clk_register_mux(NULL, "mout_i2s_audss",
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mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
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CLK_SET_RATE_NO_REPARENT,
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reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
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clk_table[CLK_DOUT_AUD_BUS] = clk_register_divider(NULL,
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"dout_aud_bus", "mout_audss", 0,
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reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
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clk_table[CLK_DOUT_I2S_A] = clk_register_divider(NULL, "dout_i2s_audss",
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"mout_i2s_audss", 0, reg_base + ASS_CLK_DIV,
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4, 4, 0, &lock);
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clk_table[CLK_I2S] = clk_register_gate(NULL, "i2s_audss",
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"dout_i2s_audss", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 6, 0, &lock);
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hclk_p = __clk_get_name(hclk);
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clk_table[CLK_HCLK_I2S] = clk_register_gate(NULL, "hclk_i2s_audss",
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hclk_p, CLK_IGNORE_UNUSED,
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reg_base + ASS_CLK_GATE, 5, 0, &lock);
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clk_table[CLK_HCLK_UART] = clk_register_gate(NULL, "hclk_uart_audss",
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hclk_p, CLK_IGNORE_UNUSED,
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reg_base + ASS_CLK_GATE, 4, 0, &lock);
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clk_table[CLK_HCLK_HWA] = clk_register_gate(NULL, "hclk_hwa_audss",
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hclk_p, CLK_IGNORE_UNUSED,
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reg_base + ASS_CLK_GATE, 3, 0, &lock);
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clk_table[CLK_HCLK_DMA] = clk_register_gate(NULL, "hclk_dma_audss",
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hclk_p, CLK_IGNORE_UNUSED,
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reg_base + ASS_CLK_GATE, 2, 0, &lock);
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clk_table[CLK_HCLK_BUF] = clk_register_gate(NULL, "hclk_buf_audss",
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hclk_p, CLK_IGNORE_UNUSED,
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reg_base + ASS_CLK_GATE, 1, 0, &lock);
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clk_table[CLK_HCLK_RP] = clk_register_gate(NULL, "hclk_rp_audss",
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hclk_p, CLK_IGNORE_UNUSED,
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reg_base + ASS_CLK_GATE, 0, 0, &lock);
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for (i = 0; i < clk_data.clk_num; i++) {
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if (IS_ERR(clk_table[i])) {
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dev_err(&pdev->dev, "failed to register clock %d\n", i);
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ret = PTR_ERR(clk_table[i]);
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goto unregister;
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}
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}
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ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
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&clk_data);
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if (ret) {
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dev_err(&pdev->dev, "failed to add clock provider\n");
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goto unregister;
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}
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&s5pv210_audss_clk_syscore_ops);
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#endif
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return 0;
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unregister:
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for (i = 0; i < clk_data.clk_num; i++) {
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if (!IS_ERR(clk_table[i]))
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clk_unregister(clk_table[i]);
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}
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return ret;
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}
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static int s5pv210_audss_clk_remove(struct platform_device *pdev)
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{
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int i;
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of_clk_del_provider(pdev->dev.of_node);
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for (i = 0; i < clk_data.clk_num; i++) {
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if (!IS_ERR(clk_table[i]))
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clk_unregister(clk_table[i]);
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}
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return 0;
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}
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static const struct of_device_id s5pv210_audss_clk_of_match[] = {
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{ .compatible = "samsung,s5pv210-audss-clock", },
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{},
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};
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static struct platform_driver s5pv210_audss_clk_driver = {
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.driver = {
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.name = "s5pv210-audss-clk",
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.owner = THIS_MODULE,
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.of_match_table = s5pv210_audss_clk_of_match,
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},
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.probe = s5pv210_audss_clk_probe,
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.remove = s5pv210_audss_clk_remove,
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};
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static int __init s5pv210_audss_clk_init(void)
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{
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return platform_driver_register(&s5pv210_audss_clk_driver);
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}
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core_initcall(s5pv210_audss_clk_init);
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static void __exit s5pv210_audss_clk_exit(void)
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{
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platform_driver_unregister(&s5pv210_audss_clk_driver);
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}
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module_exit(s5pv210_audss_clk_exit);
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MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
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MODULE_DESCRIPTION("S5PV210 Audio Subsystem Clock Controller");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:s5pv210-audss-clk");
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This header provides constants for Samsung audio subsystem
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* clock controller.
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*
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* The constants defined in this header are being used in dts
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* and s5pv210 audss driver.
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*/
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#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
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#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
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#define CLK_MOUT_AUDSS 0
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#define CLK_MOUT_I2S_A 1
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#define CLK_DOUT_AUD_BUS 2
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#define CLK_DOUT_I2S_A 3
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#define CLK_I2S 4
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#define CLK_HCLK_I2S 5
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#define CLK_HCLK_UART 6
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#define CLK_HCLK_HWA 7
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#define CLK_HCLK_DMA 8
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#define CLK_HCLK_BUF 9
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#define CLK_HCLK_RP 10
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#define AUDSS_MAX_CLKS 11
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#endif
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