[SPARC64]: Fix sparse errors in arch/sparc64/kernel/traps.c
Add 'UL' markers to DCU_* macros. Declare C functions called from assembler in entry.h Declare C functions called from within the sparc64 arch code in include/asm-sparc64/*.h headers as appropriate. Remove unused routines in traps.c Signed-off-by: David S. Miller <davem@davemloft.net>wifi-calibration
David S. Miller
parent
3d5ae6b69e
commit
99cd220133
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@ -2,6 +2,7 @@
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#define _ENTRY_H
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#include <linux/init.h>
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#include <linux/types.h>
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extern char *sparc_cpu_type;
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extern char *sparc_fpu_type;
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@ -12,4 +13,144 @@ extern void __init boot_cpu_id_too_large(int cpu);
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extern unsigned int dcache_parity_tl1_occurred;
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extern unsigned int icache_parity_tl1_occurred;
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extern void bad_trap_tl1(struct pt_regs *regs, long lvl);
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extern void do_fpe_common(struct pt_regs *regs);
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extern void do_fpieee(struct pt_regs *regs);
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extern void do_fpother(struct pt_regs *regs);
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extern void do_tof(struct pt_regs *regs);
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extern void do_div0(struct pt_regs *regs);
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extern void do_illegal_instruction(struct pt_regs *regs);
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extern void mem_address_unaligned(struct pt_regs *regs,
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unsigned long sfar,
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unsigned long sfsr);
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extern void sun4v_do_mna(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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extern void do_privop(struct pt_regs *regs);
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extern void do_privact(struct pt_regs *regs);
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extern void do_cee(struct pt_regs *regs);
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extern void do_cee_tl1(struct pt_regs *regs);
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extern void do_dae_tl1(struct pt_regs *regs);
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extern void do_iae_tl1(struct pt_regs *regs);
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extern void do_div0_tl1(struct pt_regs *regs);
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extern void do_fpdis_tl1(struct pt_regs *regs);
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extern void do_fpieee_tl1(struct pt_regs *regs);
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extern void do_fpother_tl1(struct pt_regs *regs);
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extern void do_ill_tl1(struct pt_regs *regs);
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extern void do_irq_tl1(struct pt_regs *regs);
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extern void do_lddfmna_tl1(struct pt_regs *regs);
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extern void do_stdfmna_tl1(struct pt_regs *regs);
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extern void do_paw(struct pt_regs *regs);
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extern void do_paw_tl1(struct pt_regs *regs);
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extern void do_vaw(struct pt_regs *regs);
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extern void do_vaw_tl1(struct pt_regs *regs);
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extern void do_tof_tl1(struct pt_regs *regs);
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extern void do_getpsr(struct pt_regs *regs);
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extern void spitfire_insn_access_exception(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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extern void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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extern void spitfire_data_access_exception(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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extern void spitfire_data_access_exception_tl1(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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extern void spitfire_access_error(struct pt_regs *regs,
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unsigned long status_encoded,
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unsigned long afar);
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extern void cheetah_fecc_handler(struct pt_regs *regs,
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unsigned long afsr,
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unsigned long afar);
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extern void cheetah_cee_handler(struct pt_regs *regs,
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unsigned long afsr,
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unsigned long afar);
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extern void cheetah_deferred_handler(struct pt_regs *regs,
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unsigned long afsr,
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unsigned long afar);
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extern void cheetah_plus_parity_error(int type, struct pt_regs *regs);
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extern void sun4v_insn_access_exception(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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extern void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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extern void sun4v_data_access_exception(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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extern void sun4v_data_access_exception_tl1(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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extern void sun4v_resum_error(struct pt_regs *regs,
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unsigned long offset);
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extern void sun4v_resum_overflow(struct pt_regs *regs);
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extern void sun4v_nonresum_error(struct pt_regs *regs,
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unsigned long offset);
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extern void sun4v_nonresum_overflow(struct pt_regs *regs);
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extern unsigned long sun4v_err_itlb_vaddr;
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extern unsigned long sun4v_err_itlb_ctx;
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extern unsigned long sun4v_err_itlb_pte;
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extern unsigned long sun4v_err_itlb_error;
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extern void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
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extern unsigned long sun4v_err_dtlb_vaddr;
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extern unsigned long sun4v_err_dtlb_ctx;
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extern unsigned long sun4v_err_dtlb_pte;
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extern unsigned long sun4v_err_dtlb_error;
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extern void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
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extern void hypervisor_tlbop_error(unsigned long err,
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unsigned long op);
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extern void hypervisor_tlbop_error_xcall(unsigned long err,
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unsigned long op);
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/* WARNING: The error trap handlers in assembly know the precise
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* layout of the following structure.
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*
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* C-level handlers in traps.c use this information to log the
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* error and then determine how to recover (if possible).
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*/
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struct cheetah_err_info {
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/*0x00*/u64 afsr;
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/*0x08*/u64 afar;
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/* D-cache state */
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/*0x10*/u64 dcache_data[4]; /* The actual data */
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/*0x30*/u64 dcache_index; /* D-cache index */
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/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
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/*0x40*/u64 dcache_utag; /* D-cache microtag */
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/*0x48*/u64 dcache_stag; /* D-cache snooptag */
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/* I-cache state */
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/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
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/*0x90*/u64 icache_index; /* I-cache index */
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/*0x98*/u64 icache_tag; /* I-cache phys tag */
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/*0xa0*/u64 icache_utag; /* I-cache microtag */
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/*0xa8*/u64 icache_stag; /* I-cache snooptag */
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/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
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/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
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/* E-cache state */
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/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
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/*0xe0*/u64 ecache_index; /* E-cache index */
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/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
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/*0xf0*/u64 __pad[32 - 30];
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};
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#define CHAFSR_INVALID ((u64)-1L)
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/* This is allocated at boot time based upon the largest hardware
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* cpu ID in the system. We allocate two entries per cpu, one for
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* TL==0 logging and one for TL >= 1 logging.
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*/
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extern struct cheetah_err_info *cheetah_error_log;
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#endif /* _ENTRY_H */
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@ -42,6 +42,7 @@
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#endif
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#include <asm/prom.h>
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#include "entry.h"
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/* When an irrecoverable trap occurs at tl > 0, the trap entry
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* code logs the trap state registers at every level in the trap
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@ -77,11 +78,6 @@ static void dump_tl1_traplog(struct tl1_traplog *p)
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}
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}
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void do_call_debug(struct pt_regs *regs)
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{
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notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
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}
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void bad_trap(struct pt_regs *regs, long lvl)
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{
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char buffer[32];
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@ -550,41 +546,6 @@ static unsigned long ecache_flush_physbase;
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static unsigned long ecache_flush_linesize;
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static unsigned long ecache_flush_size;
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/* WARNING: The error trap handlers in assembly know the precise
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* layout of the following structure.
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*
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* C-level handlers below use this information to log the error
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* and then determine how to recover (if possible).
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*/
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struct cheetah_err_info {
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/*0x00*/u64 afsr;
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/*0x08*/u64 afar;
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/* D-cache state */
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/*0x10*/u64 dcache_data[4]; /* The actual data */
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/*0x30*/u64 dcache_index; /* D-cache index */
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/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
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/*0x40*/u64 dcache_utag; /* D-cache microtag */
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/*0x48*/u64 dcache_stag; /* D-cache snooptag */
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/* I-cache state */
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/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
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/*0x90*/u64 icache_index; /* I-cache index */
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/*0x98*/u64 icache_tag; /* I-cache phys tag */
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/*0xa0*/u64 icache_utag; /* I-cache microtag */
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/*0xa8*/u64 icache_stag; /* I-cache snooptag */
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/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
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/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
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/* E-cache state */
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/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
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/*0xe0*/u64 ecache_index; /* E-cache index */
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/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
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/*0xf0*/u64 __pad[32 - 30];
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};
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#define CHAFSR_INVALID ((u64)-1L)
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/* This table is ordered in priority of errors and matches the
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* AFAR overwrite policy as well.
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*/
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@ -758,10 +719,6 @@ static struct afsr_error_table __jalapeno_error_table[] = {
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static struct afsr_error_table *cheetah_error_table;
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static unsigned long cheetah_afsr_errors;
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/* This is allocated at boot time based upon the largest hardware
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* cpu ID in the system. We allocate two entries per cpu, one for
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* TL==0 logging and one for TL >= 1 logging.
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*/
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struct cheetah_err_info *cheetah_error_log;
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static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
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@ -2102,7 +2059,7 @@ void do_div0(struct pt_regs *regs)
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force_sig_info(SIGFPE, &info, current);
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}
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void instruction_dump (unsigned int *pc)
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static void instruction_dump(unsigned int *pc)
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{
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int i;
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@ -2115,7 +2072,7 @@ void instruction_dump (unsigned int *pc)
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printk("\n");
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}
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static void user_instruction_dump (unsigned int __user *pc)
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static void user_instruction_dump(unsigned int __user *pc)
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{
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int i;
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unsigned int buf[9];
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@ -1274,10 +1274,6 @@ void __cpuinit sun4v_ktsb_register(void)
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/* paging_init() sets up the page tables */
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extern void cheetah_ecache_flush_init(void);
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extern void sun4v_patch_tlb_handlers(void);
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extern void cpu_probe(void);
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extern void central_probe(void);
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static unsigned long last_valid_pfn;
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@ -1,26 +1,27 @@
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/* $Id: dcu.h,v 1.2 2001/03/01 23:23:33 davem Exp $ */
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#ifndef _SPARC64_DCU_H
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#define _SPARC64_DCU_H
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#include <linux/const.h>
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/* UltraSparc-III Data Cache Unit Control Register */
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#define DCU_CP 0x0002000000000000 /* Physical Cache Enable w/o mmu*/
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#define DCU_CV 0x0001000000000000 /* Virtual Cache Enable w/o mmu */
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#define DCU_ME 0x0000800000000000 /* NC-store Merging Enable */
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#define DCU_RE 0x0000400000000000 /* RAW bypass Enable */
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#define DCU_PE 0x0000200000000000 /* PCache Enable */
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#define DCU_HPE 0x0000100000000000 /* HW prefetch Enable */
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#define DCU_SPE 0x0000080000000000 /* SW prefetch Enable */
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#define DCU_SL 0x0000040000000000 /* Secondary load steering Enab */
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#define DCU_WE 0x0000020000000000 /* WCache enable */
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#define DCU_PM 0x000001fe00000000 /* PA Watchpoint Byte Mask */
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#define DCU_VM 0x00000001fe000000 /* VA Watchpoint Byte Mask */
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#define DCU_PR 0x0000000001000000 /* PA Watchpoint Read Enable */
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#define DCU_PW 0x0000000000800000 /* PA Watchpoint Write Enable */
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#define DCU_VR 0x0000000000400000 /* VA Watchpoint Read Enable */
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#define DCU_VW 0x0000000000200000 /* VA Watchpoint Write Enable */
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#define DCU_DM 0x0000000000000008 /* DMMU Enable */
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#define DCU_IM 0x0000000000000004 /* IMMU Enable */
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#define DCU_DC 0x0000000000000002 /* Data Cache Enable */
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#define DCU_IC 0x0000000000000001 /* Instruction Cache Enable */
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#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */
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#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */
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#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */
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#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */
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#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */
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#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */
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#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */
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#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
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#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */
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#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */
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#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */
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#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */
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#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
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#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */
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#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
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#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */
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#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */
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#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */
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#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */
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#endif /* _SPARC64_DCU_H */
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@ -761,6 +761,8 @@ extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
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extern void pgtable_cache_init(void);
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extern void sun4v_register_fault_status(void);
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extern void sun4v_ktsb_register(void);
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extern void __init cheetah_ecache_flush_init(void);
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extern void sun4v_patch_tlb_handlers(void);
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extern unsigned long cmdline_memory_size;
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