drm/etnaviv: move linear window setup into etnaviv_iommuv1_restore
It is only relevant for the V1 MMU, so we should not do this in the common code. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -568,14 +568,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
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gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
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}
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/* set base addresses */
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
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/* setup the MMU page table pointers */
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/* setup the MMU */
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etnaviv_iommuv1_restore(gpu);
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/* Start command processor */
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@ -202,6 +202,13 @@ void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
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to_etnaviv_domain(gpu->mmu->domain);
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u32 pgtable;
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/* set base addresses */
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
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gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
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/* set page table address in MC */
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pgtable = (u32)etnaviv_domain->pgtable.paddr;
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