ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of broadcasted operation
On versions of the Cortex-A9 prior to r3p0, an interrupted ICIALLUIS operation may prevent the completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing CP15 maintenance operations to be uninterruptible. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
71efb063f4
commit
9a27c27ce4
|
@ -1177,6 +1177,16 @@ config ARM_ERRATA_743622
|
||||||
visible impact on the overall performance or power consumption of the
|
visible impact on the overall performance or power consumption of the
|
||||||
processor.
|
processor.
|
||||||
|
|
||||||
|
config ARM_ERRATA_751472
|
||||||
|
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
|
||||||
|
depends on CPU_V7 && SMP
|
||||||
|
help
|
||||||
|
This option enables the workaround for the 751472 Cortex-A9 (prior
|
||||||
|
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
|
||||||
|
completion of a following broadcasted operation if the second
|
||||||
|
operation is received by a CPU before the ICIALLUIS has completed,
|
||||||
|
potentially leading to corrupted entries in the cache or TLB.
|
||||||
|
|
||||||
config ARM_ERRATA_753970
|
config ARM_ERRATA_753970
|
||||||
bool "ARM errata: cache sync operation may be faulty"
|
bool "ARM errata: cache sync operation may be faulty"
|
||||||
depends on CACHE_PL310
|
depends on CACHE_PL310
|
||||||
|
|
|
@ -264,6 +264,12 @@ __v7_setup:
|
||||||
orreq r10, r10, #1 << 6 @ set bit #6
|
orreq r10, r10, #1 << 6 @ set bit #6
|
||||||
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_751472
|
||||||
|
cmp r6, #0x30 @ present prior to r3p0
|
||||||
|
mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
||||||
|
orrlt r10, r10, #1 << 11 @ set bit #11
|
||||||
|
mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
||||||
|
#endif
|
||||||
|
|
||||||
3: mov r10, #0
|
3: mov r10, #0
|
||||||
#ifdef HARVARD_CACHE
|
#ifdef HARVARD_CACHE
|
||||||
|
|
Loading…
Reference in a new issue