[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers.
The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
f9c97e5d7c
commit
9bb3c227c4
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@ -406,6 +406,18 @@ static void sun4v_irq_disable(unsigned int virt_irq)
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}
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#ifdef CONFIG_PCI_MSI
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static void sun4u_msi_enable(unsigned int virt_irq)
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{
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sun4u_irq_enable(virt_irq);
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unmask_msi_irq(virt_irq);
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}
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static void sun4u_msi_disable(unsigned int virt_irq)
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{
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mask_msi_irq(virt_irq);
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sun4u_irq_disable(virt_irq);
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}
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static void sun4v_msi_enable(unsigned int virt_irq)
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{
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sun4v_irq_enable(virt_irq);
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@ -583,6 +595,17 @@ static struct irq_chip sun4v_irq_ack = {
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};
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#ifdef CONFIG_PCI_MSI
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static struct irq_chip sun4u_msi = {
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.typename = "sun4u+msi",
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.mask = mask_msi_irq,
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.unmask = unmask_msi_irq,
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.enable = sun4u_msi_enable,
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.disable = sun4u_msi_disable,
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.ack = run_pre_handler,
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.end = sun4u_irq_end,
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.set_affinity = sun4u_set_affinity,
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};
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static struct irq_chip sun4v_msi = {
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.typename = "sun4v+msi",
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.mask = mask_msi_irq,
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@ -628,6 +651,7 @@ void irq_install_pre_handler(int virt_irq,
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chip == &sun4v_irq_ack ||
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chip == &sun4v_virq_ack
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#ifdef CONFIG_PCI_MSI
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|| chip == &sun4u_msi
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|| chip == &sun4v_msi
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#endif
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)
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@ -789,6 +813,53 @@ void sun4v_destroy_msi(unsigned int virt_irq)
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{
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virt_irq_free(virt_irq);
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}
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unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
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unsigned int msi_start, unsigned int msi_end,
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unsigned long imap_base, unsigned long iclr_base)
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{
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struct ino_bucket *bucket;
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struct irq_handler_data *data;
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unsigned long sysino;
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unsigned int devino;
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/* Find a free devino in the given range. */
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for (devino = msi_start; devino < msi_end; devino++) {
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sysino = (portid << 6) | devino;
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bucket = &ivector_table[sysino];
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if (!bucket->virt_irq)
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break;
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}
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if (devino >= msi_end)
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return -ENOSPC;
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sysino = (portid << 6) | devino;
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bucket = &ivector_table[sysino];
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bucket->virt_irq = virt_irq_alloc(__irq(bucket));
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*virt_irq_p = bucket->virt_irq;
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set_irq_chip(bucket->virt_irq, &sun4u_msi);
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data = get_irq_chip_data(bucket->virt_irq);
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if (unlikely(data))
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return devino;
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data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
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if (unlikely(!data)) {
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virt_irq_free(*virt_irq_p);
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return -ENOMEM;
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}
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set_irq_chip_data(bucket->virt_irq, data);
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data->imap = (imap_base + (devino * 0x8UL));
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data->iclr = (iclr_base + (devino * 0x8UL));
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return devino;
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}
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void sun4u_destroy_msi(unsigned int virt_irq)
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{
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virt_irq_free(virt_irq);
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}
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#endif
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void ack_bad_irq(unsigned int virt_irq)
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@ -6,9 +6,12 @@
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/irq.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include "pci_impl.h"
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@ -84,6 +87,440 @@ static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
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return 0;
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}
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#ifdef CONFIG_PCI_MSI
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struct pci_msiq_entry {
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u64 word0;
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#define MSIQ_WORD0_RESV 0x8000000000000000UL
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#define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
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#define MSIQ_WORD0_FMT_TYPE_SHIFT 56
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#define MSIQ_WORD0_LEN 0x00ffc00000000000UL
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#define MSIQ_WORD0_LEN_SHIFT 46
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#define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
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#define MSIQ_WORD0_ADDR0_SHIFT 32
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#define MSIQ_WORD0_RID 0x00000000ffff0000UL
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#define MSIQ_WORD0_RID_SHIFT 16
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#define MSIQ_WORD0_DATA0 0x000000000000ffffUL
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#define MSIQ_WORD0_DATA0_SHIFT 0
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#define MSIQ_TYPE_MSG 0x6
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#define MSIQ_TYPE_MSI32 0xb
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#define MSIQ_TYPE_MSI64 0xf
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u64 word1;
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#define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
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#define MSIQ_WORD1_ADDR1_SHIFT 16
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#define MSIQ_WORD1_DATA1 0x000000000000ffffUL
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#define MSIQ_WORD1_DATA1_SHIFT 0
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u64 resv[6];
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};
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/* All MSI registers are offset from pbm->pbm_regs */
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#define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
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#define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
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#define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
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#define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
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#define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
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#define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
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#define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
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#define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
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#define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
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#define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
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#define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
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#define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
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#define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
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#define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
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#define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
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#define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
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#define MSI_MAP_VALID 0x8000000000000000UL
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#define MSI_MAP_EQWR_N 0x4000000000000000UL
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#define MSI_MAP_EQNUM 0x000000000000003fUL
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#define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
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#define MSI_CLEAR_EQWR_N 0x4000000000000000UL
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#define IMONDO_DATA0 0x02C000UL
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#define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
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#define IMONDO_DATA1 0x02C008UL
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#define IMONDO_DATA1_DATA 0xffffffffffffffffUL
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#define MSI_32BIT_ADDR 0x034000UL
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#define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
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#define MSI_64BIT_ADDR 0x034008UL
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#define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
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/* For now this just runs as a pre-handler for the real interrupt handler.
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* So we just walk through the queue and ACK all the entries, update the
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* head pointer, and return.
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*
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* In the longer term it would be nice to do something more integrated
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* wherein we can pass in some of this MSI info to the drivers. This
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* would be most useful for PCIe fabric error messages, although we could
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* invoke those directly from the loop here in order to pass the info around.
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*/
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static void pci_msi_prehandler(unsigned int ino, void *data1, void *data2)
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{
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unsigned long msiqid, orig_head, head, type_fmt, type;
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struct pci_pbm_info *pbm = data1;
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struct pci_msiq_entry *base, *ep;
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msiqid = (unsigned long) data2;
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head = fire_read(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
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orig_head = head;
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base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
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ep = &base[head];
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while ((ep->word0 & MSIQ_WORD0_FMT_TYPE) != 0) {
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unsigned long msi_num;
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type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
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MSIQ_WORD0_FMT_TYPE_SHIFT);
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type = (type_fmt >>3);
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if (unlikely(type != MSIQ_TYPE_MSI32 &&
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type != MSIQ_TYPE_MSI64))
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goto bad_type;
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msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
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MSIQ_WORD0_DATA0_SHIFT);
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fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num),
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MSI_CLEAR_EQWR_N);
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/* Clear the entry. */
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ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
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/* Go to next entry in ring. */
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head++;
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if (head >= pbm->msiq_ent_count)
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head = 0;
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ep = &base[head];
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}
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if (likely(head != orig_head)) {
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/* ACK entries by updating head pointer. */
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fire_write(pbm->pbm_regs +
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EVENT_QUEUE_HEAD(msiqid),
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head);
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}
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return;
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bad_type:
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printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
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return;
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}
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static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
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{
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unsigned long size, bits_per_ulong;
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bits_per_ulong = sizeof(unsigned long) * 8;
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size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
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size /= 8;
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BUG_ON(size % sizeof(unsigned long));
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pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
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if (!pbm->msi_bitmap)
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return -ENOMEM;
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return 0;
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}
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static void msi_bitmap_free(struct pci_pbm_info *pbm)
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{
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kfree(pbm->msi_bitmap);
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pbm->msi_bitmap = NULL;
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}
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static int msi_queue_alloc(struct pci_pbm_info *pbm)
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{
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unsigned long pages, order, i;
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order = get_order(512 * 1024);
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pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
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if (pages == 0UL) {
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printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
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order);
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return -ENOMEM;
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}
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memset((char *)pages, 0, PAGE_SIZE << order);
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pbm->msi_queues = (void *) pages;
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fire_write(pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG,
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(EVENT_QUEUE_BASE_ADDR_ALL_ONES |
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__pa(pbm->msi_queues)));
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fire_write(pbm->pbm_regs + IMONDO_DATA0,
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pbm->portid << 6);
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fire_write(pbm->pbm_regs + IMONDO_DATA1, 0);
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fire_write(pbm->pbm_regs + MSI_32BIT_ADDR,
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pbm->msi32_start);
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fire_write(pbm->pbm_regs + MSI_64BIT_ADDR,
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pbm->msi64_start);
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for (i = 0; i < pbm->msiq_num; i++) {
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fire_write(pbm->pbm_regs + EVENT_QUEUE_HEAD(i), 0);
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fire_write(pbm->pbm_regs + EVENT_QUEUE_TAIL(i), 0);
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}
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return 0;
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}
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static int alloc_msi(struct pci_pbm_info *pbm)
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{
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int i;
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for (i = 0; i < pbm->msi_num; i++) {
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if (!test_and_set_bit(i, pbm->msi_bitmap))
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return i + pbm->msi_first;
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}
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return -ENOENT;
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}
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static void free_msi(struct pci_pbm_info *pbm, int msi_num)
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{
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msi_num -= pbm->msi_first;
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clear_bit(msi_num, pbm->msi_bitmap);
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}
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static int pci_setup_msi_irq(unsigned int *virt_irq_p,
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struct pci_dev *pdev,
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struct msi_desc *entry)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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unsigned long devino, msiqid, cregs, imap_off;
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struct msi_msg msg;
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int msi_num, err;
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u64 val;
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*virt_irq_p = 0;
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msi_num = alloc_msi(pbm);
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if (msi_num < 0)
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return msi_num;
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cregs = (unsigned long) pbm->pbm_regs;
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err = sun4u_build_msi(pbm->portid, virt_irq_p,
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pbm->msiq_first_devino,
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(pbm->msiq_first_devino +
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pbm->msiq_num),
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cregs + 0x001000UL,
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cregs + 0x001400UL);
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if (err < 0)
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goto out_err;
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devino = err;
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imap_off = 0x001000UL + (devino * 0x8UL);
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val = fire_read(pbm->pbm_regs + imap_off);
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val |= (1UL << 63) | (1UL << 6);
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fire_write(pbm->pbm_regs + imap_off, val);
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msiqid = ((devino - pbm->msiq_first_devino) +
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pbm->msiq_first);
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fire_write(pbm->pbm_regs +
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EVENT_QUEUE_CONTROL_SET(msiqid),
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EVENT_QUEUE_CONTROL_SET_EN);
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val = fire_read(pbm->pbm_regs + MSI_MAP(msi_num));
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val &= ~(MSI_MAP_EQNUM);
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val |= msiqid;
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fire_write(pbm->pbm_regs + MSI_MAP(msi_num), val);
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fire_write(pbm->pbm_regs + MSI_CLEAR(msi_num),
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MSI_CLEAR_EQWR_N);
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val = fire_read(pbm->pbm_regs + MSI_MAP(msi_num));
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val |= MSI_MAP_VALID;
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fire_write(pbm->pbm_regs + MSI_MAP(msi_num), val);
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sparc64_set_msi(*virt_irq_p, msi_num);
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if (entry->msi_attrib.is_64) {
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msg.address_hi = pbm->msi64_start >> 32;
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msg.address_lo = pbm->msi64_start & 0xffffffff;
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} else {
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msg.address_hi = 0;
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msg.address_lo = pbm->msi32_start;
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}
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msg.data = msi_num;
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set_irq_msi(*virt_irq_p, entry);
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write_msi_msg(*virt_irq_p, &msg);
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irq_install_pre_handler(*virt_irq_p,
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pci_msi_prehandler,
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pbm, (void *) msiqid);
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return 0;
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out_err:
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free_msi(pbm, msi_num);
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return err;
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}
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static void pci_teardown_msi_irq(unsigned int virt_irq,
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struct pci_dev *pdev)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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unsigned long msiqid, msi_num;
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u64 val;
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msi_num = sparc64_get_msi(virt_irq);
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val = fire_read(pbm->pbm_regs + MSI_MAP(msi_num));
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msiqid = (val & MSI_MAP_EQNUM);
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val &= ~MSI_MAP_VALID;
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fire_write(pbm->pbm_regs + MSI_MAP(msi_num), val);
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fire_write(pbm->pbm_regs + EVENT_QUEUE_CONTROL_CLEAR(msiqid),
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EVENT_QUEUE_CONTROL_CLEAR_DIS);
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free_msi(pbm, msi_num);
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/* The sun4u_destroy_msi() will liberate the devino and thus the MSIQ
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* allocation.
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*/
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sun4u_destroy_msi(virt_irq);
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}
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static void pci_fire_msi_init(struct pci_pbm_info *pbm)
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{
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const u32 *val;
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int len;
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val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
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if (!val || len != 4)
|
||||
goto no_msi;
|
||||
pbm->msiq_num = *val;
|
||||
if (pbm->msiq_num) {
|
||||
const struct msiq_prop {
|
||||
u32 first_msiq;
|
||||
u32 num_msiq;
|
||||
u32 first_devino;
|
||||
} *mqp;
|
||||
const struct msi_range_prop {
|
||||
u32 first_msi;
|
||||
u32 num_msi;
|
||||
} *mrng;
|
||||
const struct addr_range_prop {
|
||||
u32 msi32_high;
|
||||
u32 msi32_low;
|
||||
u32 msi32_len;
|
||||
u32 msi64_high;
|
||||
u32 msi64_low;
|
||||
u32 msi64_len;
|
||||
} *arng;
|
||||
|
||||
val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
|
||||
if (!val || len != 4)
|
||||
goto no_msi;
|
||||
|
||||
pbm->msiq_ent_count = *val;
|
||||
|
||||
mqp = of_get_property(pbm->prom_node,
|
||||
"msi-eq-to-devino", &len);
|
||||
if (!mqp)
|
||||
mqp = of_get_property(pbm->prom_node,
|
||||
"msi-eq-devino", &len);
|
||||
if (!mqp || len != sizeof(struct msiq_prop))
|
||||
goto no_msi;
|
||||
|
||||
pbm->msiq_first = mqp->first_msiq;
|
||||
pbm->msiq_first_devino = mqp->first_devino;
|
||||
|
||||
val = of_get_property(pbm->prom_node, "#msi", &len);
|
||||
if (!val || len != 4)
|
||||
goto no_msi;
|
||||
pbm->msi_num = *val;
|
||||
|
||||
mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
|
||||
if (!mrng || len != sizeof(struct msi_range_prop))
|
||||
goto no_msi;
|
||||
pbm->msi_first = mrng->first_msi;
|
||||
|
||||
val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
|
||||
if (!val || len != 4)
|
||||
goto no_msi;
|
||||
pbm->msi_data_mask = *val;
|
||||
|
||||
val = of_get_property(pbm->prom_node, "msix-data-width", &len);
|
||||
if (!val || len != 4)
|
||||
goto no_msi;
|
||||
pbm->msix_data_width = *val;
|
||||
|
||||
arng = of_get_property(pbm->prom_node, "msi-address-ranges",
|
||||
&len);
|
||||
if (!arng || len != sizeof(struct addr_range_prop))
|
||||
goto no_msi;
|
||||
pbm->msi32_start = ((u64)arng->msi32_high << 32) |
|
||||
(u64) arng->msi32_low;
|
||||
pbm->msi64_start = ((u64)arng->msi64_high << 32) |
|
||||
(u64) arng->msi64_low;
|
||||
pbm->msi32_len = arng->msi32_len;
|
||||
pbm->msi64_len = arng->msi64_len;
|
||||
|
||||
if (msi_bitmap_alloc(pbm))
|
||||
goto no_msi;
|
||||
|
||||
if (msi_queue_alloc(pbm)) {
|
||||
msi_bitmap_free(pbm);
|
||||
goto no_msi;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
|
||||
"devino[0x%x]\n",
|
||||
pbm->name,
|
||||
pbm->msiq_first, pbm->msiq_num,
|
||||
pbm->msiq_ent_count,
|
||||
pbm->msiq_first_devino);
|
||||
printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
|
||||
"width[%u]\n",
|
||||
pbm->name,
|
||||
pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
|
||||
pbm->msix_data_width);
|
||||
printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
|
||||
"addr64[0x%lx:0x%x]\n",
|
||||
pbm->name,
|
||||
pbm->msi32_start, pbm->msi32_len,
|
||||
pbm->msi64_start, pbm->msi64_len);
|
||||
printk(KERN_INFO "%s: MSI queues at RA [%016lx]\n",
|
||||
pbm->name,
|
||||
__pa(pbm->msi_queues));
|
||||
}
|
||||
pbm->setup_msi_irq = pci_setup_msi_irq;
|
||||
pbm->teardown_msi_irq = pci_teardown_msi_irq;
|
||||
|
||||
return;
|
||||
|
||||
no_msi:
|
||||
pbm->msiq_num = 0;
|
||||
printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
|
||||
}
|
||||
#else /* CONFIG_PCI_MSI */
|
||||
static void pci_fire_msi_init(struct pci_pbm_info *pbm)
|
||||
{
|
||||
}
|
||||
#endif /* !(CONFIG_PCI_MSI) */
|
||||
|
||||
/* Based at pbm->controller_regs */
|
||||
#define FIRE_PARITY_CONTROL 0x470010UL
|
||||
#define FIRE_PARITY_ENAB 0x8000000000000000UL
|
||||
|
|
@ -176,6 +613,7 @@ static int pci_fire_pbm_init(struct pci_controller_info *p,
|
|||
{
|
||||
const struct linux_prom64_registers *regs;
|
||||
struct pci_pbm_info *pbm;
|
||||
int err;
|
||||
|
||||
if ((portid & 1) == 0)
|
||||
pbm = &p->pbm_A;
|
||||
|
|
@ -208,7 +646,13 @@ static int pci_fire_pbm_init(struct pci_controller_info *p,
|
|||
|
||||
pci_fire_hw_init(pbm);
|
||||
|
||||
return pci_fire_pbm_iommu_init(pbm);
|
||||
err = pci_fire_pbm_iommu_init(pbm);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
pci_fire_msi_init(pbm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int portid_compare(u32 x, u32 y)
|
||||
|
|
|
|||
|
|
@ -51,6 +51,12 @@ extern unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
|
|||
unsigned int msi_devino_start,
|
||||
unsigned int msi_devino_end);
|
||||
extern void sun4v_destroy_msi(unsigned int virt_irq);
|
||||
extern unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
|
||||
unsigned int msi_devino_start,
|
||||
unsigned int msi_devino_end,
|
||||
unsigned long imap_base,
|
||||
unsigned long iclr_base);
|
||||
extern void sun4u_destroy_msi(unsigned int virt_irq);
|
||||
extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
|
||||
|
||||
extern void sparc64_set_msi(unsigned int virt_irq, u32 msi);
|
||||
|
|
|
|||
Loading…
Reference in a new issue