dmaengine: sprd: Add interrupt support for 2-stage transfer
For 2-stage transfer, some users like Audio still need transaction interrupt to notify when the 2-stage transfer is completed. Thus we should enable 2-stage transfer interrupt to support this feature. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -62,6 +62,8 @@
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/* SPRD_DMA_GLB_2STAGE_GRP register definition */
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#define SPRD_DMA_GLB_2STAGE_EN BIT(24)
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#define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20)
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#define SPRD_DMA_GLB_DEST_INT BIT(22)
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#define SPRD_DMA_GLB_SRC_INT BIT(20)
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#define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19)
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#define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18)
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#define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17)
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@ -135,6 +137,7 @@
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/* define DMA channel mode & trigger mode mask */
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#define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)
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#define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)
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#define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0)
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/* define the DMA transfer step type */
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#define SPRD_DMA_NONE_STEP 0
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@ -190,6 +193,7 @@ struct sprd_dma_chn {
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u32 dev_id;
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enum sprd_dma_chn_mode chn_mode;
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enum sprd_dma_trg_mode trg_mode;
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enum sprd_dma_int_type int_type;
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struct sprd_dma_desc *cur_desc;
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};
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@ -429,6 +433,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
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val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
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val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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if (schan->int_type != SPRD_DMA_NO_INT)
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val |= SPRD_DMA_GLB_SRC_INT;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
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break;
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@ -436,6 +443,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
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val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
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val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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if (schan->int_type != SPRD_DMA_NO_INT)
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val |= SPRD_DMA_GLB_SRC_INT;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
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break;
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@ -443,6 +453,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
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val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
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SPRD_DMA_GLB_DEST_CHN_MASK;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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if (schan->int_type != SPRD_DMA_NO_INT)
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val |= SPRD_DMA_GLB_DEST_INT;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
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break;
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@ -450,6 +463,9 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
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val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
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SPRD_DMA_GLB_DEST_CHN_MASK;
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val |= SPRD_DMA_GLB_2STAGE_EN;
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if (schan->int_type != SPRD_DMA_NO_INT)
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val |= SPRD_DMA_GLB_DEST_INT;
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sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
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break;
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@ -911,11 +927,15 @@ sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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schan->linklist.virt_addr = 0;
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}
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/* Set channel mode and trigger mode for 2-stage transfer */
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/*
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* Set channel mode, interrupt mode and trigger mode for 2-stage
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* transfer.
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*/
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schan->chn_mode =
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(flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
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schan->trg_mode =
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(flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
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schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK;
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sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
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if (!sdesc)
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