staging: rtl8723au: rtl8723a_spec.h: Use BIT() instead of BITx macros
Be consistent and stick to BIT() Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>wifi-calibration
Jes Sorensen
Greg Kroah-Hartman
parent
f4e131dc38
commit
9c45c20da2
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@ -481,11 +481,11 @@
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/* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */
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/* */
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/* EEPROM enable when set 1 */
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#define CmdEEPROM_En BIT5
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#define CmdEEPROM_En BIT(5)
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/* System EEPROM select, 0: boot from E-FUSE,
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1: The EEPROM used is 9346 */
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#define CmdEERPOMSEL BIT4
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#define Cmd9346CR_9356SEL BIT4
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#define CmdEERPOMSEL BIT(4)
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#define Cmd9346CR_9356SEL BIT(4)
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#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
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#define AutoLoadEFUSE CmdEEPROM_En
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@ -493,7 +493,7 @@
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/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
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/* */
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#define GPIOSEL_GPIO 0
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#define GPIOSEL_ENBT BIT5
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#define GPIOSEL_ENBT BIT(5)
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/* */
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/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
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@ -535,43 +535,43 @@ Default: 00b.
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#define RRSR_RSC_UPSUBCHNL 0x400000
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#define RRSR_RSC_LOWSUBCHNL 0x200000
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#define RRSR_SHORT 0x800000
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#define RRSR_1M BIT0
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#define RRSR_2M BIT1
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#define RRSR_5_5M BIT2
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#define RRSR_11M BIT3
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#define RRSR_6M BIT4
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#define RRSR_9M BIT5
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#define RRSR_12M BIT6
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#define RRSR_18M BIT7
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#define RRSR_24M BIT8
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#define RRSR_36M BIT9
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#define RRSR_48M BIT10
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#define RRSR_54M BIT11
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#define RRSR_MCS0 BIT12
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#define RRSR_MCS1 BIT13
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#define RRSR_MCS2 BIT14
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#define RRSR_MCS3 BIT15
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#define RRSR_MCS4 BIT16
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#define RRSR_MCS5 BIT17
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#define RRSR_MCS6 BIT18
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#define RRSR_MCS7 BIT19
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#define BRSR_AckShortPmb BIT23
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#define RRSR_1M BIT(0)
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#define RRSR_2M BIT(1)
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#define RRSR_5_5M BIT(2)
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#define RRSR_11M BIT(3)
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#define RRSR_6M BIT(4)
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#define RRSR_9M BIT(5)
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#define RRSR_12M BIT(6)
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#define RRSR_18M BIT(7)
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#define RRSR_24M BIT(8)
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#define RRSR_36M BIT(9)
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#define RRSR_48M BIT(10)
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#define RRSR_54M BIT(11)
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#define RRSR_MCS0 BIT(12)
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#define RRSR_MCS1 BIT(13)
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#define RRSR_MCS2 BIT(14)
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#define RRSR_MCS3 BIT(15)
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#define RRSR_MCS4 BIT(16)
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#define RRSR_MCS5 BIT(17)
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#define RRSR_MCS6 BIT(18)
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#define RRSR_MCS7 BIT(19)
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#define BRSR_AckShortPmb BIT(23)
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/* CCK ACK: use Short Preamble or not */
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/* */
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/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
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/* */
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#define BW_OPMODE_20MHZ BIT2
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#define BW_OPMODE_5G BIT1
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#define BW_OPMODE_11J BIT0
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#define BW_OPMODE_20MHZ BIT(2)
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#define BW_OPMODE_5G BIT(1)
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#define BW_OPMODE_11J BIT(0)
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/* */
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/* 8192C CAM Config Setting (offset 0x250, 1 byte) */
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/* */
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#define CAM_VALID BIT15
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#define CAM_VALID BIT(15)
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#define CAM_NOTVALID 0x0000
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#define CAM_USEDK BIT5
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#define CAM_USEDK BIT(5)
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#define CAM_CONTENT_COUNT 8
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@ -587,9 +587,9 @@ Default: 00b.
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#define CAM_CONFIG_USEDK true
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#define CAM_CONFIG_NO_USEDK false
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#define CAM_WRITE BIT16
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#define CAM_WRITE BIT(16)
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#define CAM_READ 0x00000000
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#define CAM_POLLINIG BIT31
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#define CAM_POLLINIG BIT(31)
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#define SCR_UseDK 0x01
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#define SCR_TxSecEnable 0x02
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@ -605,54 +605,54 @@ Default: 00b.
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#define IMR8190_DISABLED 0x0
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/* IMR DW0 Bit 0-31 */
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#define IMR_BCNDMAINT6 BIT31 /* Beacon DMA Interrupt 6 */
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#define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */
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#define IMR_BCNDMAINT4 BIT29 /* Beacon DMA Interrupt 4 */
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#define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */
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#define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */
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#define IMR_BCNDMAINT1 BIT26 /* Beacon DMA Interrupt 1 */
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#define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK
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#define IMR_BCNDMAINT6 BIT(31) /* Beacon DMA Interrupt 6 */
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#define IMR_BCNDMAINT5 BIT(30) /* Beacon DMA Interrupt 5 */
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#define IMR_BCNDMAINT4 BIT(29) /* Beacon DMA Interrupt 4 */
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#define IMR_BCNDMAINT3 BIT(28) /* Beacon DMA Interrupt 3 */
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#define IMR_BCNDMAINT2 BIT(27) /* Beacon DMA Interrupt 2 */
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#define IMR_BCNDMAINT1 BIT(26) /* Beacon DMA Interrupt 1 */
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#define IMR_BCNDOK8 BIT(25) /* Beacon Queue DMA OK
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Interrupt 8 */
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#define IMR_BCNDOK7 BIT24 /* Beacon Queue DMA OK
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#define IMR_BCNDOK7 BIT(24) /* Beacon Queue DMA OK
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Interrupt 7 */
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#define IMR_BCNDOK6 BIT23 /* Beacon Queue DMA OK
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#define IMR_BCNDOK6 BIT(23) /* Beacon Queue DMA OK
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Interrupt 6 */
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#define IMR_BCNDOK5 BIT22 /* Beacon Queue DMA OK
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#define IMR_BCNDOK5 BIT(22) /* Beacon Queue DMA OK
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Interrupt 5 */
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#define IMR_BCNDOK4 BIT21 /* Beacon Queue DMA OK
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#define IMR_BCNDOK4 BIT(21) /* Beacon Queue DMA OK
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Interrupt 4 */
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#define IMR_BCNDOK3 BIT20 /* Beacon Queue DMA OK
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#define IMR_BCNDOK3 BIT(20) /* Beacon Queue DMA OK
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Interrupt 3 */
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#define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK
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#define IMR_BCNDOK2 BIT(19) /* Beacon Queue DMA OK
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Interrupt 2 */
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#define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK
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#define IMR_BCNDOK1 BIT(18) /* Beacon Queue DMA OK
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Interrupt 1 */
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#define IMR_TIMEOUT2 BIT17 /* Timeout interrupt 2 */
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#define IMR_TIMEOUT1 BIT16 /* Timeout interrupt 1 */
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#define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */
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#define IMR_PSTIMEOUT BIT14 /* Power save time out
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#define IMR_TIMEOUT2 BIT(17) /* Timeout interrupt 2 */
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#define IMR_TIMEOUT1 BIT(16) /* Timeout interrupt 1 */
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#define IMR_TXFOVW BIT(15) /* Transmit FIFO Overflow */
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#define IMR_PSTIMEOUT BIT(14) /* Power save time out
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interrupt */
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#define IMR_BcnInt BIT13 /* Beacon DMA Interrupt 0 */
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#define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */
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#define IMR_RDU BIT11 /* Receive Descriptor
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#define IMR_BcnInt BIT(13) /* Beacon DMA Interrupt 0 */
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#define IMR_RXFOVW BIT(12) /* Receive FIFO Overflow */
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#define IMR_RDU BIT(11) /* Receive Descriptor
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Unavailable */
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#define IMR_ATIMEND BIT10 /* For 92C,ATIM Window
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#define IMR_ATIMEND BIT(10) /* For 92C,ATIM Window
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End Interrupt */
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#define IMR_BDOK BIT9 /* Beacon Queue DMA OK
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#define IMR_BDOK BIT(9) /* Beacon Queue DMA OK
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Interrup */
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#define IMR_HIGHDOK BIT8 /* High Queue DMA OK
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#define IMR_HIGHDOK BIT(8) /* High Queue DMA OK
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Interrupt */
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#define IMR_TBDOK BIT7 /* Transmit Beacon OK
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#define IMR_TBDOK BIT(7) /* Transmit Beacon OK
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interrup */
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#define IMR_MGNTDOK BIT6 /* Management Queue DMA OK
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#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK
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Interrupt */
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#define IMR_TBDER BIT5 /* For 92C,Transmit Beacon
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#define IMR_TBDER BIT(5) /* For 92C,Transmit Beacon
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Error Interrupt */
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#define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */
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#define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */
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#define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */
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#define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */
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#define IMR_ROK BIT0 /* Receive DMA OK Interrupt */
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#define IMR_BKDOK BIT(4) /* AC_BK DMA OK Interrupt */
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#define IMR_BEDOK BIT(3) /* AC_BE DMA OK Interrupt */
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#define IMR_VIDOK BIT(2) /* AC_VI DMA OK Interrupt */
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#define IMR_VODOK BIT(1) /* AC_VO DMA Interrupt */
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#define IMR_ROK BIT(0) /* Receive DMA OK Interrupt */
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#define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW)
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#define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK| \
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@ -660,14 +660,14 @@ Default: 00b.
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IMR_BDOK)
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/* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */
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#define IMR_BcnInt_E BIT12
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#define IMR_TXERR BIT11
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#define IMR_RXERR BIT10
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#define IMR_C2HCMD BIT9
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#define IMR_CPWM BIT8
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#define IMR_BcnInt_E BIT(12)
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#define IMR_TXERR BIT(11)
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#define IMR_RXERR BIT(10)
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#define IMR_C2HCMD BIT(9)
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#define IMR_CPWM BIT(8)
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/* RSVD [2-7] */
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#define IMR_OCPINT BIT1
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#define IMR_WLANOFF BIT0
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#define IMR_OCPINT BIT(1)
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#define IMR_WLANOFF BIT(0)
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/* 8192C EEPROM/EFUSE share register definition. */
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@ -913,35 +913,35 @@ Current IOREG MAP
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/* */
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/* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */
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/* */
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#define RCR_APPFCS BIT31 /* WMAC append FCS after payload*/
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#define RCR_APP_MIC BIT30
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#define RCR_APP_PHYSTS BIT28
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#define RCR_APP_ICV BIT29
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#define RCR_APP_PHYST_RXFF BIT28
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#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */
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#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */
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#define RCR_LSIGEN BIT23
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#define RCR_MFBEN BIT22
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#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */
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#define RCR_AMF BIT13 /* Accept management type frame */
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#define RCR_ACF BIT12 /* Accept control type frame */
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#define RCR_ADF BIT11 /* Accept data type frame */
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#define RCR_AICV BIT9 /* Accept ICV error packet */
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#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
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#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet
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#define RCR_APPFCS BIT(31) /* WMAC append FCS after payload*/
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#define RCR_APP_MIC BIT(30)
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#define RCR_APP_PHYSTS BIT(28)
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#define RCR_APP_ICV BIT(29)
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#define RCR_APP_PHYST_RXFF BIT(28)
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#define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */
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#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */
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#define RCR_LSIGEN BIT(23)
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#define RCR_MFBEN BIT(22)
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#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
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#define RCR_AMF BIT(13) /* Accept management type frame */
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#define RCR_ACF BIT(12) /* Accept control type frame */
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#define RCR_ADF BIT(11) /* Accept data type frame */
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#define RCR_AICV BIT(9) /* Accept ICV error packet */
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#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */
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#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet
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(Rx beacon, probe rsp) */
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#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet
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#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match packet
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(Data) */
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#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match
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packet */
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#define RCR_APWRMGT BIT5 /* Accept power management
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#define RCR_APWRMGT BIT(5) /* Accept power management
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packet */
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#define RCR_ADD3 BIT4 /* Accept address 3 match
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#define RCR_ADD3 BIT(4) /* Accept address 3 match
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packet */
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#define RCR_AB BIT3 /* Accept broadcast packet */
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#define RCR_AM BIT2 /* Accept multicast packet */
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#define RCR_APM BIT1 /* Accept physical match packet */
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#define RCR_AAP BIT0 /* Accept all unicast packet */
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#define RCR_AB BIT(3) /* Accept broadcast packet */
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#define RCR_AM BIT(2) /* Accept multicast packet */
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#define RCR_APM BIT(1) /* Accept physical match packet */
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#define RCR_AAP BIT(0) /* Accept all unicast packet */
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#define RCR_MXDMA_OFFSET 8
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#define RCR_FIFO_OFFSET 13
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@ -1714,33 +1714,33 @@ Current IOREG MAP
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/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
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/* Enable GPIO[9] as WiFi HW PDn source */
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#define WL_HWPDN_EN BIT0
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#define WL_HWPDN_EN BIT(0)
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/* WiFi HW PDn polarity control */
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#define WL_HWPDN_SL BIT1
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#define WL_HWPDN_SL BIT(1)
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/* WiFi function enable */
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#define WL_FUNC_EN BIT2
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#define WL_FUNC_EN BIT(2)
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/* Enable GPIO[9] as WiFi RF HW PDn source */
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#define WL_HWROF_EN BIT3
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#define WL_HWROF_EN BIT(3)
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/* Enable GPIO[11] as BT HW PDn source */
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#define BT_HWPDN_EN BIT16
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#define BT_HWPDN_EN BIT(16)
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/* BT HW PDn polarity control */
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#define BT_HWPDN_SL BIT17
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#define BT_HWPDN_SL BIT(17)
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/* BT function enable */
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#define BT_FUNC_EN BIT18
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#define BT_FUNC_EN BIT(18)
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/* Enable GPIO[11] as BT/GPS RF HW PDn source */
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#define BT_HWROF_EN BIT19
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#define BT_HWROF_EN BIT(19)
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/* Enable GPIO[10] as GPS HW PDn source */
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#define GPS_HWPDN_EN BIT20
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#define GPS_HWPDN_EN BIT(20)
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/* GPS HW PDn polarity control */
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#define GPS_HWPDN_SL BIT21
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#define GPS_HWPDN_SL BIT(21)
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/* GPS function enable */
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#define GPS_FUNC_EN BIT22
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#define GPS_FUNC_EN BIT(22)
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/* 3 REG_LIFECTRL_CTRL */
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#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3
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#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
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#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
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#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0
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#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3)
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#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2)
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#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1)
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#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0)
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#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */
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@ -1933,7 +1933,7 @@ Current IOREG MAP
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HSISR_GPIO9_INT)
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/* 2 MCUFWDL */
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#define RAM_DL_SEL BIT7 /* 1:RAM, 0:ROM */
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#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */
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/* 2 HPON_FSM */
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@ -2083,60 +2083,60 @@ Current IOREG MAP
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/* USB interrupt */
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#define UHIMR_TIMEOUT2 BIT31
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#define UHIMR_TIMEOUT1 BIT30
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#define UHIMR_PSTIMEOUT BIT29
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#define UHIMR_GTINT4 BIT28
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#define UHIMR_GTINT3 BIT27
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#define UHIMR_TXBCNERR BIT26
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#define UHIMR_TXBCNOK BIT25
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#define UHIMR_TSF_BIT32_TOGGLE BIT24
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#define UHIMR_BCNDMAINT3 BIT23
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#define UHIMR_BCNDMAINT2 BIT22
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#define UHIMR_BCNDMAINT1 BIT21
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#define UHIMR_BCNDMAINT0 BIT20
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#define UHIMR_BCNDOK3 BIT19
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#define UHIMR_BCNDOK2 BIT18
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#define UHIMR_BCNDOK1 BIT17
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#define UHIMR_BCNDOK0 BIT16
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#define UHIMR_HSISR_IND BIT15
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#define UHIMR_BCNDMAINT_E BIT14
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/* RSVD BIT13 */
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#define UHIMR_CTW_END BIT12
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/* RSVD BIT11 */
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#define UHIMR_C2HCMD BIT10
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#define UHIMR_CPWM2 BIT9
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#define UHIMR_CPWM BIT8
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#define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK
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#define UHIMR_TIMEOUT2 BIT(31)
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#define UHIMR_TIMEOUT1 BIT(30)
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#define UHIMR_PSTIMEOUT BIT(29)
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#define UHIMR_GTINT4 BIT(28)
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#define UHIMR_GTINT3 BIT(27)
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#define UHIMR_TXBCNERR BIT(26)
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#define UHIMR_TXBCNOK BIT(25)
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#define UHIMR_TSF_BIT32_TOGGLE BIT(24)
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#define UHIMR_BCNDMAINT3 BIT(23)
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#define UHIMR_BCNDMAINT2 BIT(22)
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#define UHIMR_BCNDMAINT1 BIT(21)
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#define UHIMR_BCNDMAINT0 BIT(20)
|
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#define UHIMR_BCNDOK3 BIT(19)
|
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#define UHIMR_BCNDOK2 BIT(18)
|
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#define UHIMR_BCNDOK1 BIT(17)
|
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#define UHIMR_BCNDOK0 BIT(16)
|
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#define UHIMR_HSISR_IND BIT(15)
|
||||
#define UHIMR_BCNDMAINT_E BIT(14)
|
||||
/* RSVD BIT(13) */
|
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#define UHIMR_CTW_END BIT(12)
|
||||
/* RSVD BIT(11) */
|
||||
#define UHIMR_C2HCMD BIT(10)
|
||||
#define UHIMR_CPWM2 BIT(9)
|
||||
#define UHIMR_CPWM BIT(8)
|
||||
#define UHIMR_HIGHDOK BIT(7) /* High Queue DMA OK
|
||||
Interrupt */
|
||||
#define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK
|
||||
#define UHIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
|
||||
Interrupt */
|
||||
#define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */
|
||||
#define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */
|
||||
#define UHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */
|
||||
#define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */
|
||||
#define UHIMR_RDU BIT1 /* Receive Descriptor
|
||||
#define UHIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
|
||||
#define UHIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
|
||||
#define UHIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
|
||||
#define UHIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
|
||||
#define UHIMR_RDU BIT(1) /* Receive Descriptor
|
||||
Unavailable */
|
||||
#define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */
|
||||
#define UHIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
|
||||
|
||||
/* USB Host Interrupt Status Extension bit */
|
||||
#define UHIMR_BCNDMAINT7 BIT23
|
||||
#define UHIMR_BCNDMAINT6 BIT22
|
||||
#define UHIMR_BCNDMAINT5 BIT21
|
||||
#define UHIMR_BCNDMAINT4 BIT20
|
||||
#define UHIMR_BCNDOK7 BIT19
|
||||
#define UHIMR_BCNDOK6 BIT18
|
||||
#define UHIMR_BCNDOK5 BIT17
|
||||
#define UHIMR_BCNDOK4 BIT16
|
||||
#define UHIMR_BCNDMAINT7 BIT(23)
|
||||
#define UHIMR_BCNDMAINT6 BIT(22)
|
||||
#define UHIMR_BCNDMAINT5 BIT(21)
|
||||
#define UHIMR_BCNDMAINT4 BIT(20)
|
||||
#define UHIMR_BCNDOK7 BIT(19)
|
||||
#define UHIMR_BCNDOK6 BIT(18)
|
||||
#define UHIMR_BCNDOK5 BIT(17)
|
||||
#define UHIMR_BCNDOK4 BIT(16)
|
||||
/* bit14-15: RSVD */
|
||||
#define UHIMR_ATIMEND_E BIT13
|
||||
#define UHIMR_ATIMEND BIT12
|
||||
#define UHIMR_TXERR BIT11
|
||||
#define UHIMR_RXERR BIT10
|
||||
#define UHIMR_TXFOVW BIT9
|
||||
#define UHIMR_RXFOVW BIT8
|
||||
#define UHIMR_ATIMEND_E BIT(13)
|
||||
#define UHIMR_ATIMEND BIT(12)
|
||||
#define UHIMR_TXERR BIT(11)
|
||||
#define UHIMR_RXERR BIT(10)
|
||||
#define UHIMR_TXFOVW BIT(9)
|
||||
#define UHIMR_RXFOVW BIT(8)
|
||||
/* bit2-7: RSVD */
|
||||
#define UHIMR_OCPINT BIT1
|
||||
#define UHIMR_OCPINT BIT(1)
|
||||
/* bit0: RSVD */
|
||||
|
||||
#define REG_USB_HIMR 0xFE38
|
||||
|
|
|
|||
Loading…
Reference in New Issue