MIPS: kernel: traps: Add MIPS R6 related definitions
Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
parent
515a6393db
commit
9c7d576868
|
@ -1649,7 +1649,7 @@ asmlinkage void cache_parity_error(void)
|
|||
printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
|
||||
reg_val & (1<<30) ? "secondary" : "primary",
|
||||
reg_val & (1<<31) ? "data" : "insn");
|
||||
if (cpu_has_mips_r2 &&
|
||||
if ((cpu_has_mips_r2_r6) &&
|
||||
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
|
||||
pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
|
||||
reg_val & (1<<29) ? "ED " : "",
|
||||
|
@ -1689,7 +1689,7 @@ asmlinkage void do_ftlb(void)
|
|||
unsigned int reg_val;
|
||||
|
||||
/* For the moment, report the problem and hang. */
|
||||
if (cpu_has_mips_r2 &&
|
||||
if ((cpu_has_mips_r2_r6) &&
|
||||
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
|
||||
pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
|
||||
read_c0_ecc());
|
||||
|
@ -1978,7 +1978,7 @@ static void configure_hwrena(void)
|
|||
{
|
||||
unsigned int hwrena = cpu_hwrena_impl_bits;
|
||||
|
||||
if (cpu_has_mips_r2)
|
||||
if (cpu_has_mips_r2_r6)
|
||||
hwrena |= 0x0000000f;
|
||||
|
||||
if (!noulri && cpu_has_userlocal)
|
||||
|
@ -2022,7 +2022,7 @@ void per_cpu_trap_init(bool is_boot_cpu)
|
|||
* o read IntCtl.IPTI to determine the timer interrupt
|
||||
* o read IntCtl.IPPCI to determine the performance counter interrupt
|
||||
*/
|
||||
if (cpu_has_mips_r2) {
|
||||
if (cpu_has_mips_r2_r6) {
|
||||
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
|
||||
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
|
||||
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
|
||||
|
@ -2113,7 +2113,7 @@ void __init trap_init(void)
|
|||
#else
|
||||
ebase = CKSEG0;
|
||||
#endif
|
||||
if (cpu_has_mips_r2)
|
||||
if (cpu_has_mips_r2_r6)
|
||||
ebase += (read_c0_ebase() & 0x3ffff000);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue